1 #include "perf_event_intel_uncore.h"
3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
4 static struct intel_uncore_type **msr_uncores = empty_uncore;
5 static struct intel_uncore_type **pci_uncores = empty_uncore;
6 /* pci bus to socket mapping */
7 static int pcibus_to_physid[256] = { [0 ... 255] = -1, };
9 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
11 /* mask of cpus that collect uncore events */
12 static cpumask_t uncore_cpu_mask;
14 /* constraint for the fixed counter */
15 static struct event_constraint constraint_fixed =
16 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
18 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
19 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
20 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
21 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
22 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
23 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
24 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
25 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
26 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
27 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
28 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
30 /* Sandy Bridge-EP uncore support */
31 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
33 struct pci_dev *pdev = box->pci_dev;
34 int box_ctl = uncore_pci_box_ctl(box);
37 pci_read_config_dword(pdev, box_ctl, &config);
38 config |= SNBEP_PMON_BOX_CTL_FRZ;
39 pci_write_config_dword(pdev, box_ctl, config);
42 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
44 struct pci_dev *pdev = box->pci_dev;
45 int box_ctl = uncore_pci_box_ctl(box);
48 pci_read_config_dword(pdev, box_ctl, &config);
49 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
50 pci_write_config_dword(pdev, box_ctl, config);
53 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box,
54 struct perf_event *event)
56 struct pci_dev *pdev = box->pci_dev;
57 struct hw_perf_event *hwc = &event->hw;
59 pci_write_config_dword(pdev, hwc->config_base, hwc->config |
63 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
64 struct perf_event *event)
66 struct pci_dev *pdev = box->pci_dev;
67 struct hw_perf_event *hwc = &event->hw;
69 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
72 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
73 struct perf_event *event)
75 struct pci_dev *pdev = box->pci_dev;
76 struct hw_perf_event *hwc = &event->hw;
79 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
80 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
84 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
86 struct pci_dev *pdev = box->pci_dev;
87 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
88 SNBEP_PMON_BOX_CTL_INT);
91 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
96 msr = uncore_msr_box_ctl(box);
99 config |= SNBEP_PMON_BOX_CTL_FRZ;
105 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
110 msr = uncore_msr_box_ctl(box);
113 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
119 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
120 struct perf_event *event)
122 struct hw_perf_event *hwc = &event->hw;
124 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
127 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
128 struct perf_event *event)
130 struct hw_perf_event *hwc = &event->hw;
132 wrmsrl(hwc->config_base, hwc->config);
135 static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
136 struct perf_event *event)
138 struct hw_perf_event *hwc = &event->hw;
141 rdmsrl(hwc->event_base, count);
145 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
147 unsigned msr = uncore_msr_box_ctl(box);
149 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
152 static struct attribute *snbep_uncore_formats_attr[] = {
153 &format_attr_event.attr,
154 &format_attr_umask.attr,
155 &format_attr_edge.attr,
156 &format_attr_inv.attr,
157 &format_attr_thresh8.attr,
161 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
162 &format_attr_event.attr,
163 &format_attr_umask.attr,
164 &format_attr_edge.attr,
165 &format_attr_inv.attr,
166 &format_attr_thresh5.attr,
170 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
171 &format_attr_event.attr,
172 &format_attr_occ_sel.attr,
173 &format_attr_edge.attr,
174 &format_attr_inv.attr,
175 &format_attr_thresh5.attr,
176 &format_attr_occ_invert.attr,
177 &format_attr_occ_edge.attr,
181 static struct uncore_event_desc snbep_uncore_imc_events[] = {
182 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0xff"),
183 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
184 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
185 { /* end: all zeroes */ },
188 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
189 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
190 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
191 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x02,umask=0x08"),
192 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x03,umask=0x04"),
193 { /* end: all zeroes */ },
196 static struct attribute_group snbep_uncore_format_group = {
198 .attrs = snbep_uncore_formats_attr,
201 static struct attribute_group snbep_uncore_ubox_format_group = {
203 .attrs = snbep_uncore_ubox_formats_attr,
206 static struct attribute_group snbep_uncore_pcu_format_group = {
208 .attrs = snbep_uncore_pcu_formats_attr,
211 static struct intel_uncore_ops snbep_uncore_msr_ops = {
212 .init_box = snbep_uncore_msr_init_box,
213 .disable_box = snbep_uncore_msr_disable_box,
214 .enable_box = snbep_uncore_msr_enable_box,
215 .disable_event = snbep_uncore_msr_disable_event,
216 .enable_event = snbep_uncore_msr_enable_event,
217 .read_counter = snbep_uncore_msr_read_counter,
220 static struct intel_uncore_ops snbep_uncore_pci_ops = {
221 .init_box = snbep_uncore_pci_init_box,
222 .disable_box = snbep_uncore_pci_disable_box,
223 .enable_box = snbep_uncore_pci_enable_box,
224 .disable_event = snbep_uncore_pci_disable_event,
225 .enable_event = snbep_uncore_pci_enable_event,
226 .read_counter = snbep_uncore_pci_read_counter,
229 static struct event_constraint snbep_uncore_cbox_constraints[] = {
230 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
231 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
232 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
233 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
234 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
235 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
236 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
237 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
238 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
239 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
240 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
241 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
242 UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
243 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
244 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
245 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
246 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
247 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
248 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
249 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
250 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
251 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
252 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
253 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
254 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
258 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
259 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
260 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
261 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
262 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
263 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
264 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
265 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
266 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
267 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
268 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
272 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
273 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
274 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
275 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
276 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
277 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
278 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
279 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
280 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
281 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
282 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
283 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
284 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
285 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
286 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
287 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
288 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
289 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
290 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
294 static struct intel_uncore_type snbep_uncore_ubox = {
299 .fixed_ctr_bits = 48,
300 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
301 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
302 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
303 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
304 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
305 .ops = &snbep_uncore_msr_ops,
306 .format_group = &snbep_uncore_ubox_format_group,
309 static struct intel_uncore_type snbep_uncore_cbox = {
314 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
315 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
316 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
317 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
318 .msr_offset = SNBEP_CBO_MSR_OFFSET,
319 .constraints = snbep_uncore_cbox_constraints,
320 .ops = &snbep_uncore_msr_ops,
321 .format_group = &snbep_uncore_format_group,
324 static struct intel_uncore_type snbep_uncore_pcu = {
329 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
330 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
331 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
332 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
333 .ops = &snbep_uncore_msr_ops,
334 .format_group = &snbep_uncore_pcu_format_group,
337 static struct intel_uncore_type *snbep_msr_uncores[] = {
344 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
345 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
346 .event_ctl = SNBEP_PCI_PMON_CTL0, \
347 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
348 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
349 .ops = &snbep_uncore_pci_ops, \
350 .format_group = &snbep_uncore_format_group
352 static struct intel_uncore_type snbep_uncore_ha = {
357 SNBEP_UNCORE_PCI_COMMON_INIT(),
360 static struct intel_uncore_type snbep_uncore_imc = {
365 .fixed_ctr_bits = 48,
366 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
367 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
368 .event_descs = snbep_uncore_imc_events,
369 SNBEP_UNCORE_PCI_COMMON_INIT(),
372 static struct intel_uncore_type snbep_uncore_qpi = {
377 .event_descs = snbep_uncore_qpi_events,
378 SNBEP_UNCORE_PCI_COMMON_INIT(),
382 static struct intel_uncore_type snbep_uncore_r2pcie = {
387 .constraints = snbep_uncore_r2pcie_constraints,
388 SNBEP_UNCORE_PCI_COMMON_INIT(),
391 static struct intel_uncore_type snbep_uncore_r3qpi = {
396 .constraints = snbep_uncore_r3qpi_constraints,
397 SNBEP_UNCORE_PCI_COMMON_INIT(),
400 static struct intel_uncore_type *snbep_pci_uncores[] = {
404 &snbep_uncore_r2pcie,
409 static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
411 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
412 .driver_data = (unsigned long)&snbep_uncore_ha,
415 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
416 .driver_data = (unsigned long)&snbep_uncore_imc,
419 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
420 .driver_data = (unsigned long)&snbep_uncore_imc,
423 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
424 .driver_data = (unsigned long)&snbep_uncore_imc,
427 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
428 .driver_data = (unsigned long)&snbep_uncore_imc,
431 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
432 .driver_data = (unsigned long)&snbep_uncore_qpi,
435 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
436 .driver_data = (unsigned long)&snbep_uncore_qpi,
439 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
440 .driver_data = (unsigned long)&snbep_uncore_r2pcie,
443 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
444 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
447 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
448 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
450 { /* end: all zeroes */ }
453 static struct pci_driver snbep_uncore_pci_driver = {
454 .name = "snbep_uncore",
455 .id_table = snbep_uncore_pci_ids,
459 * build pci bus to socket mapping
461 static void snbep_pci2phy_map_init(void)
463 struct pci_dev *ubox_dev = NULL;
468 /* find the UBOX device */
469 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
470 PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
474 bus = ubox_dev->bus->number;
475 /* get the Node ID of the local register */
476 pci_read_config_dword(ubox_dev, 0x40, &config);
478 /* get the Node ID mapping */
479 pci_read_config_dword(ubox_dev, 0x54, &config);
481 * every three bits in the Node ID mapping register maps
482 * to a particular node.
484 for (i = 0; i < 8; i++) {
485 if (nodeid == ((config >> (3 * i)) & 0x7)) {
486 pcibus_to_physid[bus] = i;
493 /* end of Sandy Bridge-EP uncore support */
496 /* Sandy Bridge uncore support */
497 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
498 struct perf_event *event)
500 struct hw_perf_event *hwc = &event->hw;
502 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
503 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
505 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
508 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box,
509 struct perf_event *event)
511 wrmsrl(event->hw.config_base, 0);
514 static u64 snb_uncore_msr_read_counter(struct intel_uncore_box *box,
515 struct perf_event *event)
518 rdmsrl(event->hw.event_base, count);
522 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
524 if (box->pmu->pmu_idx == 0) {
525 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
526 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
530 static struct attribute *snb_uncore_formats_attr[] = {
531 &format_attr_event.attr,
532 &format_attr_umask.attr,
533 &format_attr_edge.attr,
534 &format_attr_inv.attr,
535 &format_attr_cmask5.attr,
539 static struct attribute_group snb_uncore_format_group = {
541 .attrs = snb_uncore_formats_attr,
544 static struct intel_uncore_ops snb_uncore_msr_ops = {
545 .init_box = snb_uncore_msr_init_box,
546 .disable_event = snb_uncore_msr_disable_event,
547 .enable_event = snb_uncore_msr_enable_event,
548 .read_counter = snb_uncore_msr_read_counter,
551 static struct event_constraint snb_uncore_cbox_constraints[] = {
552 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
553 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
557 static struct intel_uncore_type snb_uncore_cbox = {
562 .fixed_ctr_bits = 48,
563 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
564 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
565 .fixed_ctr = SNB_UNC_FIXED_CTR,
566 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
568 .event_mask = SNB_UNC_RAW_EVENT_MASK,
569 .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
570 .constraints = snb_uncore_cbox_constraints,
571 .ops = &snb_uncore_msr_ops,
572 .format_group = &snb_uncore_format_group,
575 static struct intel_uncore_type *snb_msr_uncores[] = {
579 /* end of Sandy Bridge uncore support */
581 /* Nehalem uncore support */
582 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
584 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
587 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
589 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL,
590 NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
593 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box,
594 struct perf_event *event)
596 struct hw_perf_event *hwc = &event->hw;
598 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
599 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
601 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
604 static struct attribute *nhm_uncore_formats_attr[] = {
605 &format_attr_event.attr,
606 &format_attr_umask.attr,
607 &format_attr_edge.attr,
608 &format_attr_inv.attr,
609 &format_attr_cmask8.attr,
613 static struct attribute_group nhm_uncore_format_group = {
615 .attrs = nhm_uncore_formats_attr,
618 static struct uncore_event_desc nhm_uncore_events[] = {
619 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0xff"),
620 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
621 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
622 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
623 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
624 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
625 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
626 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
627 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
628 { /* end: all zeroes */ },
631 static struct intel_uncore_ops nhm_uncore_msr_ops = {
632 .disable_box = nhm_uncore_msr_disable_box,
633 .enable_box = nhm_uncore_msr_enable_box,
634 .disable_event = snb_uncore_msr_disable_event,
635 .enable_event = nhm_uncore_msr_enable_event,
636 .read_counter = snb_uncore_msr_read_counter,
639 static struct intel_uncore_type nhm_uncore = {
644 .fixed_ctr_bits = 48,
645 .event_ctl = NHM_UNC_PERFEVTSEL0,
646 .perf_ctr = NHM_UNC_UNCORE_PMC0,
647 .fixed_ctr = NHM_UNC_FIXED_CTR,
648 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL,
649 .event_mask = NHM_UNC_RAW_EVENT_MASK,
650 .event_descs = nhm_uncore_events,
651 .ops = &nhm_uncore_msr_ops,
652 .format_group = &nhm_uncore_format_group,
655 static struct intel_uncore_type *nhm_msr_uncores[] = {
659 /* end of Nehalem uncore support */
661 static void uncore_assign_hw_event(struct intel_uncore_box *box,
662 struct perf_event *event, int idx)
664 struct hw_perf_event *hwc = &event->hw;
667 hwc->last_tag = ++box->tags[idx];
669 if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
670 hwc->event_base = uncore_fixed_ctr(box);
671 hwc->config_base = uncore_fixed_ctl(box);
675 hwc->config_base = uncore_event_ctl(box, hwc->idx);
676 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
679 static void uncore_perf_event_update(struct intel_uncore_box *box,
680 struct perf_event *event)
682 u64 prev_count, new_count, delta;
685 if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
686 shift = 64 - uncore_fixed_ctr_bits(box);
688 shift = 64 - uncore_perf_ctr_bits(box);
690 /* the hrtimer might modify the previous event value */
692 prev_count = local64_read(&event->hw.prev_count);
693 new_count = uncore_read_counter(box, event);
694 if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
697 delta = (new_count << shift) - (prev_count << shift);
700 local64_add(delta, &event->count);
704 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
705 * for SandyBridge. So we use hrtimer to periodically poll the counter
708 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
710 struct intel_uncore_box *box;
714 box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
715 if (!box->n_active || box->cpu != smp_processor_id())
716 return HRTIMER_NORESTART;
718 * disable local interrupt to prevent uncore_pmu_event_start/stop
719 * to interrupt the update process
721 local_irq_save(flags);
723 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
724 uncore_perf_event_update(box, box->events[bit]);
726 local_irq_restore(flags);
728 hrtimer_forward_now(hrtimer, ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL));
729 return HRTIMER_RESTART;
732 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
734 __hrtimer_start_range_ns(&box->hrtimer,
735 ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL), 0,
736 HRTIMER_MODE_REL_PINNED, 0);
739 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
741 hrtimer_cancel(&box->hrtimer);
744 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
746 hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
747 box->hrtimer.function = uncore_pmu_hrtimer;
750 struct intel_uncore_box *uncore_alloc_box(int cpu)
752 struct intel_uncore_box *box;
754 box = kmalloc_node(sizeof(*box), GFP_KERNEL | __GFP_ZERO,
759 uncore_pmu_init_hrtimer(box);
760 atomic_set(&box->refcnt, 1);
767 static struct intel_uncore_box *
768 uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
770 static struct intel_uncore_box *box;
772 box = *per_cpu_ptr(pmu->box, cpu);
776 raw_spin_lock(&uncore_box_lock);
777 list_for_each_entry(box, &pmu->box_list, list) {
778 if (box->phys_id == topology_physical_package_id(cpu)) {
779 atomic_inc(&box->refcnt);
780 *per_cpu_ptr(pmu->box, cpu) = box;
784 raw_spin_unlock(&uncore_box_lock);
786 return *per_cpu_ptr(pmu->box, cpu);
789 static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
791 return container_of(event->pmu, struct intel_uncore_pmu, pmu);
794 static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
797 * perf core schedules event on the basis of cpu, uncore events are
798 * collected by one of the cpus inside a physical package.
800 return uncore_pmu_to_box(uncore_event_to_pmu(event),
804 static int uncore_collect_events(struct intel_uncore_box *box,
805 struct perf_event *leader, bool dogrp)
807 struct perf_event *event;
810 max_count = box->pmu->type->num_counters;
811 if (box->pmu->type->fixed_ctl)
814 if (box->n_events >= max_count)
818 box->event_list[n] = leader;
823 list_for_each_entry(event, &leader->sibling_list, group_entry) {
824 if (event->state <= PERF_EVENT_STATE_OFF)
830 box->event_list[n] = event;
836 static struct event_constraint *
837 uncore_event_constraint(struct intel_uncore_type *type,
838 struct perf_event *event)
840 struct event_constraint *c;
842 if (event->hw.config == ~0ULL)
843 return &constraint_fixed;
845 if (type->constraints) {
846 for_each_event_constraint(c, type->constraints) {
847 if ((event->hw.config & c->cmask) == c->code)
852 return &type->unconstrainted;
855 static int uncore_assign_events(struct intel_uncore_box *box,
858 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
859 struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
860 int i, ret, wmin, wmax;
861 struct hw_perf_event *hwc;
863 bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
865 for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
866 c = uncore_event_constraint(box->pmu->type,
869 wmin = min(wmin, c->weight);
870 wmax = max(wmax, c->weight);
873 /* fastpath, try to reuse previous register */
874 for (i = 0; i < n; i++) {
875 hwc = &box->event_list[i]->hw;
882 /* constraint still honored */
883 if (!test_bit(hwc->idx, c->idxmsk))
886 /* not already used */
887 if (test_bit(hwc->idx, used_mask))
890 __set_bit(hwc->idx, used_mask);
891 assign[i] = hwc->idx;
897 ret = perf_assign_events(constraints, n, wmin, wmax, assign);
898 return ret ? -EINVAL : 0;
901 static void uncore_pmu_event_start(struct perf_event *event, int flags)
903 struct intel_uncore_box *box = uncore_event_to_box(event);
904 int idx = event->hw.idx;
906 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
909 if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
913 box->events[idx] = event;
915 __set_bit(idx, box->active_mask);
917 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
918 uncore_enable_event(box, event);
920 if (box->n_active == 1) {
921 uncore_enable_box(box);
922 uncore_pmu_start_hrtimer(box);
926 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
928 struct intel_uncore_box *box = uncore_event_to_box(event);
929 struct hw_perf_event *hwc = &event->hw;
931 if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
932 uncore_disable_event(box, event);
934 box->events[hwc->idx] = NULL;
935 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
936 hwc->state |= PERF_HES_STOPPED;
938 if (box->n_active == 0) {
939 uncore_disable_box(box);
940 uncore_pmu_cancel_hrtimer(box);
944 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
946 * Drain the remaining delta count out of a event
947 * that we are disabling:
949 uncore_perf_event_update(box, event);
950 hwc->state |= PERF_HES_UPTODATE;
954 static int uncore_pmu_event_add(struct perf_event *event, int flags)
956 struct intel_uncore_box *box = uncore_event_to_box(event);
957 struct hw_perf_event *hwc = &event->hw;
958 int assign[UNCORE_PMC_IDX_MAX];
964 ret = n = uncore_collect_events(box, event, false);
968 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
969 if (!(flags & PERF_EF_START))
970 hwc->state |= PERF_HES_ARCH;
972 ret = uncore_assign_events(box, assign, n);
976 /* save events moving to new counters */
977 for (i = 0; i < box->n_events; i++) {
978 event = box->event_list[i];
981 if (hwc->idx == assign[i] &&
982 hwc->last_tag == box->tags[assign[i]])
985 * Ensure we don't accidentally enable a stopped
986 * counter simply because we rescheduled.
988 if (hwc->state & PERF_HES_STOPPED)
989 hwc->state |= PERF_HES_ARCH;
991 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
994 /* reprogram moved events into new counters */
995 for (i = 0; i < n; i++) {
996 event = box->event_list[i];
999 if (hwc->idx != assign[i] ||
1000 hwc->last_tag != box->tags[assign[i]])
1001 uncore_assign_hw_event(box, event, assign[i]);
1002 else if (i < box->n_events)
1005 if (hwc->state & PERF_HES_ARCH)
1008 uncore_pmu_event_start(event, 0);
1015 static void uncore_pmu_event_del(struct perf_event *event, int flags)
1017 struct intel_uncore_box *box = uncore_event_to_box(event);
1020 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
1022 for (i = 0; i < box->n_events; i++) {
1023 if (event == box->event_list[i]) {
1024 while (++i < box->n_events)
1025 box->event_list[i - 1] = box->event_list[i];
1033 event->hw.last_tag = ~0ULL;
1036 static void uncore_pmu_event_read(struct perf_event *event)
1038 struct intel_uncore_box *box = uncore_event_to_box(event);
1039 uncore_perf_event_update(box, event);
1043 * validation ensures the group can be loaded onto the
1044 * PMU if it was the only group available.
1046 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
1047 struct perf_event *event)
1049 struct perf_event *leader = event->group_leader;
1050 struct intel_uncore_box *fake_box;
1051 int assign[UNCORE_PMC_IDX_MAX];
1052 int ret = -EINVAL, n;
1054 fake_box = uncore_alloc_box(smp_processor_id());
1058 fake_box->pmu = pmu;
1060 * the event is not yet connected with its
1061 * siblings therefore we must first collect
1062 * existing siblings, then add the new event
1063 * before we can simulate the scheduling
1065 n = uncore_collect_events(fake_box, leader, true);
1069 fake_box->n_events = n;
1070 n = uncore_collect_events(fake_box, event, false);
1074 fake_box->n_events = n;
1076 ret = uncore_assign_events(fake_box, assign, n);
1082 int uncore_pmu_event_init(struct perf_event *event)
1084 struct intel_uncore_pmu *pmu;
1085 struct intel_uncore_box *box;
1086 struct hw_perf_event *hwc = &event->hw;
1089 if (event->attr.type != event->pmu->type)
1092 pmu = uncore_event_to_pmu(event);
1093 /* no device found for this pmu */
1094 if (pmu->func_id < 0)
1098 * Uncore PMU does measure at all privilege level all the time.
1099 * So it doesn't make sense to specify any exclude bits.
1101 if (event->attr.exclude_user || event->attr.exclude_kernel ||
1102 event->attr.exclude_hv || event->attr.exclude_idle)
1105 /* Sampling not supported yet */
1106 if (hwc->sample_period)
1110 * Place all uncore events for a particular physical package
1115 box = uncore_pmu_to_box(pmu, event->cpu);
1116 if (!box || box->cpu < 0)
1118 event->cpu = box->cpu;
1120 if (event->attr.config == UNCORE_FIXED_EVENT) {
1121 /* no fixed counter */
1122 if (!pmu->type->fixed_ctl)
1125 * if there is only one fixed counter, only the first pmu
1126 * can access the fixed counter
1128 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
1130 hwc->config = ~0ULL;
1132 hwc->config = event->attr.config & pmu->type->event_mask;
1136 event->hw.last_tag = ~0ULL;
1138 if (event->group_leader != event)
1139 ret = uncore_validate_group(pmu, event);
1146 static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu)
1150 pmu->pmu = (struct pmu) {
1151 .attr_groups = pmu->type->attr_groups,
1152 .task_ctx_nr = perf_invalid_context,
1153 .event_init = uncore_pmu_event_init,
1154 .add = uncore_pmu_event_add,
1155 .del = uncore_pmu_event_del,
1156 .start = uncore_pmu_event_start,
1157 .stop = uncore_pmu_event_stop,
1158 .read = uncore_pmu_event_read,
1161 if (pmu->type->num_boxes == 1) {
1162 if (strlen(pmu->type->name) > 0)
1163 sprintf(pmu->name, "uncore_%s", pmu->type->name);
1165 sprintf(pmu->name, "uncore");
1167 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
1171 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1175 static void __init uncore_type_exit(struct intel_uncore_type *type)
1179 for (i = 0; i < type->num_boxes; i++)
1180 free_percpu(type->pmus[i].box);
1183 kfree(type->attr_groups[1]);
1184 type->attr_groups[1] = NULL;
1187 static void uncore_types_exit(struct intel_uncore_type **types)
1190 for (i = 0; types[i]; i++)
1191 uncore_type_exit(types[i]);
1194 static int __init uncore_type_init(struct intel_uncore_type *type)
1196 struct intel_uncore_pmu *pmus;
1197 struct attribute_group *events_group;
1198 struct attribute **attrs;
1201 pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
1205 type->unconstrainted = (struct event_constraint)
1206 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
1207 0, type->num_counters, 0);
1209 for (i = 0; i < type->num_boxes; i++) {
1210 pmus[i].func_id = -1;
1211 pmus[i].pmu_idx = i;
1212 pmus[i].type = type;
1213 INIT_LIST_HEAD(&pmus[i].box_list);
1214 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
1219 if (type->event_descs) {
1221 while (type->event_descs[i].attr.attr.name)
1224 events_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
1225 sizeof(*events_group), GFP_KERNEL);
1229 attrs = (struct attribute **)(events_group + 1);
1230 events_group->name = "events";
1231 events_group->attrs = attrs;
1233 for (j = 0; j < i; j++)
1234 attrs[j] = &type->event_descs[j].attr.attr;
1236 type->attr_groups[1] = events_group;
1242 uncore_type_exit(type);
1246 static int __init uncore_types_init(struct intel_uncore_type **types)
1250 for (i = 0; types[i]; i++) {
1251 ret = uncore_type_init(types[i]);
1258 uncore_type_exit(types[i]);
1262 static struct pci_driver *uncore_pci_driver;
1263 static bool pcidrv_registered;
1266 * add a pci uncore device
1268 static int __devinit uncore_pci_add(struct intel_uncore_type *type,
1269 struct pci_dev *pdev)
1271 struct intel_uncore_pmu *pmu;
1272 struct intel_uncore_box *box;
1275 phys_id = pcibus_to_physid[pdev->bus->number];
1279 box = uncore_alloc_box(0);
1284 * for performance monitoring unit with multiple boxes,
1285 * each box has a different function id.
1287 for (i = 0; i < type->num_boxes; i++) {
1288 pmu = &type->pmus[i];
1289 if (pmu->func_id == pdev->devfn)
1291 if (pmu->func_id < 0) {
1292 pmu->func_id = pdev->devfn;
1303 box->phys_id = phys_id;
1304 box->pci_dev = pdev;
1306 uncore_box_init(box);
1307 pci_set_drvdata(pdev, box);
1309 raw_spin_lock(&uncore_box_lock);
1310 list_add_tail(&box->list, &pmu->box_list);
1311 raw_spin_unlock(&uncore_box_lock);
1316 static void __devexit uncore_pci_remove(struct pci_dev *pdev)
1318 struct intel_uncore_box *box = pci_get_drvdata(pdev);
1319 struct intel_uncore_pmu *pmu = box->pmu;
1320 int cpu, phys_id = pcibus_to_physid[pdev->bus->number];
1322 if (WARN_ON_ONCE(phys_id != box->phys_id))
1325 raw_spin_lock(&uncore_box_lock);
1326 list_del(&box->list);
1327 raw_spin_unlock(&uncore_box_lock);
1329 for_each_possible_cpu(cpu) {
1330 if (*per_cpu_ptr(pmu->box, cpu) == box) {
1331 *per_cpu_ptr(pmu->box, cpu) = NULL;
1332 atomic_dec(&box->refcnt);
1336 WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
1340 static int __devinit uncore_pci_probe(struct pci_dev *pdev,
1341 const struct pci_device_id *id)
1343 struct intel_uncore_type *type;
1345 type = (struct intel_uncore_type *)id->driver_data;
1346 return uncore_pci_add(type, pdev);
1349 static int __init uncore_pci_init(void)
1353 switch (boot_cpu_data.x86_model) {
1354 case 45: /* Sandy Bridge-EP */
1355 pci_uncores = snbep_pci_uncores;
1356 uncore_pci_driver = &snbep_uncore_pci_driver;
1357 snbep_pci2phy_map_init();
1363 ret = uncore_types_init(pci_uncores);
1367 uncore_pci_driver->probe = uncore_pci_probe;
1368 uncore_pci_driver->remove = uncore_pci_remove;
1370 ret = pci_register_driver(uncore_pci_driver);
1372 pcidrv_registered = true;
1374 uncore_types_exit(pci_uncores);
1379 static void __init uncore_pci_exit(void)
1381 if (pcidrv_registered) {
1382 pcidrv_registered = false;
1383 pci_unregister_driver(uncore_pci_driver);
1384 uncore_types_exit(pci_uncores);
1388 static void __cpuinit uncore_cpu_dying(int cpu)
1390 struct intel_uncore_type *type;
1391 struct intel_uncore_pmu *pmu;
1392 struct intel_uncore_box *box;
1395 for (i = 0; msr_uncores[i]; i++) {
1396 type = msr_uncores[i];
1397 for (j = 0; j < type->num_boxes; j++) {
1398 pmu = &type->pmus[j];
1399 box = *per_cpu_ptr(pmu->box, cpu);
1400 *per_cpu_ptr(pmu->box, cpu) = NULL;
1401 if (box && atomic_dec_and_test(&box->refcnt))
1407 static int __cpuinit uncore_cpu_starting(int cpu)
1409 struct intel_uncore_type *type;
1410 struct intel_uncore_pmu *pmu;
1411 struct intel_uncore_box *box, *exist;
1412 int i, j, k, phys_id;
1414 phys_id = topology_physical_package_id(cpu);
1416 for (i = 0; msr_uncores[i]; i++) {
1417 type = msr_uncores[i];
1418 for (j = 0; j < type->num_boxes; j++) {
1419 pmu = &type->pmus[j];
1420 box = *per_cpu_ptr(pmu->box, cpu);
1421 /* called by uncore_cpu_init? */
1422 if (box && box->phys_id >= 0) {
1423 uncore_box_init(box);
1427 for_each_online_cpu(k) {
1428 exist = *per_cpu_ptr(pmu->box, k);
1429 if (exist && exist->phys_id == phys_id) {
1430 atomic_inc(&exist->refcnt);
1431 *per_cpu_ptr(pmu->box, cpu) = exist;
1439 box->phys_id = phys_id;
1440 uncore_box_init(box);
1447 static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id)
1449 struct intel_uncore_type *type;
1450 struct intel_uncore_pmu *pmu;
1451 struct intel_uncore_box *box;
1454 for (i = 0; msr_uncores[i]; i++) {
1455 type = msr_uncores[i];
1456 for (j = 0; j < type->num_boxes; j++) {
1457 pmu = &type->pmus[j];
1458 if (pmu->func_id < 0)
1461 box = uncore_alloc_box(cpu);
1466 box->phys_id = phys_id;
1467 *per_cpu_ptr(pmu->box, cpu) = box;
1473 static void __cpuinit uncore_change_context(struct intel_uncore_type **uncores,
1474 int old_cpu, int new_cpu)
1476 struct intel_uncore_type *type;
1477 struct intel_uncore_pmu *pmu;
1478 struct intel_uncore_box *box;
1481 for (i = 0; uncores[i]; i++) {
1483 for (j = 0; j < type->num_boxes; j++) {
1484 pmu = &type->pmus[j];
1486 box = uncore_pmu_to_box(pmu, new_cpu);
1488 box = uncore_pmu_to_box(pmu, old_cpu);
1493 WARN_ON_ONCE(box->cpu != -1);
1498 WARN_ON_ONCE(box->cpu != old_cpu);
1500 uncore_pmu_cancel_hrtimer(box);
1501 perf_pmu_migrate_context(&pmu->pmu,
1511 static void __cpuinit uncore_event_exit_cpu(int cpu)
1513 int i, phys_id, target;
1515 /* if exiting cpu is used for collecting uncore events */
1516 if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1519 /* find a new cpu to collect uncore events */
1520 phys_id = topology_physical_package_id(cpu);
1522 for_each_online_cpu(i) {
1525 if (phys_id == topology_physical_package_id(i)) {
1531 /* migrate uncore events to the new cpu */
1533 cpumask_set_cpu(target, &uncore_cpu_mask);
1535 uncore_change_context(msr_uncores, cpu, target);
1536 uncore_change_context(pci_uncores, cpu, target);
1539 static void __cpuinit uncore_event_init_cpu(int cpu)
1543 phys_id = topology_physical_package_id(cpu);
1544 for_each_cpu(i, &uncore_cpu_mask) {
1545 if (phys_id == topology_physical_package_id(i))
1549 cpumask_set_cpu(cpu, &uncore_cpu_mask);
1551 uncore_change_context(msr_uncores, -1, cpu);
1552 uncore_change_context(pci_uncores, -1, cpu);
1555 static int __cpuinit uncore_cpu_notifier(struct notifier_block *self,
1556 unsigned long action, void *hcpu)
1558 unsigned int cpu = (long)hcpu;
1560 /* allocate/free data structure for uncore box */
1561 switch (action & ~CPU_TASKS_FROZEN) {
1562 case CPU_UP_PREPARE:
1563 uncore_cpu_prepare(cpu, -1);
1566 uncore_cpu_starting(cpu);
1568 case CPU_UP_CANCELED:
1570 uncore_cpu_dying(cpu);
1576 /* select the cpu that collects uncore events */
1577 switch (action & ~CPU_TASKS_FROZEN) {
1578 case CPU_DOWN_FAILED:
1580 uncore_event_init_cpu(cpu);
1582 case CPU_DOWN_PREPARE:
1583 uncore_event_exit_cpu(cpu);
1592 static struct notifier_block uncore_cpu_nb __cpuinitdata = {
1593 .notifier_call = uncore_cpu_notifier,
1595 * to migrate uncore events, our notifier should be executed
1596 * before perf core's notifier.
1598 .priority = CPU_PRI_PERF + 1,
1601 static void __init uncore_cpu_setup(void *dummy)
1603 uncore_cpu_starting(smp_processor_id());
1606 static int __init uncore_cpu_init(void)
1610 switch (boot_cpu_data.x86_model) {
1611 case 26: /* Nehalem */
1613 case 37: /* Westmere */
1615 msr_uncores = nhm_msr_uncores;
1617 case 42: /* Sandy Bridge */
1618 msr_uncores = snb_msr_uncores;
1620 case 45: /* Sandy Birdge-EP */
1621 msr_uncores = snbep_msr_uncores;
1627 ret = uncore_types_init(msr_uncores);
1633 for_each_online_cpu(cpu) {
1634 int i, phys_id = topology_physical_package_id(cpu);
1636 for_each_cpu(i, &uncore_cpu_mask) {
1637 if (phys_id == topology_physical_package_id(i)) {
1645 uncore_cpu_prepare(cpu, phys_id);
1646 uncore_event_init_cpu(cpu);
1648 on_each_cpu(uncore_cpu_setup, NULL, 1);
1650 register_cpu_notifier(&uncore_cpu_nb);
1657 static int __init uncore_pmus_register(void)
1659 struct intel_uncore_pmu *pmu;
1660 struct intel_uncore_type *type;
1663 for (i = 0; msr_uncores[i]; i++) {
1664 type = msr_uncores[i];
1665 for (j = 0; j < type->num_boxes; j++) {
1666 pmu = &type->pmus[j];
1667 uncore_pmu_register(pmu);
1671 for (i = 0; pci_uncores[i]; i++) {
1672 type = pci_uncores[i];
1673 for (j = 0; j < type->num_boxes; j++) {
1674 pmu = &type->pmus[j];
1675 uncore_pmu_register(pmu);
1682 static int __init intel_uncore_init(void)
1686 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1689 ret = uncore_pci_init();
1692 ret = uncore_cpu_init();
1698 uncore_pmus_register();
1703 device_initcall(intel_uncore_init);