arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #ifdef CONFIG_CPU_SUP_INTEL
   2
   3 /* The maximal number of PEBS events: */
   4 #define MAX_PEBS_EVENTS         4
   5
   6 /* The size of a BTS record in bytes: */
   7 #define BTS_RECORD_SIZE         24
   8
   9 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  10 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  11
  12 /*
  13  * pebs_record_32 for p4 and core not supported
  14
  15 struct pebs_record_32 {
  16         u32 flags, ip;
  17         u32 ax, bc, cx, dx;
  18         u32 si, di, bp, sp;
  19 };
  20
  21  */
  22
  23 struct pebs_record_core {
  24         u64 flags, ip;
  25         u64 ax, bx, cx, dx;
  26         u64 si, di, bp, sp;
  27         u64 r8,  r9,  r10, r11;
  28         u64 r12, r13, r14, r15;
  29 };
  30
  31 struct pebs_record_nhm {
  32         u64 flags, ip;
  33         u64 ax, bx, cx, dx;
  34         u64 si, di, bp, sp;
  35         u64 r8,  r9,  r10, r11;
  36         u64 r12, r13, r14, r15;
  37         u64 status, dla, dse, lat;
  38 };
  39
  40 /*
  41  * A debug store configuration.
  42  *
  43  * We only support architectures that use 64bit fields.
  44  */
  45 struct debug_store {
  46         u64     bts_buffer_base;
  47         u64     bts_index;
  48         u64     bts_absolute_maximum;
  49         u64     bts_interrupt_threshold;
  50         u64     pebs_buffer_base;
  51         u64     pebs_index;
  52         u64     pebs_absolute_maximum;
  53         u64     pebs_interrupt_threshold;
  54         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  55 };
  56
  57 static void init_debug_store_on_cpu(int cpu)
  58 {
  59         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
  60
  61         if (!ds)
  62                 return;
  63
  64         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
  65                      (u32)((u64)(unsigned long)ds),
  66                      (u32)((u64)(unsigned long)ds >> 32));
  67 }
  68
  69 static void fini_debug_store_on_cpu(int cpu)
  70 {
  71         if (!per_cpu(cpu_hw_events, cpu).ds)
  72                 return;
  73
  74         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
  75 }
  76
  77 static int alloc_pebs_buffer(int cpu)
  78 {
  79         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
  80         int max, thresh = 1; /* always use a single PEBS record */
  81         void *buffer;
  82
  83         if (!x86_pmu.pebs)
  84                 return 0;
  85
  86         buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL);
  87         if (unlikely(!buffer))
  88                 return -ENOMEM;
  89
  90         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
  91
  92         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
  93         ds->pebs_index = ds->pebs_buffer_base;
  94         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
  95                 max * x86_pmu.pebs_record_size;
  96
  97         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
  98                 thresh * x86_pmu.pebs_record_size;
  99
 100         return 0;
 101 }
 102
 103 static void release_pebs_buffer(int cpu)
 104 {
 105         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 106
 107         if (!ds || !x86_pmu.pebs)
 108                 return;
 109
 110         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 111         ds->pebs_buffer_base = 0;
 112 }
 113
 114 static int alloc_bts_buffer(int cpu)
 115 {
 116         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 117         int max, thresh;
 118         void *buffer;
 119
 120         if (!x86_pmu.bts)
 121                 return 0;
 122
 123         buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 124         if (unlikely(!buffer))
 125                 return -ENOMEM;
 126
 127         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 128         thresh = max / 16;
 129
 130         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 131         ds->bts_index = ds->bts_buffer_base;
 132         ds->bts_absolute_maximum = ds->bts_buffer_base +
 133                 max * BTS_RECORD_SIZE;
 134         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 135                 thresh * BTS_RECORD_SIZE;
 136
 137         return 0;
 138 }
 139
 140 static void release_bts_buffer(int cpu)
 141 {
 142         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 143
 144         if (!ds || !x86_pmu.bts)
 145                 return;
 146
 147         kfree((void *)(unsigned long)ds->bts_buffer_base);
 148         ds->bts_buffer_base = 0;
 149 }
 150
 151 static int alloc_ds_buffer(int cpu)
 152 {
 153         struct debug_store *ds;
 154
 155         ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 156         if (unlikely(!ds))
 157                 return -ENOMEM;
 158
 159         per_cpu(cpu_hw_events, cpu).ds = ds;
 160
 161         return 0;
 162 }
 163
 164 static void release_ds_buffer(int cpu)
 165 {
 166         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 167
 168         if (!ds)
 169                 return;
 170
 171         per_cpu(cpu_hw_events, cpu).ds = NULL;
 172         kfree(ds);
 173 }
 174
 175 static void release_ds_buffers(void)
 176 {
 177         int cpu;
 178
 179         if (!x86_pmu.bts && !x86_pmu.pebs)
 180                 return;
 181
 182         get_online_cpus();
 183         for_each_online_cpu(cpu)
 184                 fini_debug_store_on_cpu(cpu);
 185
 186         for_each_possible_cpu(cpu) {
 187                 release_pebs_buffer(cpu);
 188                 release_bts_buffer(cpu);
 189                 release_ds_buffer(cpu);
 190         }
 191         put_online_cpus();
 192 }
 193
 194 static int reserve_ds_buffers(void)
 195 {
 196         int bts_err = 0, pebs_err = 0;
 197         int cpu;
 198
 199         x86_pmu.bts_active = 0;
 200         x86_pmu.pebs_active = 0;
 201
 202         if (!x86_pmu.bts && !x86_pmu.pebs)
 203                 return 0;
 204
 205         if (!x86_pmu.bts)
 206                 bts_err = 1;
 207
 208         if (!x86_pmu.pebs)
 209                 pebs_err = 1;
 210
 211         get_online_cpus();
 212
 213         for_each_possible_cpu(cpu) {
 214                 if (alloc_ds_buffer(cpu)) {
 215                         bts_err = 1;
 216                         pebs_err = 1;
 217                 }
 218
 219                 if (!bts_err && alloc_bts_buffer(cpu))
 220                         bts_err = 1;
 221
 222                 if (!pebs_err && alloc_pebs_buffer(cpu))
 223                         pebs_err = 1;
 224
 225                 if (bts_err && pebs_err)
 226                         break;
 227         }
 228
 229         if (bts_err) {
 230                 for_each_possible_cpu(cpu)
 231                         release_bts_buffer(cpu);
 232         }
 233
 234         if (pebs_err) {
 235                 for_each_possible_cpu(cpu)
 236                         release_pebs_buffer(cpu);
 237         }
 238
 239         if (bts_err && pebs_err) {
 240                 for_each_possible_cpu(cpu)
 241                         release_ds_buffer(cpu);
 242         } else {
 243                 if (x86_pmu.bts && !bts_err)
 244                         x86_pmu.bts_active = 1;
 245
 246                 if (x86_pmu.pebs && !pebs_err)
 247                         x86_pmu.pebs_active = 1;
 248
 249                 for_each_online_cpu(cpu)
 250                         init_debug_store_on_cpu(cpu);
 251         }
 252
 253         put_online_cpus();
 254
 255         return 0;
 256 }
 257
 258 /*
 259  * BTS
 260  */
 261
 262 static struct event_constraint bts_constraint =
 263         EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
 264
 265 static void intel_pmu_enable_bts(u64 config)
 266 {
 267         unsigned long debugctlmsr;
 268
 269         debugctlmsr = get_debugctlmsr();
 270
 271         debugctlmsr |= DEBUGCTLMSR_TR;
 272         debugctlmsr |= DEBUGCTLMSR_BTS;
 273         debugctlmsr |= DEBUGCTLMSR_BTINT;
 274
 275         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 276                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 277
 278         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 279                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 280
 281         update_debugctlmsr(debugctlmsr);
 282 }
 283
 284 static void intel_pmu_disable_bts(void)
 285 {
 286         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 287         unsigned long debugctlmsr;
 288
 289         if (!cpuc->ds)
 290                 return;
 291
 292         debugctlmsr = get_debugctlmsr();
 293
 294         debugctlmsr &=
 295                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 296                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 297
 298         update_debugctlmsr(debugctlmsr);
 299 }
 300
 301 static int intel_pmu_drain_bts_buffer(void)
 302 {
 303         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 304         struct debug_store *ds = cpuc->ds;
 305         struct bts_record {
 306                 u64     from;
 307                 u64     to;
 308                 u64     flags;
 309         };
 310         struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
 311         struct bts_record *at, *top;
 312         struct perf_output_handle handle;
 313         struct perf_event_header header;
 314         struct perf_sample_data data;
 315         struct pt_regs regs;
 316
 317         if (!event)
 318                 return 0;
 319
 320         if (!x86_pmu.bts_active)
 321                 return 0;
 322
 323         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 324         top = (struct bts_record *)(unsigned long)ds->bts_index;
 325
 326         if (top <= at)
 327                 return 0;
 328
 329         ds->bts_index = ds->bts_buffer_base;
 330
 331         perf_sample_data_init(&data, 0);
 332         data.period = event->hw.last_period;
 333         regs.ip     = 0;
 334
 335         /*
 336          * Prepare a generic sample, i.e. fill in the invariant fields.
 337          * We will overwrite the from and to address before we output
 338          * the sample.
 339          */
 340         perf_prepare_sample(&header, &data, event, &regs);
 341
 342         if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
 343                 return 1;
 344
 345         for (; at < top; at++) {
 346                 data.ip         = at->from;
 347                 data.addr       = at->to;
 348
 349                 perf_output_sample(&handle, &header, &data, event);
 350         }
 351
 352         perf_output_end(&handle);
 353
 354         /* There's new data available. */
 355         event->hw.interrupts++;
 356         event->pending_kill = POLL_IN;
 357         return 1;
 358 }
 359
 360 /*
 361  * PEBS
 362  */
 363
 364 static struct event_constraint intel_core_pebs_events[] = {
 365         PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
 366         PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 367         PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 368         PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 369         PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
 370         PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 371         PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
 372         PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 373         PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
 374         EVENT_CONSTRAINT_END
 375 };
 376
 377 static struct event_constraint intel_nehalem_pebs_events[] = {
 378         PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
 379         PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
 380         PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
 381         PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
 382         PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
 383         PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 384         PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
 385         PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 386         PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
 387         EVENT_CONSTRAINT_END
 388 };
 389
 390 static struct event_constraint *
 391 intel_pebs_constraints(struct perf_event *event)
 392 {
 393         struct event_constraint *c;
 394
 395         if (!event->attr.precise_ip)
 396                 return NULL;
 397
 398         if (x86_pmu.pebs_constraints) {
 399                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 400                         if ((event->hw.config & c->cmask) == c->code)
 401                                 return c;
 402                 }
 403         }
 404
 405         return &emptyconstraint;
 406 }
 407
 408 static void intel_pmu_pebs_enable(struct perf_event *event)
 409 {
 410         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 411         struct hw_perf_event *hwc = &event->hw;
 412
 413         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 414
 415         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 416         WARN_ON_ONCE(cpuc->enabled);
 417
 418         if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
 419                 intel_pmu_lbr_enable(event);
 420 }
 421
 422 static void intel_pmu_pebs_disable(struct perf_event *event)
 423 {
 424         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 425         struct hw_perf_event *hwc = &event->hw;
 426
 427         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 428         if (cpuc->enabled)
 429                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 430
 431         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 432
 433         if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
 434                 intel_pmu_lbr_disable(event);
 435 }
 436
 437 static void intel_pmu_pebs_enable_all(void)
 438 {
 439         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 440
 441         if (cpuc->pebs_enabled)
 442                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 443 }
 444
 445 static void intel_pmu_pebs_disable_all(void)
 446 {
 447         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 448
 449         if (cpuc->pebs_enabled)
 450                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 451 }
 452
 453 #include <asm/insn.h>
 454
 455 static inline bool kernel_ip(unsigned long ip)
 456 {
 457 #ifdef CONFIG_X86_32
 458         return ip > PAGE_OFFSET;
 459 #else
 460         return (long)ip < 0;
 461 #endif
 462 }
 463
 464 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 465 {
 466         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 467         unsigned long from = cpuc->lbr_entries[0].from;
 468         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 469         unsigned long ip = regs->ip;
 470
 471         /*
 472          * We don't need to fixup if the PEBS assist is fault like
 473          */
 474         if (!x86_pmu.intel_cap.pebs_trap)
 475                 return 1;
 476
 477         /*
 478          * No LBR entry, no basic block, no rewinding
 479          */
 480         if (!cpuc->lbr_stack.nr || !from || !to)
 481                 return 0;
 482
 483         /*
 484          * Basic blocks should never cross user/kernel boundaries
 485          */
 486         if (kernel_ip(ip) != kernel_ip(to))
 487                 return 0;
 488
 489         /*
 490          * unsigned math, either ip is before the start (impossible) or
 491          * the basic block is larger than 1 page (sanity)
 492          */
 493         if ((ip - to) > PAGE_SIZE)
 494                 return 0;
 495
 496         /*
 497          * We sampled a branch insn, rewind using the LBR stack
 498          */
 499         if (ip == to) {
 500                 regs->ip = from;
 501                 return 1;
 502         }
 503
 504         do {
 505                 struct insn insn;
 506                 u8 buf[MAX_INSN_SIZE];
 507                 void *kaddr;
 508
 509                 old_to = to;
 510                 if (!kernel_ip(ip)) {
 511                         int bytes, size = MAX_INSN_SIZE;
 512
 513                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 514                         if (bytes != size)
 515                                 return 0;
 516
 517                         kaddr = buf;
 518                 } else
 519                         kaddr = (void *)to;
 520
 521                 kernel_insn_init(&insn, kaddr);
 522                 insn_get_length(&insn);
 523                 to += insn.length;
 524         } while (to < ip);
 525
 526         if (to == ip) {
 527                 regs->ip = old_to;
 528                 return 1;
 529         }
 530
 531         /*
 532          * Even though we decoded the basic block, the instruction stream
 533          * never matched the given IP, either the TO or the IP got corrupted.
 534          */
 535         return 0;
 536 }
 537
 538 static int intel_pmu_save_and_restart(struct perf_event *event);
 539
 540 static void __intel_pmu_pebs_event(struct perf_event *event,
 541                                    struct pt_regs *iregs, void *__pebs)
 542 {
 543         /*
 544          * We cast to pebs_record_core since that is a subset of
 545          * both formats and we don't use the other fields in this
 546          * routine.
 547          */
 548         struct pebs_record_core *pebs = __pebs;
 549         struct perf_sample_data data;
 550         struct pt_regs regs;
 551
 552         if (!intel_pmu_save_and_restart(event))
 553                 return;
 554
 555         perf_sample_data_init(&data, 0);
 556         data.period = event->hw.last_period;
 557
 558         /*
 559          * We use the interrupt regs as a base because the PEBS record
 560          * does not contain a full regs set, specifically it seems to
 561          * lack segment descriptors, which get used by things like
 562          * user_mode().
 563          *
 564          * In the simple case fix up only the IP and BP,SP regs, for
 565          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 566          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 567          */
 568         regs = *iregs;
 569         regs.ip = pebs->ip;
 570         regs.bp = pebs->bp;
 571         regs.sp = pebs->sp;
 572
 573         if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 574                 regs.flags |= PERF_EFLAGS_EXACT;
 575         else
 576                 regs.flags &= ~PERF_EFLAGS_EXACT;
 577
 578         if (perf_event_overflow(event, 1, &data, &regs))
 579                 x86_pmu_stop(event, 0);
 580 }
 581
 582 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 583 {
 584         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 585         struct debug_store *ds = cpuc->ds;
 586         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 587         struct pebs_record_core *at, *top;
 588         int n;
 589
 590         if (!x86_pmu.pebs_active)
 591                 return;
 592
 593         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 594         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 595
 596         /*
 597          * Whatever else happens, drain the thing
 598          */
 599         ds->pebs_index = ds->pebs_buffer_base;
 600
 601         if (!test_bit(0, cpuc->active_mask))
 602                 return;
 603
 604         WARN_ON_ONCE(!event);
 605
 606         if (!event->attr.precise_ip)
 607                 return;
 608
 609         n = top - at;
 610         if (n <= 0)
 611                 return;
 612
 613         /*
 614          * Should not happen, we program the threshold at 1 and do not
 615          * set a reset value.
 616          */
 617         WARN_ON_ONCE(n > 1);
 618         at += n - 1;
 619
 620         __intel_pmu_pebs_event(event, iregs, at);
 621 }
 622
 623 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 624 {
 625         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 626         struct debug_store *ds = cpuc->ds;
 627         struct pebs_record_nhm *at, *top;
 628         struct perf_event *event = NULL;
 629         u64 status = 0;
 630         int bit, n;
 631
 632         if (!x86_pmu.pebs_active)
 633                 return;
 634
 635         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 636         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 637
 638         ds->pebs_index = ds->pebs_buffer_base;
 639
 640         n = top - at;
 641         if (n <= 0)
 642                 return;
 643
 644         /*
 645          * Should not happen, we program the threshold at 1 and do not
 646          * set a reset value.
 647          */
 648         WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
 649
 650         for ( ; at < top; at++) {
 651                 for_each_set_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
 652                         event = cpuc->events[bit];
 653                         if (!test_bit(bit, cpuc->active_mask))
 654                                 continue;
 655
 656                         WARN_ON_ONCE(!event);
 657
 658                         if (!event->attr.precise_ip)
 659                                 continue;
 660
 661                         if (__test_and_set_bit(bit, (unsigned long *)&status))
 662                                 continue;
 663
 664                         break;
 665                 }
 666
 667                 if (!event || bit >= MAX_PEBS_EVENTS)
 668                         continue;
 669
 670                 __intel_pmu_pebs_event(event, iregs, at);
 671         }
 672 }
 673
 674 /*
 675  * BTS, PEBS probe and setup
 676  */
 677
 678 static void intel_ds_init(void)
 679 {
 680         /*
 681          * No support for 32bit formats
 682          */
 683         if (!boot_cpu_has(X86_FEATURE_DTES64))
 684                 return;
 685
 686         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 687         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
 688         if (x86_pmu.pebs) {
 689                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 690                 int format = x86_pmu.intel_cap.pebs_format;
 691
 692                 switch (format) {
 693                 case 0:
 694                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
 695                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
 696                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
 697                         x86_pmu.pebs_constraints = intel_core_pebs_events;
 698                         break;
 699
 700                 case 1:
 701                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
 702                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
 703                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
 704                         x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
 705                         break;
 706
 707                 default:
 708                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
 709                         x86_pmu.pebs = 0;
 710                         break;
 711                 }
 712         }
 713 }
 714
 715 #else /* CONFIG_CPU_SUP_INTEL */
 716
 717 static int reserve_ds_buffers(void)
 718 {
 719         return 0;
 720 }
 721
 722 static void release_ds_buffers(void)
 723 {
 724 }
 725
 726 #endif /* CONFIG_CPU_SUP_INTEL */