arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         unsigned long size, len = 0;
  53         struct page *page;
  54         void *map;
  55         int ret;
  56
  57         do {
  58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  59                 if (!ret)
  60                         break;
  61
  62                 offset = addr & (PAGE_SIZE - 1);
  63                 size = min(PAGE_SIZE - offset, n - len);
  64
  65                 map = kmap_atomic(page);
  66                 memcpy(to, map+offset, size);
  67                 kunmap_atomic(map);
  68                 put_page(page);
  69
  70                 len  += size;
  71                 to   += size;
  72                 addr += size;
  73
  74         } while (len < n);
  75
  76         return len;
  77 }
  78
  79 struct event_constraint {
  80         union {
  81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  82                 u64             idxmsk64;
  83         };
  84         u64     code;
  85         u64     cmask;
  86         int     weight;
  87 };
  88
  89 struct amd_nb {
  90         int nb_id;  /* NorthBridge id */
  91         int refcnt; /* reference count */
  92         struct perf_event *owners[X86_PMC_IDX_MAX];
  93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  94 };
  95
  96 #define MAX_LBR_ENTRIES         16
  97
  98 struct cpu_hw_events {
  99         /*
 100          * Generic x86 PMC bits
 101          */
 102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171
 172 #define EVENT_CONSTRAINT_END            \
 173         EVENT_CONSTRAINT(0, 0, 0)
 174
 175 #define for_each_event_constraint(e, c) \
 176         for ((e) = (c); (e)->weight; (e)++)
 177
 178 union perf_capabilities {
 179         struct {
 180                 u64     lbr_format    : 6;
 181                 u64     pebs_trap     : 1;
 182                 u64     pebs_arch_reg : 1;
 183                 u64     pebs_format   : 4;
 184                 u64     smm_freeze    : 1;
 185         };
 186         u64     capabilities;
 187 };
 188
 189 /*
 190  * struct x86_pmu - generic x86 pmu
 191  */
 192 struct x86_pmu {
 193         /*
 194          * Generic x86 PMC bits
 195          */
 196         const char      *name;
 197         int             version;
 198         int             (*handle_irq)(struct pt_regs *);
 199         void            (*disable_all)(void);
 200         void            (*enable_all)(int added);
 201         void            (*enable)(struct perf_event *);
 202         void            (*disable)(struct perf_event *);
 203         int             (*hw_config)(struct perf_event *event);
 204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 205         unsigned        eventsel;
 206         unsigned        perfctr;
 207         u64             (*event_map)(int);
 208         int             max_events;
 209         int             num_counters;
 210         int             num_counters_fixed;
 211         int             cntval_bits;
 212         u64             cntval_mask;
 213         int             apic;
 214         u64             max_period;
 215         struct event_constraint *
 216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218
 219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 220                                                  struct perf_event *event);
 221         struct event_constraint *event_constraints;
 222         void            (*quirks)(void);
 223         int             perfctr_second_write;
 224
 225         int             (*cpu_prepare)(int cpu);
 226         void            (*cpu_starting)(int cpu);
 227         void            (*cpu_dying)(int cpu);
 228         void            (*cpu_dead)(int cpu);
 229
 230         /*
 231          * Intel Arch Perfmon v2+
 232          */
 233         u64                     intel_ctrl;
 234         union perf_capabilities intel_cap;
 235
 236         /*
 237          * Intel DebugStore bits
 238          */
 239         int             bts, pebs;
 240         int             bts_active, pebs_active;
 241         int             pebs_record_size;
 242         void            (*drain_pebs)(struct pt_regs *regs);
 243         struct event_constraint *pebs_constraints;
 244
 245         /*
 246          * Intel LBR
 247          */
 248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 249         int             lbr_nr;                    /* hardware stack size */
 250 };
 251
 252 static struct x86_pmu x86_pmu __read_mostly;
 253
 254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 255         .enabled = 1,
 256 };
 257
 258 static int x86_perf_event_set_period(struct perf_event *event);
 259
 260 /*
 261  * Generalized hw caching related hw_event table, filled
 262  * in on a per model basis. A value of 0 means
 263  * 'not supported', -1 means 'hw_event makes no sense on
 264  * this CPU', any other value means the raw hw_event
 265  * ID.
 266  */
 267
 268 #define C(x) PERF_COUNT_HW_CACHE_##x
 269
 270 static u64 __read_mostly hw_cache_event_ids
 271                                 [PERF_COUNT_HW_CACHE_MAX]
 272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 274
 275 /*
 276  * Propagate event elapsed time into the generic event.
 277  * Can only be executed on the CPU where the event is active.
 278  * Returns the delta events processed.
 279  */
 280 static u64
 281 x86_perf_event_update(struct perf_event *event)
 282 {
 283         struct hw_perf_event *hwc = &event->hw;
 284         int shift = 64 - x86_pmu.cntval_bits;
 285         u64 prev_raw_count, new_raw_count;
 286         int idx = hwc->idx;
 287         s64 delta;
 288
 289         if (idx == X86_PMC_IDX_FIXED_BTS)
 290                 return 0;
 291
 292         /*
 293          * Careful: an NMI might modify the previous event value.
 294          *
 295          * Our tactic to handle this is to first atomically read and
 296          * exchange a new raw count - then add that new-prev delta
 297          * count to the generic event atomically:
 298          */
 299 again:
 300         prev_raw_count = local64_read(&hwc->prev_count);
 301         rdmsrl(hwc->event_base + idx, new_raw_count);
 302
 303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 304                                         new_raw_count) != prev_raw_count)
 305                 goto again;
 306
 307         /*
 308          * Now we have the new raw value and have updated the prev
 309          * timestamp already. We can now calculate the elapsed delta
 310          * (event-)time and add that to the generic event.
 311          *
 312          * Careful, not all hw sign-extends above the physical width
 313          * of the count.
 314          */
 315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 316         delta >>= shift;
 317
 318         local64_add(delta, &event->count);
 319         local64_sub(delta, &hwc->period_left);
 320
 321         return new_raw_count;
 322 }
 323
 324 static atomic_t active_events;
 325 static DEFINE_MUTEX(pmc_reserve_mutex);
 326
 327 #ifdef CONFIG_X86_LOCAL_APIC
 328
 329 static bool reserve_pmc_hardware(void)
 330 {
 331         int i;
 332
 333         for (i = 0; i < x86_pmu.num_counters; i++) {
 334                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 335                         goto perfctr_fail;
 336         }
 337
 338         for (i = 0; i < x86_pmu.num_counters; i++) {
 339                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 340                         goto eventsel_fail;
 341         }
 342
 343         return true;
 344
 345 eventsel_fail:
 346         for (i--; i >= 0; i--)
 347                 release_evntsel_nmi(x86_pmu.eventsel + i);
 348
 349         i = x86_pmu.num_counters;
 350
 351 perfctr_fail:
 352         for (i--; i >= 0; i--)
 353                 release_perfctr_nmi(x86_pmu.perfctr + i);
 354
 355         return false;
 356 }
 357
 358 static void release_pmc_hardware(void)
 359 {
 360         int i;
 361
 362         for (i = 0; i < x86_pmu.num_counters; i++) {
 363                 release_perfctr_nmi(x86_pmu.perfctr + i);
 364                 release_evntsel_nmi(x86_pmu.eventsel + i);
 365         }
 366 }
 367
 368 #else
 369
 370 static bool reserve_pmc_hardware(void) { return true; }
 371 static void release_pmc_hardware(void) {}
 372
 373 #endif
 374
 375 static bool check_hw_exists(void)
 376 {
 377         u64 val, val_new = 0;
 378         int i, reg, ret = 0;
 379
 380         /*
 381          * Check to see if the BIOS enabled any of the counters, if so
 382          * complain and bail.
 383          */
 384         for (i = 0; i < x86_pmu.num_counters; i++) {
 385                 reg = x86_pmu.eventsel + i;
 386                 ret = rdmsrl_safe(reg, &val);
 387                 if (ret)
 388                         goto msr_fail;
 389                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 390                         goto bios_fail;
 391         }
 392
 393         if (x86_pmu.num_counters_fixed) {
 394                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 395                 ret = rdmsrl_safe(reg, &val);
 396                 if (ret)
 397                         goto msr_fail;
 398                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 399                         if (val & (0x03 << i*4))
 400                                 goto bios_fail;
 401                 }
 402         }
 403
 404         /*
 405          * Now write a value and read it back to see if it matches,
 406          * this is needed to detect certain hardware emulators (qemu/kvm)
 407          * that don't trap on the MSR access and always return 0s.
 408          */
 409         val = 0xabcdUL;
 410         ret = checking_wrmsrl(x86_pmu.perfctr, val);
 411         ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new);
 412         if (ret || val != val_new)
 413                 goto msr_fail;
 414
 415         return true;
 416
 417 bios_fail:
 418         printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
 419         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 420         return false;
 421
 422 msr_fail:
 423         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 424         return false;
 425 }
 426
 427 static void reserve_ds_buffers(void);
 428 static void release_ds_buffers(void);
 429
 430 static void hw_perf_event_destroy(struct perf_event *event)
 431 {
 432         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 433                 release_pmc_hardware();
 434                 release_ds_buffers();
 435                 mutex_unlock(&pmc_reserve_mutex);
 436         }
 437 }
 438
 439 static inline int x86_pmu_initialized(void)
 440 {
 441         return x86_pmu.handle_irq != NULL;
 442 }
 443
 444 static inline int
 445 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 446 {
 447         unsigned int cache_type, cache_op, cache_result;
 448         u64 config, val;
 449
 450         config = attr->config;
 451
 452         cache_type = (config >>  0) & 0xff;
 453         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 454                 return -EINVAL;
 455
 456         cache_op = (config >>  8) & 0xff;
 457         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 458                 return -EINVAL;
 459
 460         cache_result = (config >> 16) & 0xff;
 461         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 462                 return -EINVAL;
 463
 464         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 465
 466         if (val == 0)
 467                 return -ENOENT;
 468
 469         if (val == -1)
 470                 return -EINVAL;
 471
 472         hwc->config |= val;
 473
 474         return 0;
 475 }
 476
 477 static int x86_setup_perfctr(struct perf_event *event)
 478 {
 479         struct perf_event_attr *attr = &event->attr;
 480         struct hw_perf_event *hwc = &event->hw;
 481         u64 config;
 482
 483         if (!is_sampling_event(event)) {
 484                 hwc->sample_period = x86_pmu.max_period;
 485                 hwc->last_period = hwc->sample_period;
 486                 local64_set(&hwc->period_left, hwc->sample_period);
 487         } else {
 488                 /*
 489                  * If we have a PMU initialized but no APIC
 490                  * interrupts, we cannot sample hardware
 491                  * events (user-space has to fall back and
 492                  * sample via a hrtimer based software event):
 493                  */
 494                 if (!x86_pmu.apic)
 495                         return -EOPNOTSUPP;
 496         }
 497
 498         if (attr->type == PERF_TYPE_RAW)
 499                 return 0;
 500
 501         if (attr->type == PERF_TYPE_HW_CACHE)
 502                 return set_ext_hw_attr(hwc, attr);
 503
 504         if (attr->config >= x86_pmu.max_events)
 505                 return -EINVAL;
 506
 507         /*
 508          * The generic map:
 509          */
 510         config = x86_pmu.event_map(attr->config);
 511
 512         if (config == 0)
 513                 return -ENOENT;
 514
 515         if (config == -1LL)
 516                 return -EINVAL;
 517
 518         /*
 519          * Branch tracing:
 520          */
 521         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 522             (hwc->sample_period == 1)) {
 523                 /* BTS is not supported by this architecture. */
 524                 if (!x86_pmu.bts_active)
 525                         return -EOPNOTSUPP;
 526
 527                 /* BTS is currently only allowed for user-mode. */
 528                 if (!attr->exclude_kernel)
 529                         return -EOPNOTSUPP;
 530         }
 531
 532         hwc->config |= config;
 533
 534         return 0;
 535 }
 536
 537 static int x86_pmu_hw_config(struct perf_event *event)
 538 {
 539         if (event->attr.precise_ip) {
 540                 int precise = 0;
 541
 542                 /* Support for constant skid */
 543                 if (x86_pmu.pebs_active) {
 544                         precise++;
 545
 546                         /* Support for IP fixup */
 547                         if (x86_pmu.lbr_nr)
 548                                 precise++;
 549                 }
 550
 551                 if (event->attr.precise_ip > precise)
 552                         return -EOPNOTSUPP;
 553         }
 554
 555         /*
 556          * Generate PMC IRQs:
 557          * (keep 'enabled' bit clear for now)
 558          */
 559         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 560
 561         /*
 562          * Count user and OS events unless requested not to
 563          */
 564         if (!event->attr.exclude_user)
 565                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 566         if (!event->attr.exclude_kernel)
 567                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 568
 569         if (event->attr.type == PERF_TYPE_RAW)
 570                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 571
 572         return x86_setup_perfctr(event);
 573 }
 574
 575 /*
 576  * Setup the hardware configuration for a given attr_type
 577  */
 578 static int __x86_pmu_event_init(struct perf_event *event)
 579 {
 580         int err;
 581
 582         if (!x86_pmu_initialized())
 583                 return -ENODEV;
 584
 585         err = 0;
 586         if (!atomic_inc_not_zero(&active_events)) {
 587                 mutex_lock(&pmc_reserve_mutex);
 588                 if (atomic_read(&active_events) == 0) {
 589                         if (!reserve_pmc_hardware())
 590                                 err = -EBUSY;
 591                         else
 592                                 reserve_ds_buffers();
 593                 }
 594                 if (!err)
 595                         atomic_inc(&active_events);
 596                 mutex_unlock(&pmc_reserve_mutex);
 597         }
 598         if (err)
 599                 return err;
 600
 601         event->destroy = hw_perf_event_destroy;
 602
 603         event->hw.idx = -1;
 604         event->hw.last_cpu = -1;
 605         event->hw.last_tag = ~0ULL;
 606
 607         return x86_pmu.hw_config(event);
 608 }
 609
 610 static void x86_pmu_disable_all(void)
 611 {
 612         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 613         int idx;
 614
 615         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 616                 u64 val;
 617
 618                 if (!test_bit(idx, cpuc->active_mask))
 619                         continue;
 620                 rdmsrl(x86_pmu.eventsel + idx, val);
 621                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 622                         continue;
 623                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 624                 wrmsrl(x86_pmu.eventsel + idx, val);
 625         }
 626 }
 627
 628 static void x86_pmu_disable(struct pmu *pmu)
 629 {
 630         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 631
 632         if (!x86_pmu_initialized())
 633                 return;
 634
 635         if (!cpuc->enabled)
 636                 return;
 637
 638         cpuc->n_added = 0;
 639         cpuc->enabled = 0;
 640         barrier();
 641
 642         x86_pmu.disable_all();
 643 }
 644
 645 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 646                                           u64 enable_mask)
 647 {
 648         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 649 }
 650
 651 static void x86_pmu_enable_all(int added)
 652 {
 653         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 654         int idx;
 655
 656         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 657                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 658
 659                 if (!test_bit(idx, cpuc->active_mask))
 660                         continue;
 661
 662                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 663         }
 664 }
 665
 666 static struct pmu pmu;
 667
 668 static inline int is_x86_event(struct perf_event *event)
 669 {
 670         return event->pmu == &pmu;
 671 }
 672
 673 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 674 {
 675         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 676         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 677         int i, j, w, wmax, num = 0;
 678         struct hw_perf_event *hwc;
 679
 680         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 681
 682         for (i = 0; i < n; i++) {
 683                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 684                 constraints[i] = c;
 685         }
 686
 687         /*
 688          * fastpath, try to reuse previous register
 689          */
 690         for (i = 0; i < n; i++) {
 691                 hwc = &cpuc->event_list[i]->hw;
 692                 c = constraints[i];
 693
 694                 /* never assigned */
 695                 if (hwc->idx == -1)
 696                         break;
 697
 698                 /* constraint still honored */
 699                 if (!test_bit(hwc->idx, c->idxmsk))
 700                         break;
 701
 702                 /* not already used */
 703                 if (test_bit(hwc->idx, used_mask))
 704                         break;
 705
 706                 __set_bit(hwc->idx, used_mask);
 707                 if (assign)
 708                         assign[i] = hwc->idx;
 709         }
 710         if (i == n)
 711                 goto done;
 712
 713         /*
 714          * begin slow path
 715          */
 716
 717         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 718
 719         /*
 720          * weight = number of possible counters
 721          *
 722          * 1    = most constrained, only works on one counter
 723          * wmax = least constrained, works on any counter
 724          *
 725          * assign events to counters starting with most
 726          * constrained events.
 727          */
 728         wmax = x86_pmu.num_counters;
 729
 730         /*
 731          * when fixed event counters are present,
 732          * wmax is incremented by 1 to account
 733          * for one more choice
 734          */
 735         if (x86_pmu.num_counters_fixed)
 736                 wmax++;
 737
 738         for (w = 1, num = n; num && w <= wmax; w++) {
 739                 /* for each event */
 740                 for (i = 0; num && i < n; i++) {
 741                         c = constraints[i];
 742                         hwc = &cpuc->event_list[i]->hw;
 743
 744                         if (c->weight != w)
 745                                 continue;
 746
 747                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 748                                 if (!test_bit(j, used_mask))
 749                                         break;
 750                         }
 751
 752                         if (j == X86_PMC_IDX_MAX)
 753                                 break;
 754
 755                         __set_bit(j, used_mask);
 756
 757                         if (assign)
 758                                 assign[i] = j;
 759                         num--;
 760                 }
 761         }
 762 done:
 763         /*
 764          * scheduling failed or is just a simulation,
 765          * free resources if necessary
 766          */
 767         if (!assign || num) {
 768                 for (i = 0; i < n; i++) {
 769                         if (x86_pmu.put_event_constraints)
 770                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 771                 }
 772         }
 773         return num ? -ENOSPC : 0;
 774 }
 775
 776 /*
 777  * dogrp: true if must collect siblings events (group)
 778  * returns total number of events and error code
 779  */
 780 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 781 {
 782         struct perf_event *event;
 783         int n, max_count;
 784
 785         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 786
 787         /* current number of events already accepted */
 788         n = cpuc->n_events;
 789
 790         if (is_x86_event(leader)) {
 791                 if (n >= max_count)
 792                         return -ENOSPC;
 793                 cpuc->event_list[n] = leader;
 794                 n++;
 795         }
 796         if (!dogrp)
 797                 return n;
 798
 799         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 800                 if (!is_x86_event(event) ||
 801                     event->state <= PERF_EVENT_STATE_OFF)
 802                         continue;
 803
 804                 if (n >= max_count)
 805                         return -ENOSPC;
 806
 807                 cpuc->event_list[n] = event;
 808                 n++;
 809         }
 810         return n;
 811 }
 812
 813 static inline void x86_assign_hw_event(struct perf_event *event,
 814                                 struct cpu_hw_events *cpuc, int i)
 815 {
 816         struct hw_perf_event *hwc = &event->hw;
 817
 818         hwc->idx = cpuc->assign[i];
 819         hwc->last_cpu = smp_processor_id();
 820         hwc->last_tag = ++cpuc->tags[i];
 821
 822         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 823                 hwc->config_base = 0;
 824                 hwc->event_base = 0;
 825         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 826                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 827                 /*
 828                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 829                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 830                  */
 831                 hwc->event_base =
 832                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 833         } else {
 834                 hwc->config_base = x86_pmu.eventsel;
 835                 hwc->event_base  = x86_pmu.perfctr;
 836         }
 837 }
 838
 839 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 840                                         struct cpu_hw_events *cpuc,
 841                                         int i)
 842 {
 843         return hwc->idx == cpuc->assign[i] &&
 844                 hwc->last_cpu == smp_processor_id() &&
 845                 hwc->last_tag == cpuc->tags[i];
 846 }
 847
 848 static void x86_pmu_start(struct perf_event *event, int flags);
 849 static void x86_pmu_stop(struct perf_event *event, int flags);
 850
 851 static void x86_pmu_enable(struct pmu *pmu)
 852 {
 853         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 854         struct perf_event *event;
 855         struct hw_perf_event *hwc;
 856         int i, added = cpuc->n_added;
 857
 858         if (!x86_pmu_initialized())
 859                 return;
 860
 861         if (cpuc->enabled)
 862                 return;
 863
 864         if (cpuc->n_added) {
 865                 int n_running = cpuc->n_events - cpuc->n_added;
 866                 /*
 867                  * apply assignment obtained either from
 868                  * hw_perf_group_sched_in() or x86_pmu_enable()
 869                  *
 870                  * step1: save events moving to new counters
 871                  * step2: reprogram moved events into new counters
 872                  */
 873                 for (i = 0; i < n_running; i++) {
 874                         event = cpuc->event_list[i];
 875                         hwc = &event->hw;
 876
 877                         /*
 878                          * we can avoid reprogramming counter if:
 879                          * - assigned same counter as last time
 880                          * - running on same CPU as last time
 881                          * - no other event has used the counter since
 882                          */
 883                         if (hwc->idx == -1 ||
 884                             match_prev_assignment(hwc, cpuc, i))
 885                                 continue;
 886
 887                         /*
 888                          * Ensure we don't accidentally enable a stopped
 889                          * counter simply because we rescheduled.
 890                          */
 891                         if (hwc->state & PERF_HES_STOPPED)
 892                                 hwc->state |= PERF_HES_ARCH;
 893
 894                         x86_pmu_stop(event, PERF_EF_UPDATE);
 895                 }
 896
 897                 for (i = 0; i < cpuc->n_events; i++) {
 898                         event = cpuc->event_list[i];
 899                         hwc = &event->hw;
 900
 901                         if (!match_prev_assignment(hwc, cpuc, i))
 902                                 x86_assign_hw_event(event, cpuc, i);
 903                         else if (i < n_running)
 904                                 continue;
 905
 906                         if (hwc->state & PERF_HES_ARCH)
 907                                 continue;
 908
 909                         x86_pmu_start(event, PERF_EF_RELOAD);
 910                 }
 911                 cpuc->n_added = 0;
 912                 perf_events_lapic_init();
 913         }
 914
 915         cpuc->enabled = 1;
 916         barrier();
 917
 918         x86_pmu.enable_all(added);
 919 }
 920
 921 static inline void x86_pmu_disable_event(struct perf_event *event)
 922 {
 923         struct hw_perf_event *hwc = &event->hw;
 924
 925         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 926 }
 927
 928 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 929
 930 /*
 931  * Set the next IRQ period, based on the hwc->period_left value.
 932  * To be called with the event disabled in hw:
 933  */
 934 static int
 935 x86_perf_event_set_period(struct perf_event *event)
 936 {
 937         struct hw_perf_event *hwc = &event->hw;
 938         s64 left = local64_read(&hwc->period_left);
 939         s64 period = hwc->sample_period;
 940         int ret = 0, idx = hwc->idx;
 941
 942         if (idx == X86_PMC_IDX_FIXED_BTS)
 943                 return 0;
 944
 945         /*
 946          * If we are way outside a reasonable range then just skip forward:
 947          */
 948         if (unlikely(left <= -period)) {
 949                 left = period;
 950                 local64_set(&hwc->period_left, left);
 951                 hwc->last_period = period;
 952                 ret = 1;
 953         }
 954
 955         if (unlikely(left <= 0)) {
 956                 left += period;
 957                 local64_set(&hwc->period_left, left);
 958                 hwc->last_period = period;
 959                 ret = 1;
 960         }
 961         /*
 962          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 963          */
 964         if (unlikely(left < 2))
 965                 left = 2;
 966
 967         if (left > x86_pmu.max_period)
 968                 left = x86_pmu.max_period;
 969
 970         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 971
 972         /*
 973          * The hw event starts counting from this event offset,
 974          * mark it to be able to extra future deltas:
 975          */
 976         local64_set(&hwc->prev_count, (u64)-left);
 977
 978         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 979
 980         /*
 981          * Due to erratum on certan cpu we need
 982          * a second write to be sure the register
 983          * is updated properly
 984          */
 985         if (x86_pmu.perfctr_second_write) {
 986                 wrmsrl(hwc->event_base + idx,
 987                         (u64)(-left) & x86_pmu.cntval_mask);
 988         }
 989
 990         perf_event_update_userpage(event);
 991
 992         return ret;
 993 }
 994
 995 static void x86_pmu_enable_event(struct perf_event *event)
 996 {
 997         if (__this_cpu_read(cpu_hw_events.enabled))
 998                 __x86_pmu_enable_event(&event->hw,
 999                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1000 }
1001
1002 /*
1003  * Add a single event to the PMU.
1004  *
1005  * The event is added to the group of enabled events
1006  * but only if it can be scehduled with existing events.
1007  */
1008 static int x86_pmu_add(struct perf_event *event, int flags)
1009 {
1010         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1011         struct hw_perf_event *hwc;
1012         int assign[X86_PMC_IDX_MAX];
1013         int n, n0, ret;
1014
1015         hwc = &event->hw;
1016
1017         perf_pmu_disable(event->pmu);
1018         n0 = cpuc->n_events;
1019         ret = n = collect_events(cpuc, event, false);
1020         if (ret < 0)
1021                 goto out;
1022
1023         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1024         if (!(flags & PERF_EF_START))
1025                 hwc->state |= PERF_HES_ARCH;
1026
1027         /*
1028          * If group events scheduling transaction was started,
1029          * skip the schedulability test here, it will be peformed
1030          * at commit time (->commit_txn) as a whole
1031          */
1032         if (cpuc->group_flag & PERF_EVENT_TXN)
1033                 goto done_collect;
1034
1035         ret = x86_pmu.schedule_events(cpuc, n, assign);
1036         if (ret)
1037                 goto out;
1038         /*
1039          * copy new assignment, now we know it is possible
1040          * will be used by hw_perf_enable()
1041          */
1042         memcpy(cpuc->assign, assign, n*sizeof(int));
1043
1044 done_collect:
1045         cpuc->n_events = n;
1046         cpuc->n_added += n - n0;
1047         cpuc->n_txn += n - n0;
1048
1049         ret = 0;
1050 out:
1051         perf_pmu_enable(event->pmu);
1052         return ret;
1053 }
1054
1055 static void x86_pmu_start(struct perf_event *event, int flags)
1056 {
1057         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1058         int idx = event->hw.idx;
1059
1060         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1061                 return;
1062
1063         if (WARN_ON_ONCE(idx == -1))
1064                 return;
1065
1066         if (flags & PERF_EF_RELOAD) {
1067                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1068                 x86_perf_event_set_period(event);
1069         }
1070
1071         event->hw.state = 0;
1072
1073         cpuc->events[idx] = event;
1074         __set_bit(idx, cpuc->active_mask);
1075         __set_bit(idx, cpuc->running);
1076         x86_pmu.enable(event);
1077         perf_event_update_userpage(event);
1078 }
1079
1080 void perf_event_print_debug(void)
1081 {
1082         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1083         u64 pebs;
1084         struct cpu_hw_events *cpuc;
1085         unsigned long flags;
1086         int cpu, idx;
1087
1088         if (!x86_pmu.num_counters)
1089                 return;
1090
1091         local_irq_save(flags);
1092
1093         cpu = smp_processor_id();
1094         cpuc = &per_cpu(cpu_hw_events, cpu);
1095
1096         if (x86_pmu.version >= 2) {
1097                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1098                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1099                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1100                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1101                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1102
1103                 pr_info("\n");
1104                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1105                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1106                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1107                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1108                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1109         }
1110         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1111
1112         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1113                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1114                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1115
1116                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1117
1118                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1119                         cpu, idx, pmc_ctrl);
1120                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1121                         cpu, idx, pmc_count);
1122                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1123                         cpu, idx, prev_left);
1124         }
1125         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1126                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1127
1128                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1129                         cpu, idx, pmc_count);
1130         }
1131         local_irq_restore(flags);
1132 }
1133
1134 static void x86_pmu_stop(struct perf_event *event, int flags)
1135 {
1136         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1137         struct hw_perf_event *hwc = &event->hw;
1138
1139         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1140                 x86_pmu.disable(event);
1141                 cpuc->events[hwc->idx] = NULL;
1142                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1143                 hwc->state |= PERF_HES_STOPPED;
1144         }
1145
1146         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1147                 /*
1148                  * Drain the remaining delta count out of a event
1149                  * that we are disabling:
1150                  */
1151                 x86_perf_event_update(event);
1152                 hwc->state |= PERF_HES_UPTODATE;
1153         }
1154 }
1155
1156 static void x86_pmu_del(struct perf_event *event, int flags)
1157 {
1158         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1159         int i;
1160
1161         /*
1162          * If we're called during a txn, we don't need to do anything.
1163          * The events never got scheduled and ->cancel_txn will truncate
1164          * the event_list.
1165          */
1166         if (cpuc->group_flag & PERF_EVENT_TXN)
1167                 return;
1168
1169         x86_pmu_stop(event, PERF_EF_UPDATE);
1170
1171         for (i = 0; i < cpuc->n_events; i++) {
1172                 if (event == cpuc->event_list[i]) {
1173
1174                         if (x86_pmu.put_event_constraints)
1175                                 x86_pmu.put_event_constraints(cpuc, event);
1176
1177                         while (++i < cpuc->n_events)
1178                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1179
1180                         --cpuc->n_events;
1181                         break;
1182                 }
1183         }
1184         perf_event_update_userpage(event);
1185 }
1186
1187 static int x86_pmu_handle_irq(struct pt_regs *regs)
1188 {
1189         struct perf_sample_data data;
1190         struct cpu_hw_events *cpuc;
1191         struct perf_event *event;
1192         int idx, handled = 0;
1193         u64 val;
1194
1195         perf_sample_data_init(&data, 0);
1196
1197         cpuc = &__get_cpu_var(cpu_hw_events);
1198
1199         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1200                 if (!test_bit(idx, cpuc->active_mask)) {
1201                         /*
1202                          * Though we deactivated the counter some cpus
1203                          * might still deliver spurious interrupts still
1204                          * in flight. Catch them:
1205                          */
1206                         if (__test_and_clear_bit(idx, cpuc->running))
1207                                 handled++;
1208                         continue;
1209                 }
1210
1211                 event = cpuc->events[idx];
1212
1213                 val = x86_perf_event_update(event);
1214                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1215                         continue;
1216
1217                 /*
1218                  * event overflow
1219                  */
1220                 handled++;
1221                 data.period     = event->hw.last_period;
1222
1223                 if (!x86_perf_event_set_period(event))
1224                         continue;
1225
1226                 if (perf_event_overflow(event, 1, &data, regs))
1227                         x86_pmu_stop(event, 0);
1228         }
1229
1230         if (handled)
1231                 inc_irq_stat(apic_perf_irqs);
1232
1233         return handled;
1234 }
1235
1236 void perf_events_lapic_init(void)
1237 {
1238         if (!x86_pmu.apic || !x86_pmu_initialized())
1239                 return;
1240
1241         /*
1242          * Always use NMI for PMU
1243          */
1244         apic_write(APIC_LVTPC, APIC_DM_NMI);
1245 }
1246
1247 struct pmu_nmi_state {
1248         unsigned int    marked;
1249         int             handled;
1250 };
1251
1252 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1253
1254 static int __kprobes
1255 perf_event_nmi_handler(struct notifier_block *self,
1256                          unsigned long cmd, void *__args)
1257 {
1258         struct die_args *args = __args;
1259         unsigned int this_nmi;
1260         int handled;
1261
1262         if (!atomic_read(&active_events))
1263                 return NOTIFY_DONE;
1264
1265         switch (cmd) {
1266         case DIE_NMI:
1267                 break;
1268         case DIE_NMIUNKNOWN:
1269                 this_nmi = percpu_read(irq_stat.__nmi_count);
1270                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1271                         /* let the kernel handle the unknown nmi */
1272                         return NOTIFY_DONE;
1273                 /*
1274                  * This one is a PMU back-to-back nmi. Two events
1275                  * trigger 'simultaneously' raising two back-to-back
1276                  * NMIs. If the first NMI handles both, the latter
1277                  * will be empty and daze the CPU. So, we drop it to
1278                  * avoid false-positive 'unknown nmi' messages.
1279                  */
1280                 return NOTIFY_STOP;
1281         default:
1282                 return NOTIFY_DONE;
1283         }
1284
1285         apic_write(APIC_LVTPC, APIC_DM_NMI);
1286
1287         handled = x86_pmu.handle_irq(args->regs);
1288         if (!handled)
1289                 return NOTIFY_DONE;
1290
1291         this_nmi = percpu_read(irq_stat.__nmi_count);
1292         if ((handled > 1) ||
1293                 /* the next nmi could be a back-to-back nmi */
1294             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1295              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1296                 /*
1297                  * We could have two subsequent back-to-back nmis: The
1298                  * first handles more than one counter, the 2nd
1299                  * handles only one counter and the 3rd handles no
1300                  * counter.
1301                  *
1302                  * This is the 2nd nmi because the previous was
1303                  * handling more than one counter. We will mark the
1304                  * next (3rd) and then drop it if unhandled.
1305                  */
1306                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1307                 __this_cpu_write(pmu_nmi.handled, handled);
1308         }
1309
1310         return NOTIFY_STOP;
1311 }
1312
1313 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1314         .notifier_call          = perf_event_nmi_handler,
1315         .next                   = NULL,
1316         .priority               = NMI_LOCAL_LOW_PRIOR,
1317 };
1318
1319 static struct event_constraint unconstrained;
1320 static struct event_constraint emptyconstraint;
1321
1322 static struct event_constraint *
1323 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1324 {
1325         struct event_constraint *c;
1326
1327         if (x86_pmu.event_constraints) {
1328                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1329                         if ((event->hw.config & c->cmask) == c->code)
1330                                 return c;
1331                 }
1332         }
1333
1334         return &unconstrained;
1335 }
1336
1337 #include "perf_event_amd.c"
1338 #include "perf_event_p6.c"
1339 #include "perf_event_p4.c"
1340 #include "perf_event_intel_lbr.c"
1341 #include "perf_event_intel_ds.c"
1342 #include "perf_event_intel.c"
1343
1344 static int __cpuinit
1345 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1346 {
1347         unsigned int cpu = (long)hcpu;
1348         int ret = NOTIFY_OK;
1349
1350         switch (action & ~CPU_TASKS_FROZEN) {
1351         case CPU_UP_PREPARE:
1352                 if (x86_pmu.cpu_prepare)
1353                         ret = x86_pmu.cpu_prepare(cpu);
1354                 break;
1355
1356         case CPU_STARTING:
1357                 if (x86_pmu.cpu_starting)
1358                         x86_pmu.cpu_starting(cpu);
1359                 break;
1360
1361         case CPU_DYING:
1362                 if (x86_pmu.cpu_dying)
1363                         x86_pmu.cpu_dying(cpu);
1364                 break;
1365
1366         case CPU_UP_CANCELED:
1367         case CPU_DEAD:
1368                 if (x86_pmu.cpu_dead)
1369                         x86_pmu.cpu_dead(cpu);
1370                 break;
1371
1372         default:
1373                 break;
1374         }
1375
1376         return ret;
1377 }
1378
1379 static void __init pmu_check_apic(void)
1380 {
1381         if (cpu_has_apic)
1382                 return;
1383
1384         x86_pmu.apic = 0;
1385         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1386         pr_info("no hardware sampling interrupt available.\n");
1387 }
1388
1389 static int __init init_hw_perf_events(void)
1390 {
1391         struct event_constraint *c;
1392         int err;
1393
1394         pr_info("Performance Events: ");
1395
1396         switch (boot_cpu_data.x86_vendor) {
1397         case X86_VENDOR_INTEL:
1398                 err = intel_pmu_init();
1399                 break;
1400         case X86_VENDOR_AMD:
1401                 err = amd_pmu_init();
1402                 break;
1403         default:
1404                 return 0;
1405         }
1406         if (err != 0) {
1407                 pr_cont("no PMU driver, software events only.\n");
1408                 return 0;
1409         }
1410
1411         pmu_check_apic();
1412
1413         /* sanity check that the hardware exists or is emulated */
1414         if (!check_hw_exists())
1415                 return 0;
1416
1417         pr_cont("%s PMU driver.\n", x86_pmu.name);
1418
1419         if (x86_pmu.quirks)
1420                 x86_pmu.quirks();
1421
1422         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1423                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1424                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1425                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1426         }
1427         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1428
1429         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1430                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1431                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1432                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1433         }
1434
1435         x86_pmu.intel_ctrl |=
1436                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1437
1438         perf_events_lapic_init();
1439         register_die_notifier(&perf_event_nmi_notifier);
1440
1441         unconstrained = (struct event_constraint)
1442                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1443                                    0, x86_pmu.num_counters);
1444
1445         if (x86_pmu.event_constraints) {
1446                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1447                         if (c->cmask != X86_RAW_EVENT_MASK)
1448                                 continue;
1449
1450                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1451                         c->weight += x86_pmu.num_counters;
1452                 }
1453         }
1454
1455         pr_info("... version:                %d\n",     x86_pmu.version);
1456         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1457         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1458         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1459         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1460         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1461         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1462
1463         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1464         perf_cpu_notifier(x86_pmu_notifier);
1465
1466         return 0;
1467 }
1468 early_initcall(init_hw_perf_events);
1469
1470 static inline void x86_pmu_read(struct perf_event *event)
1471 {
1472         x86_perf_event_update(event);
1473 }
1474
1475 /*
1476  * Start group events scheduling transaction
1477  * Set the flag to make pmu::enable() not perform the
1478  * schedulability test, it will be performed at commit time
1479  */
1480 static void x86_pmu_start_txn(struct pmu *pmu)
1481 {
1482         perf_pmu_disable(pmu);
1483         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1484         __this_cpu_write(cpu_hw_events.n_txn, 0);
1485 }
1486
1487 /*
1488  * Stop group events scheduling transaction
1489  * Clear the flag and pmu::enable() will perform the
1490  * schedulability test.
1491  */
1492 static void x86_pmu_cancel_txn(struct pmu *pmu)
1493 {
1494         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1495         /*
1496          * Truncate the collected events.
1497          */
1498         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1499         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1500         perf_pmu_enable(pmu);
1501 }
1502
1503 /*
1504  * Commit group events scheduling transaction
1505  * Perform the group schedulability test as a whole
1506  * Return 0 if success
1507  */
1508 static int x86_pmu_commit_txn(struct pmu *pmu)
1509 {
1510         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1511         int assign[X86_PMC_IDX_MAX];
1512         int n, ret;
1513
1514         n = cpuc->n_events;
1515
1516         if (!x86_pmu_initialized())
1517                 return -EAGAIN;
1518
1519         ret = x86_pmu.schedule_events(cpuc, n, assign);
1520         if (ret)
1521                 return ret;
1522
1523         /*
1524          * copy new assignment, now we know it is possible
1525          * will be used by hw_perf_enable()
1526          */
1527         memcpy(cpuc->assign, assign, n*sizeof(int));
1528
1529         cpuc->group_flag &= ~PERF_EVENT_TXN;
1530         perf_pmu_enable(pmu);
1531         return 0;
1532 }
1533
1534 /*
1535  * validate that we can schedule this event
1536  */
1537 static int validate_event(struct perf_event *event)
1538 {
1539         struct cpu_hw_events *fake_cpuc;
1540         struct event_constraint *c;
1541         int ret = 0;
1542
1543         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1544         if (!fake_cpuc)
1545                 return -ENOMEM;
1546
1547         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1548
1549         if (!c || !c->weight)
1550                 ret = -ENOSPC;
1551
1552         if (x86_pmu.put_event_constraints)
1553                 x86_pmu.put_event_constraints(fake_cpuc, event);
1554
1555         kfree(fake_cpuc);
1556
1557         return ret;
1558 }
1559
1560 /*
1561  * validate a single event group
1562  *
1563  * validation include:
1564  *      - check events are compatible which each other
1565  *      - events do not compete for the same counter
1566  *      - number of events <= number of counters
1567  *
1568  * validation ensures the group can be loaded onto the
1569  * PMU if it was the only group available.
1570  */
1571 static int validate_group(struct perf_event *event)
1572 {
1573         struct perf_event *leader = event->group_leader;
1574         struct cpu_hw_events *fake_cpuc;
1575         int ret, n;
1576
1577         ret = -ENOMEM;
1578         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1579         if (!fake_cpuc)
1580                 goto out;
1581
1582         /*
1583          * the event is not yet connected with its
1584          * siblings therefore we must first collect
1585          * existing siblings, then add the new event
1586          * before we can simulate the scheduling
1587          */
1588         ret = -ENOSPC;
1589         n = collect_events(fake_cpuc, leader, true);
1590         if (n < 0)
1591                 goto out_free;
1592
1593         fake_cpuc->n_events = n;
1594         n = collect_events(fake_cpuc, event, false);
1595         if (n < 0)
1596                 goto out_free;
1597
1598         fake_cpuc->n_events = n;
1599
1600         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1601
1602 out_free:
1603         kfree(fake_cpuc);
1604 out:
1605         return ret;
1606 }
1607
1608 static int x86_pmu_event_init(struct perf_event *event)
1609 {
1610         struct pmu *tmp;
1611         int err;
1612
1613         switch (event->attr.type) {
1614         case PERF_TYPE_RAW:
1615         case PERF_TYPE_HARDWARE:
1616         case PERF_TYPE_HW_CACHE:
1617                 break;
1618
1619         default:
1620                 return -ENOENT;
1621         }
1622
1623         err = __x86_pmu_event_init(event);
1624         if (!err) {
1625                 /*
1626                  * we temporarily connect event to its pmu
1627                  * such that validate_group() can classify
1628                  * it as an x86 event using is_x86_event()
1629                  */
1630                 tmp = event->pmu;
1631                 event->pmu = &pmu;
1632
1633                 if (event->group_leader != event)
1634                         err = validate_group(event);
1635                 else
1636                         err = validate_event(event);
1637
1638                 event->pmu = tmp;
1639         }
1640         if (err) {
1641                 if (event->destroy)
1642                         event->destroy(event);
1643         }
1644
1645         return err;
1646 }
1647
1648 static struct pmu pmu = {
1649         .pmu_enable     = x86_pmu_enable,
1650         .pmu_disable    = x86_pmu_disable,
1651
1652         .event_init     = x86_pmu_event_init,
1653
1654         .add            = x86_pmu_add,
1655         .del            = x86_pmu_del,
1656         .start          = x86_pmu_start,
1657         .stop           = x86_pmu_stop,
1658         .read           = x86_pmu_read,
1659
1660         .start_txn      = x86_pmu_start_txn,
1661         .cancel_txn     = x86_pmu_cancel_txn,
1662         .commit_txn     = x86_pmu_commit_txn,
1663 };
1664
1665 /*
1666  * callchain support
1667  */
1668
1669 static void
1670 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1671 {
1672         /* Ignore warnings */
1673 }
1674
1675 static void backtrace_warning(void *data, char *msg)
1676 {
1677         /* Ignore warnings */
1678 }
1679
1680 static int backtrace_stack(void *data, char *name)
1681 {
1682         return 0;
1683 }
1684
1685 static void backtrace_address(void *data, unsigned long addr, int reliable)
1686 {
1687         struct perf_callchain_entry *entry = data;
1688
1689         perf_callchain_store(entry, addr);
1690 }
1691
1692 static const struct stacktrace_ops backtrace_ops = {
1693         .warning                = backtrace_warning,
1694         .warning_symbol         = backtrace_warning_symbol,
1695         .stack                  = backtrace_stack,
1696         .address                = backtrace_address,
1697         .walk_stack             = print_context_stack_bp,
1698 };
1699
1700 void
1701 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1702 {
1703         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1704                 /* TODO: We don't support guest os callchain now */
1705                 return;
1706         }
1707
1708         perf_callchain_store(entry, regs->ip);
1709
1710         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1711 }
1712
1713 #ifdef CONFIG_COMPAT
1714 static inline int
1715 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1716 {
1717         /* 32-bit process in 64-bit kernel. */
1718         struct stack_frame_ia32 frame;
1719         const void __user *fp;
1720
1721         if (!test_thread_flag(TIF_IA32))
1722                 return 0;
1723
1724         fp = compat_ptr(regs->bp);
1725         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1726                 unsigned long bytes;
1727                 frame.next_frame     = 0;
1728                 frame.return_address = 0;
1729
1730                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1731                 if (bytes != sizeof(frame))
1732                         break;
1733
1734                 if (fp < compat_ptr(regs->sp))
1735                         break;
1736
1737                 perf_callchain_store(entry, frame.return_address);
1738                 fp = compat_ptr(frame.next_frame);
1739         }
1740         return 1;
1741 }
1742 #else
1743 static inline int
1744 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1745 {
1746     return 0;
1747 }
1748 #endif
1749
1750 void
1751 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1752 {
1753         struct stack_frame frame;
1754         const void __user *fp;
1755
1756         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1757                 /* TODO: We don't support guest os callchain now */
1758                 return;
1759         }
1760
1761         fp = (void __user *)regs->bp;
1762
1763         perf_callchain_store(entry, regs->ip);
1764
1765         if (perf_callchain_user32(regs, entry))
1766                 return;
1767
1768         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1769                 unsigned long bytes;
1770                 frame.next_frame             = NULL;
1771                 frame.return_address = 0;
1772
1773                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1774                 if (bytes != sizeof(frame))
1775                         break;
1776
1777                 if ((unsigned long)fp < regs->sp)
1778                         break;
1779
1780                 perf_callchain_store(entry, frame.return_address);
1781                 fp = frame.next_frame;
1782         }
1783 }
1784
1785 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1786 {
1787         unsigned long ip;
1788
1789         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1790                 ip = perf_guest_cbs->get_guest_ip();
1791         else
1792                 ip = instruction_pointer(regs);
1793
1794         return ip;
1795 }
1796
1797 unsigned long perf_misc_flags(struct pt_regs *regs)
1798 {
1799         int misc = 0;
1800
1801         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1802                 if (perf_guest_cbs->is_user_mode())
1803                         misc |= PERF_RECORD_MISC_GUEST_USER;
1804                 else
1805                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1806         } else {
1807                 if (user_mode(regs))
1808                         misc |= PERF_RECORD_MISC_USER;
1809                 else
1810                         misc |= PERF_RECORD_MISC_KERNEL;
1811         }
1812
1813         if (regs->flags & PERF_EFLAGS_EXACT)
1814                 misc |= PERF_RECORD_MISC_EXACT_IP;
1815
1816         return misc;
1817 }