arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         unsigned long size, len = 0;
  53         struct page *page;
  54         void *map;
  55         int ret;
  56
  57         do {
  58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  59                 if (!ret)
  60                         break;
  61
  62                 offset = addr & (PAGE_SIZE - 1);
  63                 size = min(PAGE_SIZE - offset, n - len);
  64
  65                 map = kmap_atomic(page);
  66                 memcpy(to, map+offset, size);
  67                 kunmap_atomic(map);
  68                 put_page(page);
  69
  70                 len  += size;
  71                 to   += size;
  72                 addr += size;
  73
  74         } while (len < n);
  75
  76         return len;
  77 }
  78
  79 struct event_constraint {
  80         union {
  81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  82                 u64             idxmsk64;
  83         };
  84         u64     code;
  85         u64     cmask;
  86         int     weight;
  87 };
  88
  89 struct amd_nb {
  90         int nb_id;  /* NorthBridge id */
  91         int refcnt; /* reference count */
  92         struct perf_event *owners[X86_PMC_IDX_MAX];
  93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  94 };
  95
  96 #define MAX_LBR_ENTRIES         16
  97
  98 struct cpu_hw_events {
  99         /*
 100          * Generic x86 PMC bits
 101          */
 102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171
 172 #define EVENT_CONSTRAINT_END            \
 173         EVENT_CONSTRAINT(0, 0, 0)
 174
 175 #define for_each_event_constraint(e, c) \
 176         for ((e) = (c); (e)->weight; (e)++)
 177
 178 union perf_capabilities {
 179         struct {
 180                 u64     lbr_format    : 6;
 181                 u64     pebs_trap     : 1;
 182                 u64     pebs_arch_reg : 1;
 183                 u64     pebs_format   : 4;
 184                 u64     smm_freeze    : 1;
 185         };
 186         u64     capabilities;
 187 };
 188
 189 /*
 190  * struct x86_pmu - generic x86 pmu
 191  */
 192 struct x86_pmu {
 193         /*
 194          * Generic x86 PMC bits
 195          */
 196         const char      *name;
 197         int             version;
 198         int             (*handle_irq)(struct pt_regs *);
 199         void            (*disable_all)(void);
 200         void            (*enable_all)(int added);
 201         void            (*enable)(struct perf_event *);
 202         void            (*disable)(struct perf_event *);
 203         int             (*hw_config)(struct perf_event *event);
 204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 205         unsigned        eventsel;
 206         unsigned        perfctr;
 207         u64             (*event_map)(int);
 208         int             max_events;
 209         int             num_counters;
 210         int             num_counters_fixed;
 211         int             cntval_bits;
 212         u64             cntval_mask;
 213         int             apic;
 214         u64             max_period;
 215         struct event_constraint *
 216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218
 219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 220                                                  struct perf_event *event);
 221         struct event_constraint *event_constraints;
 222         void            (*quirks)(void);
 223         int             perfctr_second_write;
 224
 225         int             (*cpu_prepare)(int cpu);
 226         void            (*cpu_starting)(int cpu);
 227         void            (*cpu_dying)(int cpu);
 228         void            (*cpu_dead)(int cpu);
 229
 230         /*
 231          * Intel Arch Perfmon v2+
 232          */
 233         u64                     intel_ctrl;
 234         union perf_capabilities intel_cap;
 235
 236         /*
 237          * Intel DebugStore bits
 238          */
 239         int             bts, pebs;
 240         int             bts_active, pebs_active;
 241         int             pebs_record_size;
 242         void            (*drain_pebs)(struct pt_regs *regs);
 243         struct event_constraint *pebs_constraints;
 244
 245         /*
 246          * Intel LBR
 247          */
 248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 249         int             lbr_nr;                    /* hardware stack size */
 250 };
 251
 252 static struct x86_pmu x86_pmu __read_mostly;
 253
 254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 255         .enabled = 1,
 256 };
 257
 258 static int x86_perf_event_set_period(struct perf_event *event);
 259
 260 /*
 261  * Generalized hw caching related hw_event table, filled
 262  * in on a per model basis. A value of 0 means
 263  * 'not supported', -1 means 'hw_event makes no sense on
 264  * this CPU', any other value means the raw hw_event
 265  * ID.
 266  */
 267
 268 #define C(x) PERF_COUNT_HW_CACHE_##x
 269
 270 static u64 __read_mostly hw_cache_event_ids
 271                                 [PERF_COUNT_HW_CACHE_MAX]
 272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 274
 275 /*
 276  * Propagate event elapsed time into the generic event.
 277  * Can only be executed on the CPU where the event is active.
 278  * Returns the delta events processed.
 279  */
 280 static u64
 281 x86_perf_event_update(struct perf_event *event)
 282 {
 283         struct hw_perf_event *hwc = &event->hw;
 284         int shift = 64 - x86_pmu.cntval_bits;
 285         u64 prev_raw_count, new_raw_count;
 286         int idx = hwc->idx;
 287         s64 delta;
 288
 289         if (idx == X86_PMC_IDX_FIXED_BTS)
 290                 return 0;
 291
 292         /*
 293          * Careful: an NMI might modify the previous event value.
 294          *
 295          * Our tactic to handle this is to first atomically read and
 296          * exchange a new raw count - then add that new-prev delta
 297          * count to the generic event atomically:
 298          */
 299 again:
 300         prev_raw_count = local64_read(&hwc->prev_count);
 301         rdmsrl(hwc->event_base + idx, new_raw_count);
 302
 303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 304                                         new_raw_count) != prev_raw_count)
 305                 goto again;
 306
 307         /*
 308          * Now we have the new raw value and have updated the prev
 309          * timestamp already. We can now calculate the elapsed delta
 310          * (event-)time and add that to the generic event.
 311          *
 312          * Careful, not all hw sign-extends above the physical width
 313          * of the count.
 314          */
 315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 316         delta >>= shift;
 317
 318         local64_add(delta, &event->count);
 319         local64_sub(delta, &hwc->period_left);
 320
 321         return new_raw_count;
 322 }
 323
 324 static inline unsigned int x86_pmu_config_addr(int index)
 325 {
 326         return x86_pmu.eventsel + index;
 327 }
 328
 329 static inline unsigned int x86_pmu_event_addr(int index)
 330 {
 331         return x86_pmu.perfctr + index;
 332 }
 333
 334 static atomic_t active_events;
 335 static DEFINE_MUTEX(pmc_reserve_mutex);
 336
 337 #ifdef CONFIG_X86_LOCAL_APIC
 338
 339 static bool reserve_pmc_hardware(void)
 340 {
 341         int i;
 342
 343         for (i = 0; i < x86_pmu.num_counters; i++) {
 344                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 345                         goto perfctr_fail;
 346         }
 347
 348         for (i = 0; i < x86_pmu.num_counters; i++) {
 349                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 350                         goto eventsel_fail;
 351         }
 352
 353         return true;
 354
 355 eventsel_fail:
 356         for (i--; i >= 0; i--)
 357                 release_evntsel_nmi(x86_pmu_config_addr(i));
 358
 359         i = x86_pmu.num_counters;
 360
 361 perfctr_fail:
 362         for (i--; i >= 0; i--)
 363                 release_perfctr_nmi(x86_pmu_event_addr(i));
 364
 365         return false;
 366 }
 367
 368 static void release_pmc_hardware(void)
 369 {
 370         int i;
 371
 372         for (i = 0; i < x86_pmu.num_counters; i++) {
 373                 release_perfctr_nmi(x86_pmu_event_addr(i));
 374                 release_evntsel_nmi(x86_pmu_config_addr(i));
 375         }
 376 }
 377
 378 #else
 379
 380 static bool reserve_pmc_hardware(void) { return true; }
 381 static void release_pmc_hardware(void) {}
 382
 383 #endif
 384
 385 static bool check_hw_exists(void)
 386 {
 387         u64 val, val_new = 0;
 388         int i, reg, ret = 0;
 389
 390         /*
 391          * Check to see if the BIOS enabled any of the counters, if so
 392          * complain and bail.
 393          */
 394         for (i = 0; i < x86_pmu.num_counters; i++) {
 395                 reg = x86_pmu_config_addr(i);
 396                 ret = rdmsrl_safe(reg, &val);
 397                 if (ret)
 398                         goto msr_fail;
 399                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 400                         goto bios_fail;
 401         }
 402
 403         if (x86_pmu.num_counters_fixed) {
 404                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 405                 ret = rdmsrl_safe(reg, &val);
 406                 if (ret)
 407                         goto msr_fail;
 408                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 409                         if (val & (0x03 << i*4))
 410                                 goto bios_fail;
 411                 }
 412         }
 413
 414         /*
 415          * Now write a value and read it back to see if it matches,
 416          * this is needed to detect certain hardware emulators (qemu/kvm)
 417          * that don't trap on the MSR access and always return 0s.
 418          */
 419         val = 0xabcdUL;
 420         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 421         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 422         if (ret || val != val_new)
 423                 goto msr_fail;
 424
 425         return true;
 426
 427 bios_fail:
 428         printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
 429         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 430         return false;
 431
 432 msr_fail:
 433         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 434         return false;
 435 }
 436
 437 static void reserve_ds_buffers(void);
 438 static void release_ds_buffers(void);
 439
 440 static void hw_perf_event_destroy(struct perf_event *event)
 441 {
 442         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 443                 release_pmc_hardware();
 444                 release_ds_buffers();
 445                 mutex_unlock(&pmc_reserve_mutex);
 446         }
 447 }
 448
 449 static inline int x86_pmu_initialized(void)
 450 {
 451         return x86_pmu.handle_irq != NULL;
 452 }
 453
 454 static inline int
 455 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 456 {
 457         unsigned int cache_type, cache_op, cache_result;
 458         u64 config, val;
 459
 460         config = attr->config;
 461
 462         cache_type = (config >>  0) & 0xff;
 463         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 464                 return -EINVAL;
 465
 466         cache_op = (config >>  8) & 0xff;
 467         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 468                 return -EINVAL;
 469
 470         cache_result = (config >> 16) & 0xff;
 471         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 472                 return -EINVAL;
 473
 474         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 475
 476         if (val == 0)
 477                 return -ENOENT;
 478
 479         if (val == -1)
 480                 return -EINVAL;
 481
 482         hwc->config |= val;
 483
 484         return 0;
 485 }
 486
 487 static int x86_setup_perfctr(struct perf_event *event)
 488 {
 489         struct perf_event_attr *attr = &event->attr;
 490         struct hw_perf_event *hwc = &event->hw;
 491         u64 config;
 492
 493         if (!is_sampling_event(event)) {
 494                 hwc->sample_period = x86_pmu.max_period;
 495                 hwc->last_period = hwc->sample_period;
 496                 local64_set(&hwc->period_left, hwc->sample_period);
 497         } else {
 498                 /*
 499                  * If we have a PMU initialized but no APIC
 500                  * interrupts, we cannot sample hardware
 501                  * events (user-space has to fall back and
 502                  * sample via a hrtimer based software event):
 503                  */
 504                 if (!x86_pmu.apic)
 505                         return -EOPNOTSUPP;
 506         }
 507
 508         if (attr->type == PERF_TYPE_RAW)
 509                 return 0;
 510
 511         if (attr->type == PERF_TYPE_HW_CACHE)
 512                 return set_ext_hw_attr(hwc, attr);
 513
 514         if (attr->config >= x86_pmu.max_events)
 515                 return -EINVAL;
 516
 517         /*
 518          * The generic map:
 519          */
 520         config = x86_pmu.event_map(attr->config);
 521
 522         if (config == 0)
 523                 return -ENOENT;
 524
 525         if (config == -1LL)
 526                 return -EINVAL;
 527
 528         /*
 529          * Branch tracing:
 530          */
 531         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 532             (hwc->sample_period == 1)) {
 533                 /* BTS is not supported by this architecture. */
 534                 if (!x86_pmu.bts_active)
 535                         return -EOPNOTSUPP;
 536
 537                 /* BTS is currently only allowed for user-mode. */
 538                 if (!attr->exclude_kernel)
 539                         return -EOPNOTSUPP;
 540         }
 541
 542         hwc->config |= config;
 543
 544         return 0;
 545 }
 546
 547 static int x86_pmu_hw_config(struct perf_event *event)
 548 {
 549         if (event->attr.precise_ip) {
 550                 int precise = 0;
 551
 552                 /* Support for constant skid */
 553                 if (x86_pmu.pebs_active) {
 554                         precise++;
 555
 556                         /* Support for IP fixup */
 557                         if (x86_pmu.lbr_nr)
 558                                 precise++;
 559                 }
 560
 561                 if (event->attr.precise_ip > precise)
 562                         return -EOPNOTSUPP;
 563         }
 564
 565         /*
 566          * Generate PMC IRQs:
 567          * (keep 'enabled' bit clear for now)
 568          */
 569         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 570
 571         /*
 572          * Count user and OS events unless requested not to
 573          */
 574         if (!event->attr.exclude_user)
 575                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 576         if (!event->attr.exclude_kernel)
 577                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 578
 579         if (event->attr.type == PERF_TYPE_RAW)
 580                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 581
 582         return x86_setup_perfctr(event);
 583 }
 584
 585 /*
 586  * Setup the hardware configuration for a given attr_type
 587  */
 588 static int __x86_pmu_event_init(struct perf_event *event)
 589 {
 590         int err;
 591
 592         if (!x86_pmu_initialized())
 593                 return -ENODEV;
 594
 595         err = 0;
 596         if (!atomic_inc_not_zero(&active_events)) {
 597                 mutex_lock(&pmc_reserve_mutex);
 598                 if (atomic_read(&active_events) == 0) {
 599                         if (!reserve_pmc_hardware())
 600                                 err = -EBUSY;
 601                         else
 602                                 reserve_ds_buffers();
 603                 }
 604                 if (!err)
 605                         atomic_inc(&active_events);
 606                 mutex_unlock(&pmc_reserve_mutex);
 607         }
 608         if (err)
 609                 return err;
 610
 611         event->destroy = hw_perf_event_destroy;
 612
 613         event->hw.idx = -1;
 614         event->hw.last_cpu = -1;
 615         event->hw.last_tag = ~0ULL;
 616
 617         return x86_pmu.hw_config(event);
 618 }
 619
 620 static void x86_pmu_disable_all(void)
 621 {
 622         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 623         int idx;
 624
 625         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 626                 u64 val;
 627
 628                 if (!test_bit(idx, cpuc->active_mask))
 629                         continue;
 630                 rdmsrl(x86_pmu_config_addr(idx), val);
 631                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 632                         continue;
 633                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 634                 wrmsrl(x86_pmu_config_addr(idx), val);
 635         }
 636 }
 637
 638 static void x86_pmu_disable(struct pmu *pmu)
 639 {
 640         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 641
 642         if (!x86_pmu_initialized())
 643                 return;
 644
 645         if (!cpuc->enabled)
 646                 return;
 647
 648         cpuc->n_added = 0;
 649         cpuc->enabled = 0;
 650         barrier();
 651
 652         x86_pmu.disable_all();
 653 }
 654
 655 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 656                                           u64 enable_mask)
 657 {
 658         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 659 }
 660
 661 static void x86_pmu_enable_all(int added)
 662 {
 663         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 664         int idx;
 665
 666         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 667                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 668
 669                 if (!test_bit(idx, cpuc->active_mask))
 670                         continue;
 671
 672                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 673         }
 674 }
 675
 676 static struct pmu pmu;
 677
 678 static inline int is_x86_event(struct perf_event *event)
 679 {
 680         return event->pmu == &pmu;
 681 }
 682
 683 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 684 {
 685         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 686         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 687         int i, j, w, wmax, num = 0;
 688         struct hw_perf_event *hwc;
 689
 690         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 691
 692         for (i = 0; i < n; i++) {
 693                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 694                 constraints[i] = c;
 695         }
 696
 697         /*
 698          * fastpath, try to reuse previous register
 699          */
 700         for (i = 0; i < n; i++) {
 701                 hwc = &cpuc->event_list[i]->hw;
 702                 c = constraints[i];
 703
 704                 /* never assigned */
 705                 if (hwc->idx == -1)
 706                         break;
 707
 708                 /* constraint still honored */
 709                 if (!test_bit(hwc->idx, c->idxmsk))
 710                         break;
 711
 712                 /* not already used */
 713                 if (test_bit(hwc->idx, used_mask))
 714                         break;
 715
 716                 __set_bit(hwc->idx, used_mask);
 717                 if (assign)
 718                         assign[i] = hwc->idx;
 719         }
 720         if (i == n)
 721                 goto done;
 722
 723         /*
 724          * begin slow path
 725          */
 726
 727         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 728
 729         /*
 730          * weight = number of possible counters
 731          *
 732          * 1    = most constrained, only works on one counter
 733          * wmax = least constrained, works on any counter
 734          *
 735          * assign events to counters starting with most
 736          * constrained events.
 737          */
 738         wmax = x86_pmu.num_counters;
 739
 740         /*
 741          * when fixed event counters are present,
 742          * wmax is incremented by 1 to account
 743          * for one more choice
 744          */
 745         if (x86_pmu.num_counters_fixed)
 746                 wmax++;
 747
 748         for (w = 1, num = n; num && w <= wmax; w++) {
 749                 /* for each event */
 750                 for (i = 0; num && i < n; i++) {
 751                         c = constraints[i];
 752                         hwc = &cpuc->event_list[i]->hw;
 753
 754                         if (c->weight != w)
 755                                 continue;
 756
 757                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 758                                 if (!test_bit(j, used_mask))
 759                                         break;
 760                         }
 761
 762                         if (j == X86_PMC_IDX_MAX)
 763                                 break;
 764
 765                         __set_bit(j, used_mask);
 766
 767                         if (assign)
 768                                 assign[i] = j;
 769                         num--;
 770                 }
 771         }
 772 done:
 773         /*
 774          * scheduling failed or is just a simulation,
 775          * free resources if necessary
 776          */
 777         if (!assign || num) {
 778                 for (i = 0; i < n; i++) {
 779                         if (x86_pmu.put_event_constraints)
 780                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 781                 }
 782         }
 783         return num ? -ENOSPC : 0;
 784 }
 785
 786 /*
 787  * dogrp: true if must collect siblings events (group)
 788  * returns total number of events and error code
 789  */
 790 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 791 {
 792         struct perf_event *event;
 793         int n, max_count;
 794
 795         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 796
 797         /* current number of events already accepted */
 798         n = cpuc->n_events;
 799
 800         if (is_x86_event(leader)) {
 801                 if (n >= max_count)
 802                         return -ENOSPC;
 803                 cpuc->event_list[n] = leader;
 804                 n++;
 805         }
 806         if (!dogrp)
 807                 return n;
 808
 809         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 810                 if (!is_x86_event(event) ||
 811                     event->state <= PERF_EVENT_STATE_OFF)
 812                         continue;
 813
 814                 if (n >= max_count)
 815                         return -ENOSPC;
 816
 817                 cpuc->event_list[n] = event;
 818                 n++;
 819         }
 820         return n;
 821 }
 822
 823 static inline void x86_assign_hw_event(struct perf_event *event,
 824                                 struct cpu_hw_events *cpuc, int i)
 825 {
 826         struct hw_perf_event *hwc = &event->hw;
 827
 828         hwc->idx = cpuc->assign[i];
 829         hwc->last_cpu = smp_processor_id();
 830         hwc->last_tag = ++cpuc->tags[i];
 831
 832         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 833                 hwc->config_base = 0;
 834                 hwc->event_base = 0;
 835         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 836                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 837                 /*
 838                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 839                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 840                  */
 841                 hwc->event_base =
 842                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 843         } else {
 844                 hwc->config_base = x86_pmu.eventsel;
 845                 hwc->event_base  = x86_pmu.perfctr;
 846         }
 847 }
 848
 849 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 850                                         struct cpu_hw_events *cpuc,
 851                                         int i)
 852 {
 853         return hwc->idx == cpuc->assign[i] &&
 854                 hwc->last_cpu == smp_processor_id() &&
 855                 hwc->last_tag == cpuc->tags[i];
 856 }
 857
 858 static void x86_pmu_start(struct perf_event *event, int flags);
 859 static void x86_pmu_stop(struct perf_event *event, int flags);
 860
 861 static void x86_pmu_enable(struct pmu *pmu)
 862 {
 863         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 864         struct perf_event *event;
 865         struct hw_perf_event *hwc;
 866         int i, added = cpuc->n_added;
 867
 868         if (!x86_pmu_initialized())
 869                 return;
 870
 871         if (cpuc->enabled)
 872                 return;
 873
 874         if (cpuc->n_added) {
 875                 int n_running = cpuc->n_events - cpuc->n_added;
 876                 /*
 877                  * apply assignment obtained either from
 878                  * hw_perf_group_sched_in() or x86_pmu_enable()
 879                  *
 880                  * step1: save events moving to new counters
 881                  * step2: reprogram moved events into new counters
 882                  */
 883                 for (i = 0; i < n_running; i++) {
 884                         event = cpuc->event_list[i];
 885                         hwc = &event->hw;
 886
 887                         /*
 888                          * we can avoid reprogramming counter if:
 889                          * - assigned same counter as last time
 890                          * - running on same CPU as last time
 891                          * - no other event has used the counter since
 892                          */
 893                         if (hwc->idx == -1 ||
 894                             match_prev_assignment(hwc, cpuc, i))
 895                                 continue;
 896
 897                         /*
 898                          * Ensure we don't accidentally enable a stopped
 899                          * counter simply because we rescheduled.
 900                          */
 901                         if (hwc->state & PERF_HES_STOPPED)
 902                                 hwc->state |= PERF_HES_ARCH;
 903
 904                         x86_pmu_stop(event, PERF_EF_UPDATE);
 905                 }
 906
 907                 for (i = 0; i < cpuc->n_events; i++) {
 908                         event = cpuc->event_list[i];
 909                         hwc = &event->hw;
 910
 911                         if (!match_prev_assignment(hwc, cpuc, i))
 912                                 x86_assign_hw_event(event, cpuc, i);
 913                         else if (i < n_running)
 914                                 continue;
 915
 916                         if (hwc->state & PERF_HES_ARCH)
 917                                 continue;
 918
 919                         x86_pmu_start(event, PERF_EF_RELOAD);
 920                 }
 921                 cpuc->n_added = 0;
 922                 perf_events_lapic_init();
 923         }
 924
 925         cpuc->enabled = 1;
 926         barrier();
 927
 928         x86_pmu.enable_all(added);
 929 }
 930
 931 static inline void x86_pmu_disable_event(struct perf_event *event)
 932 {
 933         struct hw_perf_event *hwc = &event->hw;
 934
 935         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 936 }
 937
 938 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 939
 940 /*
 941  * Set the next IRQ period, based on the hwc->period_left value.
 942  * To be called with the event disabled in hw:
 943  */
 944 static int
 945 x86_perf_event_set_period(struct perf_event *event)
 946 {
 947         struct hw_perf_event *hwc = &event->hw;
 948         s64 left = local64_read(&hwc->period_left);
 949         s64 period = hwc->sample_period;
 950         int ret = 0, idx = hwc->idx;
 951
 952         if (idx == X86_PMC_IDX_FIXED_BTS)
 953                 return 0;
 954
 955         /*
 956          * If we are way outside a reasonable range then just skip forward:
 957          */
 958         if (unlikely(left <= -period)) {
 959                 left = period;
 960                 local64_set(&hwc->period_left, left);
 961                 hwc->last_period = period;
 962                 ret = 1;
 963         }
 964
 965         if (unlikely(left <= 0)) {
 966                 left += period;
 967                 local64_set(&hwc->period_left, left);
 968                 hwc->last_period = period;
 969                 ret = 1;
 970         }
 971         /*
 972          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 973          */
 974         if (unlikely(left < 2))
 975                 left = 2;
 976
 977         if (left > x86_pmu.max_period)
 978                 left = x86_pmu.max_period;
 979
 980         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 981
 982         /*
 983          * The hw event starts counting from this event offset,
 984          * mark it to be able to extra future deltas:
 985          */
 986         local64_set(&hwc->prev_count, (u64)-left);
 987
 988         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 989
 990         /*
 991          * Due to erratum on certan cpu we need
 992          * a second write to be sure the register
 993          * is updated properly
 994          */
 995         if (x86_pmu.perfctr_second_write) {
 996                 wrmsrl(hwc->event_base + idx,
 997                         (u64)(-left) & x86_pmu.cntval_mask);
 998         }
 999
1000         perf_event_update_userpage(event);
1001
1002         return ret;
1003 }
1004
1005 static void x86_pmu_enable_event(struct perf_event *event)
1006 {
1007         if (__this_cpu_read(cpu_hw_events.enabled))
1008                 __x86_pmu_enable_event(&event->hw,
1009                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1010 }
1011
1012 /*
1013  * Add a single event to the PMU.
1014  *
1015  * The event is added to the group of enabled events
1016  * but only if it can be scehduled with existing events.
1017  */
1018 static int x86_pmu_add(struct perf_event *event, int flags)
1019 {
1020         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1021         struct hw_perf_event *hwc;
1022         int assign[X86_PMC_IDX_MAX];
1023         int n, n0, ret;
1024
1025         hwc = &event->hw;
1026
1027         perf_pmu_disable(event->pmu);
1028         n0 = cpuc->n_events;
1029         ret = n = collect_events(cpuc, event, false);
1030         if (ret < 0)
1031                 goto out;
1032
1033         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1034         if (!(flags & PERF_EF_START))
1035                 hwc->state |= PERF_HES_ARCH;
1036
1037         /*
1038          * If group events scheduling transaction was started,
1039          * skip the schedulability test here, it will be peformed
1040          * at commit time (->commit_txn) as a whole
1041          */
1042         if (cpuc->group_flag & PERF_EVENT_TXN)
1043                 goto done_collect;
1044
1045         ret = x86_pmu.schedule_events(cpuc, n, assign);
1046         if (ret)
1047                 goto out;
1048         /*
1049          * copy new assignment, now we know it is possible
1050          * will be used by hw_perf_enable()
1051          */
1052         memcpy(cpuc->assign, assign, n*sizeof(int));
1053
1054 done_collect:
1055         cpuc->n_events = n;
1056         cpuc->n_added += n - n0;
1057         cpuc->n_txn += n - n0;
1058
1059         ret = 0;
1060 out:
1061         perf_pmu_enable(event->pmu);
1062         return ret;
1063 }
1064
1065 static void x86_pmu_start(struct perf_event *event, int flags)
1066 {
1067         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1068         int idx = event->hw.idx;
1069
1070         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1071                 return;
1072
1073         if (WARN_ON_ONCE(idx == -1))
1074                 return;
1075
1076         if (flags & PERF_EF_RELOAD) {
1077                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1078                 x86_perf_event_set_period(event);
1079         }
1080
1081         event->hw.state = 0;
1082
1083         cpuc->events[idx] = event;
1084         __set_bit(idx, cpuc->active_mask);
1085         __set_bit(idx, cpuc->running);
1086         x86_pmu.enable(event);
1087         perf_event_update_userpage(event);
1088 }
1089
1090 void perf_event_print_debug(void)
1091 {
1092         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1093         u64 pebs;
1094         struct cpu_hw_events *cpuc;
1095         unsigned long flags;
1096         int cpu, idx;
1097
1098         if (!x86_pmu.num_counters)
1099                 return;
1100
1101         local_irq_save(flags);
1102
1103         cpu = smp_processor_id();
1104         cpuc = &per_cpu(cpu_hw_events, cpu);
1105
1106         if (x86_pmu.version >= 2) {
1107                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1108                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1109                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1110                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1111                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1112
1113                 pr_info("\n");
1114                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1115                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1116                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1117                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1118                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1119         }
1120         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1121
1122         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1123                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1124                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1125
1126                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1127
1128                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1129                         cpu, idx, pmc_ctrl);
1130                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1131                         cpu, idx, pmc_count);
1132                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1133                         cpu, idx, prev_left);
1134         }
1135         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1136                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1137
1138                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1139                         cpu, idx, pmc_count);
1140         }
1141         local_irq_restore(flags);
1142 }
1143
1144 static void x86_pmu_stop(struct perf_event *event, int flags)
1145 {
1146         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1147         struct hw_perf_event *hwc = &event->hw;
1148
1149         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1150                 x86_pmu.disable(event);
1151                 cpuc->events[hwc->idx] = NULL;
1152                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1153                 hwc->state |= PERF_HES_STOPPED;
1154         }
1155
1156         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1157                 /*
1158                  * Drain the remaining delta count out of a event
1159                  * that we are disabling:
1160                  */
1161                 x86_perf_event_update(event);
1162                 hwc->state |= PERF_HES_UPTODATE;
1163         }
1164 }
1165
1166 static void x86_pmu_del(struct perf_event *event, int flags)
1167 {
1168         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1169         int i;
1170
1171         /*
1172          * If we're called during a txn, we don't need to do anything.
1173          * The events never got scheduled and ->cancel_txn will truncate
1174          * the event_list.
1175          */
1176         if (cpuc->group_flag & PERF_EVENT_TXN)
1177                 return;
1178
1179         x86_pmu_stop(event, PERF_EF_UPDATE);
1180
1181         for (i = 0; i < cpuc->n_events; i++) {
1182                 if (event == cpuc->event_list[i]) {
1183
1184                         if (x86_pmu.put_event_constraints)
1185                                 x86_pmu.put_event_constraints(cpuc, event);
1186
1187                         while (++i < cpuc->n_events)
1188                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1189
1190                         --cpuc->n_events;
1191                         break;
1192                 }
1193         }
1194         perf_event_update_userpage(event);
1195 }
1196
1197 static int x86_pmu_handle_irq(struct pt_regs *regs)
1198 {
1199         struct perf_sample_data data;
1200         struct cpu_hw_events *cpuc;
1201         struct perf_event *event;
1202         int idx, handled = 0;
1203         u64 val;
1204
1205         perf_sample_data_init(&data, 0);
1206
1207         cpuc = &__get_cpu_var(cpu_hw_events);
1208
1209         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1210                 if (!test_bit(idx, cpuc->active_mask)) {
1211                         /*
1212                          * Though we deactivated the counter some cpus
1213                          * might still deliver spurious interrupts still
1214                          * in flight. Catch them:
1215                          */
1216                         if (__test_and_clear_bit(idx, cpuc->running))
1217                                 handled++;
1218                         continue;
1219                 }
1220
1221                 event = cpuc->events[idx];
1222
1223                 val = x86_perf_event_update(event);
1224                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1225                         continue;
1226
1227                 /*
1228                  * event overflow
1229                  */
1230                 handled++;
1231                 data.period     = event->hw.last_period;
1232
1233                 if (!x86_perf_event_set_period(event))
1234                         continue;
1235
1236                 if (perf_event_overflow(event, 1, &data, regs))
1237                         x86_pmu_stop(event, 0);
1238         }
1239
1240         if (handled)
1241                 inc_irq_stat(apic_perf_irqs);
1242
1243         return handled;
1244 }
1245
1246 void perf_events_lapic_init(void)
1247 {
1248         if (!x86_pmu.apic || !x86_pmu_initialized())
1249                 return;
1250
1251         /*
1252          * Always use NMI for PMU
1253          */
1254         apic_write(APIC_LVTPC, APIC_DM_NMI);
1255 }
1256
1257 struct pmu_nmi_state {
1258         unsigned int    marked;
1259         int             handled;
1260 };
1261
1262 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1263
1264 static int __kprobes
1265 perf_event_nmi_handler(struct notifier_block *self,
1266                          unsigned long cmd, void *__args)
1267 {
1268         struct die_args *args = __args;
1269         unsigned int this_nmi;
1270         int handled;
1271
1272         if (!atomic_read(&active_events))
1273                 return NOTIFY_DONE;
1274
1275         switch (cmd) {
1276         case DIE_NMI:
1277                 break;
1278         case DIE_NMIUNKNOWN:
1279                 this_nmi = percpu_read(irq_stat.__nmi_count);
1280                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1281                         /* let the kernel handle the unknown nmi */
1282                         return NOTIFY_DONE;
1283                 /*
1284                  * This one is a PMU back-to-back nmi. Two events
1285                  * trigger 'simultaneously' raising two back-to-back
1286                  * NMIs. If the first NMI handles both, the latter
1287                  * will be empty and daze the CPU. So, we drop it to
1288                  * avoid false-positive 'unknown nmi' messages.
1289                  */
1290                 return NOTIFY_STOP;
1291         default:
1292                 return NOTIFY_DONE;
1293         }
1294
1295         apic_write(APIC_LVTPC, APIC_DM_NMI);
1296
1297         handled = x86_pmu.handle_irq(args->regs);
1298         if (!handled)
1299                 return NOTIFY_DONE;
1300
1301         this_nmi = percpu_read(irq_stat.__nmi_count);
1302         if ((handled > 1) ||
1303                 /* the next nmi could be a back-to-back nmi */
1304             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1305              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1306                 /*
1307                  * We could have two subsequent back-to-back nmis: The
1308                  * first handles more than one counter, the 2nd
1309                  * handles only one counter and the 3rd handles no
1310                  * counter.
1311                  *
1312                  * This is the 2nd nmi because the previous was
1313                  * handling more than one counter. We will mark the
1314                  * next (3rd) and then drop it if unhandled.
1315                  */
1316                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1317                 __this_cpu_write(pmu_nmi.handled, handled);
1318         }
1319
1320         return NOTIFY_STOP;
1321 }
1322
1323 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1324         .notifier_call          = perf_event_nmi_handler,
1325         .next                   = NULL,
1326         .priority               = NMI_LOCAL_LOW_PRIOR,
1327 };
1328
1329 static struct event_constraint unconstrained;
1330 static struct event_constraint emptyconstraint;
1331
1332 static struct event_constraint *
1333 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1334 {
1335         struct event_constraint *c;
1336
1337         if (x86_pmu.event_constraints) {
1338                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1339                         if ((event->hw.config & c->cmask) == c->code)
1340                                 return c;
1341                 }
1342         }
1343
1344         return &unconstrained;
1345 }
1346
1347 #include "perf_event_amd.c"
1348 #include "perf_event_p6.c"
1349 #include "perf_event_p4.c"
1350 #include "perf_event_intel_lbr.c"
1351 #include "perf_event_intel_ds.c"
1352 #include "perf_event_intel.c"
1353
1354 static int __cpuinit
1355 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1356 {
1357         unsigned int cpu = (long)hcpu;
1358         int ret = NOTIFY_OK;
1359
1360         switch (action & ~CPU_TASKS_FROZEN) {
1361         case CPU_UP_PREPARE:
1362                 if (x86_pmu.cpu_prepare)
1363                         ret = x86_pmu.cpu_prepare(cpu);
1364                 break;
1365
1366         case CPU_STARTING:
1367                 if (x86_pmu.cpu_starting)
1368                         x86_pmu.cpu_starting(cpu);
1369                 break;
1370
1371         case CPU_DYING:
1372                 if (x86_pmu.cpu_dying)
1373                         x86_pmu.cpu_dying(cpu);
1374                 break;
1375
1376         case CPU_UP_CANCELED:
1377         case CPU_DEAD:
1378                 if (x86_pmu.cpu_dead)
1379                         x86_pmu.cpu_dead(cpu);
1380                 break;
1381
1382         default:
1383                 break;
1384         }
1385
1386         return ret;
1387 }
1388
1389 static void __init pmu_check_apic(void)
1390 {
1391         if (cpu_has_apic)
1392                 return;
1393
1394         x86_pmu.apic = 0;
1395         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1396         pr_info("no hardware sampling interrupt available.\n");
1397 }
1398
1399 static int __init init_hw_perf_events(void)
1400 {
1401         struct event_constraint *c;
1402         int err;
1403
1404         pr_info("Performance Events: ");
1405
1406         switch (boot_cpu_data.x86_vendor) {
1407         case X86_VENDOR_INTEL:
1408                 err = intel_pmu_init();
1409                 break;
1410         case X86_VENDOR_AMD:
1411                 err = amd_pmu_init();
1412                 break;
1413         default:
1414                 return 0;
1415         }
1416         if (err != 0) {
1417                 pr_cont("no PMU driver, software events only.\n");
1418                 return 0;
1419         }
1420
1421         pmu_check_apic();
1422
1423         /* sanity check that the hardware exists or is emulated */
1424         if (!check_hw_exists())
1425                 return 0;
1426
1427         pr_cont("%s PMU driver.\n", x86_pmu.name);
1428
1429         if (x86_pmu.quirks)
1430                 x86_pmu.quirks();
1431
1432         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1433                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1434                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1435                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1436         }
1437         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1438
1439         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1440                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1441                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1442                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1443         }
1444
1445         x86_pmu.intel_ctrl |=
1446                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1447
1448         perf_events_lapic_init();
1449         register_die_notifier(&perf_event_nmi_notifier);
1450
1451         unconstrained = (struct event_constraint)
1452                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1453                                    0, x86_pmu.num_counters);
1454
1455         if (x86_pmu.event_constraints) {
1456                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1457                         if (c->cmask != X86_RAW_EVENT_MASK)
1458                                 continue;
1459
1460                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1461                         c->weight += x86_pmu.num_counters;
1462                 }
1463         }
1464
1465         pr_info("... version:                %d\n",     x86_pmu.version);
1466         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1467         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1468         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1469         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1470         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1471         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1472
1473         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1474         perf_cpu_notifier(x86_pmu_notifier);
1475
1476         return 0;
1477 }
1478 early_initcall(init_hw_perf_events);
1479
1480 static inline void x86_pmu_read(struct perf_event *event)
1481 {
1482         x86_perf_event_update(event);
1483 }
1484
1485 /*
1486  * Start group events scheduling transaction
1487  * Set the flag to make pmu::enable() not perform the
1488  * schedulability test, it will be performed at commit time
1489  */
1490 static void x86_pmu_start_txn(struct pmu *pmu)
1491 {
1492         perf_pmu_disable(pmu);
1493         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1494         __this_cpu_write(cpu_hw_events.n_txn, 0);
1495 }
1496
1497 /*
1498  * Stop group events scheduling transaction
1499  * Clear the flag and pmu::enable() will perform the
1500  * schedulability test.
1501  */
1502 static void x86_pmu_cancel_txn(struct pmu *pmu)
1503 {
1504         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1505         /*
1506          * Truncate the collected events.
1507          */
1508         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1509         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1510         perf_pmu_enable(pmu);
1511 }
1512
1513 /*
1514  * Commit group events scheduling transaction
1515  * Perform the group schedulability test as a whole
1516  * Return 0 if success
1517  */
1518 static int x86_pmu_commit_txn(struct pmu *pmu)
1519 {
1520         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1521         int assign[X86_PMC_IDX_MAX];
1522         int n, ret;
1523
1524         n = cpuc->n_events;
1525
1526         if (!x86_pmu_initialized())
1527                 return -EAGAIN;
1528
1529         ret = x86_pmu.schedule_events(cpuc, n, assign);
1530         if (ret)
1531                 return ret;
1532
1533         /*
1534          * copy new assignment, now we know it is possible
1535          * will be used by hw_perf_enable()
1536          */
1537         memcpy(cpuc->assign, assign, n*sizeof(int));
1538
1539         cpuc->group_flag &= ~PERF_EVENT_TXN;
1540         perf_pmu_enable(pmu);
1541         return 0;
1542 }
1543
1544 /*
1545  * validate that we can schedule this event
1546  */
1547 static int validate_event(struct perf_event *event)
1548 {
1549         struct cpu_hw_events *fake_cpuc;
1550         struct event_constraint *c;
1551         int ret = 0;
1552
1553         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1554         if (!fake_cpuc)
1555                 return -ENOMEM;
1556
1557         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1558
1559         if (!c || !c->weight)
1560                 ret = -ENOSPC;
1561
1562         if (x86_pmu.put_event_constraints)
1563                 x86_pmu.put_event_constraints(fake_cpuc, event);
1564
1565         kfree(fake_cpuc);
1566
1567         return ret;
1568 }
1569
1570 /*
1571  * validate a single event group
1572  *
1573  * validation include:
1574  *      - check events are compatible which each other
1575  *      - events do not compete for the same counter
1576  *      - number of events <= number of counters
1577  *
1578  * validation ensures the group can be loaded onto the
1579  * PMU if it was the only group available.
1580  */
1581 static int validate_group(struct perf_event *event)
1582 {
1583         struct perf_event *leader = event->group_leader;
1584         struct cpu_hw_events *fake_cpuc;
1585         int ret, n;
1586
1587         ret = -ENOMEM;
1588         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1589         if (!fake_cpuc)
1590                 goto out;
1591
1592         /*
1593          * the event is not yet connected with its
1594          * siblings therefore we must first collect
1595          * existing siblings, then add the new event
1596          * before we can simulate the scheduling
1597          */
1598         ret = -ENOSPC;
1599         n = collect_events(fake_cpuc, leader, true);
1600         if (n < 0)
1601                 goto out_free;
1602
1603         fake_cpuc->n_events = n;
1604         n = collect_events(fake_cpuc, event, false);
1605         if (n < 0)
1606                 goto out_free;
1607
1608         fake_cpuc->n_events = n;
1609
1610         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1611
1612 out_free:
1613         kfree(fake_cpuc);
1614 out:
1615         return ret;
1616 }
1617
1618 static int x86_pmu_event_init(struct perf_event *event)
1619 {
1620         struct pmu *tmp;
1621         int err;
1622
1623         switch (event->attr.type) {
1624         case PERF_TYPE_RAW:
1625         case PERF_TYPE_HARDWARE:
1626         case PERF_TYPE_HW_CACHE:
1627                 break;
1628
1629         default:
1630                 return -ENOENT;
1631         }
1632
1633         err = __x86_pmu_event_init(event);
1634         if (!err) {
1635                 /*
1636                  * we temporarily connect event to its pmu
1637                  * such that validate_group() can classify
1638                  * it as an x86 event using is_x86_event()
1639                  */
1640                 tmp = event->pmu;
1641                 event->pmu = &pmu;
1642
1643                 if (event->group_leader != event)
1644                         err = validate_group(event);
1645                 else
1646                         err = validate_event(event);
1647
1648                 event->pmu = tmp;
1649         }
1650         if (err) {
1651                 if (event->destroy)
1652                         event->destroy(event);
1653         }
1654
1655         return err;
1656 }
1657
1658 static struct pmu pmu = {
1659         .pmu_enable     = x86_pmu_enable,
1660         .pmu_disable    = x86_pmu_disable,
1661
1662         .event_init     = x86_pmu_event_init,
1663
1664         .add            = x86_pmu_add,
1665         .del            = x86_pmu_del,
1666         .start          = x86_pmu_start,
1667         .stop           = x86_pmu_stop,
1668         .read           = x86_pmu_read,
1669
1670         .start_txn      = x86_pmu_start_txn,
1671         .cancel_txn     = x86_pmu_cancel_txn,
1672         .commit_txn     = x86_pmu_commit_txn,
1673 };
1674
1675 /*
1676  * callchain support
1677  */
1678
1679 static void
1680 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1681 {
1682         /* Ignore warnings */
1683 }
1684
1685 static void backtrace_warning(void *data, char *msg)
1686 {
1687         /* Ignore warnings */
1688 }
1689
1690 static int backtrace_stack(void *data, char *name)
1691 {
1692         return 0;
1693 }
1694
1695 static void backtrace_address(void *data, unsigned long addr, int reliable)
1696 {
1697         struct perf_callchain_entry *entry = data;
1698
1699         perf_callchain_store(entry, addr);
1700 }
1701
1702 static const struct stacktrace_ops backtrace_ops = {
1703         .warning                = backtrace_warning,
1704         .warning_symbol         = backtrace_warning_symbol,
1705         .stack                  = backtrace_stack,
1706         .address                = backtrace_address,
1707         .walk_stack             = print_context_stack_bp,
1708 };
1709
1710 void
1711 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1712 {
1713         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1714                 /* TODO: We don't support guest os callchain now */
1715                 return;
1716         }
1717
1718         perf_callchain_store(entry, regs->ip);
1719
1720         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1721 }
1722
1723 #ifdef CONFIG_COMPAT
1724 static inline int
1725 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1726 {
1727         /* 32-bit process in 64-bit kernel. */
1728         struct stack_frame_ia32 frame;
1729         const void __user *fp;
1730
1731         if (!test_thread_flag(TIF_IA32))
1732                 return 0;
1733
1734         fp = compat_ptr(regs->bp);
1735         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1736                 unsigned long bytes;
1737                 frame.next_frame     = 0;
1738                 frame.return_address = 0;
1739
1740                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1741                 if (bytes != sizeof(frame))
1742                         break;
1743
1744                 if (fp < compat_ptr(regs->sp))
1745                         break;
1746
1747                 perf_callchain_store(entry, frame.return_address);
1748                 fp = compat_ptr(frame.next_frame);
1749         }
1750         return 1;
1751 }
1752 #else
1753 static inline int
1754 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1755 {
1756     return 0;
1757 }
1758 #endif
1759
1760 void
1761 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1762 {
1763         struct stack_frame frame;
1764         const void __user *fp;
1765
1766         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1767                 /* TODO: We don't support guest os callchain now */
1768                 return;
1769         }
1770
1771         fp = (void __user *)regs->bp;
1772
1773         perf_callchain_store(entry, regs->ip);
1774
1775         if (perf_callchain_user32(regs, entry))
1776                 return;
1777
1778         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1779                 unsigned long bytes;
1780                 frame.next_frame             = NULL;
1781                 frame.return_address = 0;
1782
1783                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1784                 if (bytes != sizeof(frame))
1785                         break;
1786
1787                 if ((unsigned long)fp < regs->sp)
1788                         break;
1789
1790                 perf_callchain_store(entry, frame.return_address);
1791                 fp = frame.next_frame;
1792         }
1793 }
1794
1795 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1796 {
1797         unsigned long ip;
1798
1799         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1800                 ip = perf_guest_cbs->get_guest_ip();
1801         else
1802                 ip = instruction_pointer(regs);
1803
1804         return ip;
1805 }
1806
1807 unsigned long perf_misc_flags(struct pt_regs *regs)
1808 {
1809         int misc = 0;
1810
1811         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1812                 if (perf_guest_cbs->is_user_mode())
1813                         misc |= PERF_RECORD_MISC_GUEST_USER;
1814                 else
1815                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1816         } else {
1817                 if (user_mode(regs))
1818                         misc |= PERF_RECORD_MISC_USER;
1819                 else
1820                         misc |= PERF_RECORD_MISC_KERNEL;
1821         }
1822
1823         if (regs->flags & PERF_EFLAGS_EXACT)
1824                 misc |= PERF_RECORD_MISC_EXACT_IP;
1825
1826         return misc;
1827 }