2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 unsigned long size, len = 0;
58 ret = __get_user_pages_fast(addr, 1, 0, &page);
62 offset = addr & (PAGE_SIZE - 1);
63 size = min(PAGE_SIZE - offset, n - len);
65 map = kmap_atomic(page);
66 memcpy(to, map+offset, size);
79 struct event_constraint {
81 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
90 int nb_id; /* NorthBridge id */
91 int refcnt; /* reference count */
92 struct perf_event *owners[X86_PMC_IDX_MAX];
93 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
96 #define MAX_LBR_ENTRIES 16
98 struct cpu_hw_events {
100 * Generic x86 PMC bits
102 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
103 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
104 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
110 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111 u64 tags[X86_PMC_IDX_MAX];
112 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
114 unsigned int group_flag;
117 * Intel DebugStore bits
119 struct debug_store *ds;
127 struct perf_branch_stack lbr_stack;
128 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
133 struct amd_nb *amd_nb;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define PEBS_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
178 union perf_capabilities {
182 u64 pebs_arch_reg : 1;
190 * struct x86_pmu - generic x86 pmu
194 * Generic x86 PMC bits
198 int (*handle_irq)(struct pt_regs *);
199 void (*disable_all)(void);
200 void (*enable_all)(int added);
201 void (*enable)(struct perf_event *);
202 void (*disable)(struct perf_event *);
203 int (*hw_config)(struct perf_event *event);
204 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
207 u64 (*event_map)(int);
210 int num_counters_fixed;
215 struct event_constraint *
216 (*get_event_constraints)(struct cpu_hw_events *cpuc,
217 struct perf_event *event);
219 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
220 struct perf_event *event);
221 struct event_constraint *event_constraints;
222 void (*quirks)(void);
223 int perfctr_second_write;
225 int (*cpu_prepare)(int cpu);
226 void (*cpu_starting)(int cpu);
227 void (*cpu_dying)(int cpu);
228 void (*cpu_dead)(int cpu);
231 * Intel Arch Perfmon v2+
234 union perf_capabilities intel_cap;
237 * Intel DebugStore bits
240 int bts_active, pebs_active;
241 int pebs_record_size;
242 void (*drain_pebs)(struct pt_regs *regs);
243 struct event_constraint *pebs_constraints;
248 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
249 int lbr_nr; /* hardware stack size */
252 static struct x86_pmu x86_pmu __read_mostly;
254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
258 static int x86_perf_event_set_period(struct perf_event *event);
261 * Generalized hw caching related hw_event table, filled
262 * in on a per model basis. A value of 0 means
263 * 'not supported', -1 means 'hw_event makes no sense on
264 * this CPU', any other value means the raw hw_event
268 #define C(x) PERF_COUNT_HW_CACHE_##x
270 static u64 __read_mostly hw_cache_event_ids
271 [PERF_COUNT_HW_CACHE_MAX]
272 [PERF_COUNT_HW_CACHE_OP_MAX]
273 [PERF_COUNT_HW_CACHE_RESULT_MAX];
276 * Propagate event elapsed time into the generic event.
277 * Can only be executed on the CPU where the event is active.
278 * Returns the delta events processed.
281 x86_perf_event_update(struct perf_event *event)
283 struct hw_perf_event *hwc = &event->hw;
284 int shift = 64 - x86_pmu.cntval_bits;
285 u64 prev_raw_count, new_raw_count;
289 if (idx == X86_PMC_IDX_FIXED_BTS)
293 * Careful: an NMI might modify the previous event value.
295 * Our tactic to handle this is to first atomically read and
296 * exchange a new raw count - then add that new-prev delta
297 * count to the generic event atomically:
300 prev_raw_count = local64_read(&hwc->prev_count);
301 rdmsrl(hwc->event_base + idx, new_raw_count);
303 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
304 new_raw_count) != prev_raw_count)
308 * Now we have the new raw value and have updated the prev
309 * timestamp already. We can now calculate the elapsed delta
310 * (event-)time and add that to the generic event.
312 * Careful, not all hw sign-extends above the physical width
315 delta = (new_raw_count << shift) - (prev_raw_count << shift);
318 local64_add(delta, &event->count);
319 local64_sub(delta, &hwc->period_left);
321 return new_raw_count;
324 static atomic_t active_events;
325 static DEFINE_MUTEX(pmc_reserve_mutex);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 static bool reserve_pmc_hardware(void)
333 for (i = 0; i < x86_pmu.num_counters; i++) {
334 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
338 for (i = 0; i < x86_pmu.num_counters; i++) {
339 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
346 for (i--; i >= 0; i--)
347 release_evntsel_nmi(x86_pmu.eventsel + i);
349 i = x86_pmu.num_counters;
352 for (i--; i >= 0; i--)
353 release_perfctr_nmi(x86_pmu.perfctr + i);
358 static void release_pmc_hardware(void)
362 for (i = 0; i < x86_pmu.num_counters; i++) {
363 release_perfctr_nmi(x86_pmu.perfctr + i);
364 release_evntsel_nmi(x86_pmu.eventsel + i);
370 static bool reserve_pmc_hardware(void) { return true; }
371 static void release_pmc_hardware(void) {}
375 static bool check_hw_exists(void)
377 u64 val, val_new = 0;
381 ret |= checking_wrmsrl(x86_pmu.perfctr, val);
382 ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new);
383 if (ret || val != val_new)
389 static void reserve_ds_buffers(void);
390 static void release_ds_buffers(void);
392 static void hw_perf_event_destroy(struct perf_event *event)
394 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
395 release_pmc_hardware();
396 release_ds_buffers();
397 mutex_unlock(&pmc_reserve_mutex);
401 static inline int x86_pmu_initialized(void)
403 return x86_pmu.handle_irq != NULL;
407 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
409 unsigned int cache_type, cache_op, cache_result;
412 config = attr->config;
414 cache_type = (config >> 0) & 0xff;
415 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
418 cache_op = (config >> 8) & 0xff;
419 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
422 cache_result = (config >> 16) & 0xff;
423 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
426 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
439 static int x86_setup_perfctr(struct perf_event *event)
441 struct perf_event_attr *attr = &event->attr;
442 struct hw_perf_event *hwc = &event->hw;
445 if (!is_sampling_event(event)) {
446 hwc->sample_period = x86_pmu.max_period;
447 hwc->last_period = hwc->sample_period;
448 local64_set(&hwc->period_left, hwc->sample_period);
451 * If we have a PMU initialized but no APIC
452 * interrupts, we cannot sample hardware
453 * events (user-space has to fall back and
454 * sample via a hrtimer based software event):
460 if (attr->type == PERF_TYPE_RAW)
463 if (attr->type == PERF_TYPE_HW_CACHE)
464 return set_ext_hw_attr(hwc, attr);
466 if (attr->config >= x86_pmu.max_events)
472 config = x86_pmu.event_map(attr->config);
483 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
484 (hwc->sample_period == 1)) {
485 /* BTS is not supported by this architecture. */
486 if (!x86_pmu.bts_active)
489 /* BTS is currently only allowed for user-mode. */
490 if (!attr->exclude_kernel)
494 hwc->config |= config;
499 static int x86_pmu_hw_config(struct perf_event *event)
501 if (event->attr.precise_ip) {
504 /* Support for constant skid */
505 if (x86_pmu.pebs_active) {
508 /* Support for IP fixup */
513 if (event->attr.precise_ip > precise)
519 * (keep 'enabled' bit clear for now)
521 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
524 * Count user and OS events unless requested not to
526 if (!event->attr.exclude_user)
527 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
528 if (!event->attr.exclude_kernel)
529 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
531 if (event->attr.type == PERF_TYPE_RAW)
532 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
534 return x86_setup_perfctr(event);
538 * Setup the hardware configuration for a given attr_type
540 static int __x86_pmu_event_init(struct perf_event *event)
544 if (!x86_pmu_initialized())
548 if (!atomic_inc_not_zero(&active_events)) {
549 mutex_lock(&pmc_reserve_mutex);
550 if (atomic_read(&active_events) == 0) {
551 if (!reserve_pmc_hardware())
554 reserve_ds_buffers();
557 atomic_inc(&active_events);
558 mutex_unlock(&pmc_reserve_mutex);
563 event->destroy = hw_perf_event_destroy;
566 event->hw.last_cpu = -1;
567 event->hw.last_tag = ~0ULL;
569 return x86_pmu.hw_config(event);
572 static void x86_pmu_disable_all(void)
574 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
577 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
580 if (!test_bit(idx, cpuc->active_mask))
582 rdmsrl(x86_pmu.eventsel + idx, val);
583 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
585 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
586 wrmsrl(x86_pmu.eventsel + idx, val);
590 static void x86_pmu_disable(struct pmu *pmu)
592 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
594 if (!x86_pmu_initialized())
604 x86_pmu.disable_all();
607 static void x86_pmu_enable_all(int added)
609 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
612 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
613 struct perf_event *event = cpuc->events[idx];
616 if (!test_bit(idx, cpuc->active_mask))
619 val = event->hw.config;
620 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
621 wrmsrl(x86_pmu.eventsel + idx, val);
625 static struct pmu pmu;
627 static inline int is_x86_event(struct perf_event *event)
629 return event->pmu == &pmu;
632 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
634 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
635 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
636 int i, j, w, wmax, num = 0;
637 struct hw_perf_event *hwc;
639 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
641 for (i = 0; i < n; i++) {
642 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
647 * fastpath, try to reuse previous register
649 for (i = 0; i < n; i++) {
650 hwc = &cpuc->event_list[i]->hw;
657 /* constraint still honored */
658 if (!test_bit(hwc->idx, c->idxmsk))
661 /* not already used */
662 if (test_bit(hwc->idx, used_mask))
665 __set_bit(hwc->idx, used_mask);
667 assign[i] = hwc->idx;
676 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
679 * weight = number of possible counters
681 * 1 = most constrained, only works on one counter
682 * wmax = least constrained, works on any counter
684 * assign events to counters starting with most
685 * constrained events.
687 wmax = x86_pmu.num_counters;
690 * when fixed event counters are present,
691 * wmax is incremented by 1 to account
692 * for one more choice
694 if (x86_pmu.num_counters_fixed)
697 for (w = 1, num = n; num && w <= wmax; w++) {
699 for (i = 0; num && i < n; i++) {
701 hwc = &cpuc->event_list[i]->hw;
706 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
707 if (!test_bit(j, used_mask))
711 if (j == X86_PMC_IDX_MAX)
714 __set_bit(j, used_mask);
723 * scheduling failed or is just a simulation,
724 * free resources if necessary
726 if (!assign || num) {
727 for (i = 0; i < n; i++) {
728 if (x86_pmu.put_event_constraints)
729 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
732 return num ? -ENOSPC : 0;
736 * dogrp: true if must collect siblings events (group)
737 * returns total number of events and error code
739 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
741 struct perf_event *event;
744 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
746 /* current number of events already accepted */
749 if (is_x86_event(leader)) {
752 cpuc->event_list[n] = leader;
758 list_for_each_entry(event, &leader->sibling_list, group_entry) {
759 if (!is_x86_event(event) ||
760 event->state <= PERF_EVENT_STATE_OFF)
766 cpuc->event_list[n] = event;
772 static inline void x86_assign_hw_event(struct perf_event *event,
773 struct cpu_hw_events *cpuc, int i)
775 struct hw_perf_event *hwc = &event->hw;
777 hwc->idx = cpuc->assign[i];
778 hwc->last_cpu = smp_processor_id();
779 hwc->last_tag = ++cpuc->tags[i];
781 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
782 hwc->config_base = 0;
784 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
785 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
787 * We set it so that event_base + idx in wrmsr/rdmsr maps to
788 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
791 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
793 hwc->config_base = x86_pmu.eventsel;
794 hwc->event_base = x86_pmu.perfctr;
798 static inline int match_prev_assignment(struct hw_perf_event *hwc,
799 struct cpu_hw_events *cpuc,
802 return hwc->idx == cpuc->assign[i] &&
803 hwc->last_cpu == smp_processor_id() &&
804 hwc->last_tag == cpuc->tags[i];
807 static void x86_pmu_start(struct perf_event *event, int flags);
808 static void x86_pmu_stop(struct perf_event *event, int flags);
810 static void x86_pmu_enable(struct pmu *pmu)
812 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
813 struct perf_event *event;
814 struct hw_perf_event *hwc;
815 int i, added = cpuc->n_added;
817 if (!x86_pmu_initialized())
824 int n_running = cpuc->n_events - cpuc->n_added;
826 * apply assignment obtained either from
827 * hw_perf_group_sched_in() or x86_pmu_enable()
829 * step1: save events moving to new counters
830 * step2: reprogram moved events into new counters
832 for (i = 0; i < n_running; i++) {
833 event = cpuc->event_list[i];
837 * we can avoid reprogramming counter if:
838 * - assigned same counter as last time
839 * - running on same CPU as last time
840 * - no other event has used the counter since
842 if (hwc->idx == -1 ||
843 match_prev_assignment(hwc, cpuc, i))
847 * Ensure we don't accidentally enable a stopped
848 * counter simply because we rescheduled.
850 if (hwc->state & PERF_HES_STOPPED)
851 hwc->state |= PERF_HES_ARCH;
853 x86_pmu_stop(event, PERF_EF_UPDATE);
856 for (i = 0; i < cpuc->n_events; i++) {
857 event = cpuc->event_list[i];
860 if (!match_prev_assignment(hwc, cpuc, i))
861 x86_assign_hw_event(event, cpuc, i);
862 else if (i < n_running)
865 if (hwc->state & PERF_HES_ARCH)
868 x86_pmu_start(event, PERF_EF_RELOAD);
871 perf_events_lapic_init();
877 x86_pmu.enable_all(added);
880 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
883 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
886 static inline void x86_pmu_disable_event(struct perf_event *event)
888 struct hw_perf_event *hwc = &event->hw;
890 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
893 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
896 * Set the next IRQ period, based on the hwc->period_left value.
897 * To be called with the event disabled in hw:
900 x86_perf_event_set_period(struct perf_event *event)
902 struct hw_perf_event *hwc = &event->hw;
903 s64 left = local64_read(&hwc->period_left);
904 s64 period = hwc->sample_period;
905 int ret = 0, idx = hwc->idx;
907 if (idx == X86_PMC_IDX_FIXED_BTS)
911 * If we are way outside a reasonable range then just skip forward:
913 if (unlikely(left <= -period)) {
915 local64_set(&hwc->period_left, left);
916 hwc->last_period = period;
920 if (unlikely(left <= 0)) {
922 local64_set(&hwc->period_left, left);
923 hwc->last_period = period;
927 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
929 if (unlikely(left < 2))
932 if (left > x86_pmu.max_period)
933 left = x86_pmu.max_period;
935 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
938 * The hw event starts counting from this event offset,
939 * mark it to be able to extra future deltas:
941 local64_set(&hwc->prev_count, (u64)-left);
943 wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
946 * Due to erratum on certan cpu we need
947 * a second write to be sure the register
948 * is updated properly
950 if (x86_pmu.perfctr_second_write) {
951 wrmsrl(hwc->event_base + idx,
952 (u64)(-left) & x86_pmu.cntval_mask);
955 perf_event_update_userpage(event);
960 static void x86_pmu_enable_event(struct perf_event *event)
962 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
964 __x86_pmu_enable_event(&event->hw,
965 ARCH_PERFMON_EVENTSEL_ENABLE);
969 * Add a single event to the PMU.
971 * The event is added to the group of enabled events
972 * but only if it can be scehduled with existing events.
974 static int x86_pmu_add(struct perf_event *event, int flags)
976 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
977 struct hw_perf_event *hwc;
978 int assign[X86_PMC_IDX_MAX];
983 perf_pmu_disable(event->pmu);
985 ret = n = collect_events(cpuc, event, false);
989 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
990 if (!(flags & PERF_EF_START))
991 hwc->state |= PERF_HES_ARCH;
994 * If group events scheduling transaction was started,
995 * skip the schedulability test here, it will be peformed
996 * at commit time (->commit_txn) as a whole
998 if (cpuc->group_flag & PERF_EVENT_TXN)
1001 ret = x86_pmu.schedule_events(cpuc, n, assign);
1005 * copy new assignment, now we know it is possible
1006 * will be used by hw_perf_enable()
1008 memcpy(cpuc->assign, assign, n*sizeof(int));
1012 cpuc->n_added += n - n0;
1013 cpuc->n_txn += n - n0;
1017 perf_pmu_enable(event->pmu);
1021 static void x86_pmu_start(struct perf_event *event, int flags)
1023 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1024 int idx = event->hw.idx;
1026 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1029 if (WARN_ON_ONCE(idx == -1))
1032 if (flags & PERF_EF_RELOAD) {
1033 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1034 x86_perf_event_set_period(event);
1037 event->hw.state = 0;
1039 cpuc->events[idx] = event;
1040 __set_bit(idx, cpuc->active_mask);
1041 __set_bit(idx, cpuc->running);
1042 x86_pmu.enable(event);
1043 perf_event_update_userpage(event);
1046 void perf_event_print_debug(void)
1048 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1050 struct cpu_hw_events *cpuc;
1051 unsigned long flags;
1054 if (!x86_pmu.num_counters)
1057 local_irq_save(flags);
1059 cpu = smp_processor_id();
1060 cpuc = &per_cpu(cpu_hw_events, cpu);
1062 if (x86_pmu.version >= 2) {
1063 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1064 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1065 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1066 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1067 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1070 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1071 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1072 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1073 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1074 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1076 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1078 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1079 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1080 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1082 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1084 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1085 cpu, idx, pmc_ctrl);
1086 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1087 cpu, idx, pmc_count);
1088 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1089 cpu, idx, prev_left);
1091 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1092 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1094 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1095 cpu, idx, pmc_count);
1097 local_irq_restore(flags);
1100 static void x86_pmu_stop(struct perf_event *event, int flags)
1102 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1103 struct hw_perf_event *hwc = &event->hw;
1105 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1106 x86_pmu.disable(event);
1107 cpuc->events[hwc->idx] = NULL;
1108 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1109 hwc->state |= PERF_HES_STOPPED;
1112 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1114 * Drain the remaining delta count out of a event
1115 * that we are disabling:
1117 x86_perf_event_update(event);
1118 hwc->state |= PERF_HES_UPTODATE;
1122 static void x86_pmu_del(struct perf_event *event, int flags)
1124 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1128 * If we're called during a txn, we don't need to do anything.
1129 * The events never got scheduled and ->cancel_txn will truncate
1132 if (cpuc->group_flag & PERF_EVENT_TXN)
1135 x86_pmu_stop(event, PERF_EF_UPDATE);
1137 for (i = 0; i < cpuc->n_events; i++) {
1138 if (event == cpuc->event_list[i]) {
1140 if (x86_pmu.put_event_constraints)
1141 x86_pmu.put_event_constraints(cpuc, event);
1143 while (++i < cpuc->n_events)
1144 cpuc->event_list[i-1] = cpuc->event_list[i];
1150 perf_event_update_userpage(event);
1153 static int x86_pmu_handle_irq(struct pt_regs *regs)
1155 struct perf_sample_data data;
1156 struct cpu_hw_events *cpuc;
1157 struct perf_event *event;
1158 int idx, handled = 0;
1161 perf_sample_data_init(&data, 0);
1163 cpuc = &__get_cpu_var(cpu_hw_events);
1165 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1166 if (!test_bit(idx, cpuc->active_mask)) {
1168 * Though we deactivated the counter some cpus
1169 * might still deliver spurious interrupts still
1170 * in flight. Catch them:
1172 if (__test_and_clear_bit(idx, cpuc->running))
1177 event = cpuc->events[idx];
1179 val = x86_perf_event_update(event);
1180 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1187 data.period = event->hw.last_period;
1189 if (!x86_perf_event_set_period(event))
1192 if (perf_event_overflow(event, 1, &data, regs))
1193 x86_pmu_stop(event, 0);
1197 inc_irq_stat(apic_perf_irqs);
1202 void perf_events_lapic_init(void)
1204 if (!x86_pmu.apic || !x86_pmu_initialized())
1208 * Always use NMI for PMU
1210 apic_write(APIC_LVTPC, APIC_DM_NMI);
1213 struct pmu_nmi_state {
1214 unsigned int marked;
1218 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1220 static int __kprobes
1221 perf_event_nmi_handler(struct notifier_block *self,
1222 unsigned long cmd, void *__args)
1224 struct die_args *args = __args;
1225 unsigned int this_nmi;
1228 if (!atomic_read(&active_events))
1235 case DIE_NMIUNKNOWN:
1236 this_nmi = percpu_read(irq_stat.__nmi_count);
1237 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1238 /* let the kernel handle the unknown nmi */
1241 * This one is a PMU back-to-back nmi. Two events
1242 * trigger 'simultaneously' raising two back-to-back
1243 * NMIs. If the first NMI handles both, the latter
1244 * will be empty and daze the CPU. So, we drop it to
1245 * avoid false-positive 'unknown nmi' messages.
1252 apic_write(APIC_LVTPC, APIC_DM_NMI);
1254 handled = x86_pmu.handle_irq(args->regs);
1258 this_nmi = percpu_read(irq_stat.__nmi_count);
1259 if ((handled > 1) ||
1260 /* the next nmi could be a back-to-back nmi */
1261 ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1262 (__get_cpu_var(pmu_nmi).handled > 1))) {
1264 * We could have two subsequent back-to-back nmis: The
1265 * first handles more than one counter, the 2nd
1266 * handles only one counter and the 3rd handles no
1269 * This is the 2nd nmi because the previous was
1270 * handling more than one counter. We will mark the
1271 * next (3rd) and then drop it if unhandled.
1273 __get_cpu_var(pmu_nmi).marked = this_nmi + 1;
1274 __get_cpu_var(pmu_nmi).handled = handled;
1280 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1281 .notifier_call = perf_event_nmi_handler,
1286 static struct event_constraint unconstrained;
1287 static struct event_constraint emptyconstraint;
1289 static struct event_constraint *
1290 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1292 struct event_constraint *c;
1294 if (x86_pmu.event_constraints) {
1295 for_each_event_constraint(c, x86_pmu.event_constraints) {
1296 if ((event->hw.config & c->cmask) == c->code)
1301 return &unconstrained;
1304 #include "perf_event_amd.c"
1305 #include "perf_event_p6.c"
1306 #include "perf_event_p4.c"
1307 #include "perf_event_intel_lbr.c"
1308 #include "perf_event_intel_ds.c"
1309 #include "perf_event_intel.c"
1311 static int __cpuinit
1312 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1314 unsigned int cpu = (long)hcpu;
1315 int ret = NOTIFY_OK;
1317 switch (action & ~CPU_TASKS_FROZEN) {
1318 case CPU_UP_PREPARE:
1319 if (x86_pmu.cpu_prepare)
1320 ret = x86_pmu.cpu_prepare(cpu);
1324 if (x86_pmu.cpu_starting)
1325 x86_pmu.cpu_starting(cpu);
1329 if (x86_pmu.cpu_dying)
1330 x86_pmu.cpu_dying(cpu);
1333 case CPU_UP_CANCELED:
1335 if (x86_pmu.cpu_dead)
1336 x86_pmu.cpu_dead(cpu);
1346 static void __init pmu_check_apic(void)
1352 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1353 pr_info("no hardware sampling interrupt available.\n");
1356 void __init init_hw_perf_events(void)
1358 struct event_constraint *c;
1361 pr_info("Performance Events: ");
1363 switch (boot_cpu_data.x86_vendor) {
1364 case X86_VENDOR_INTEL:
1365 err = intel_pmu_init();
1367 case X86_VENDOR_AMD:
1368 err = amd_pmu_init();
1374 pr_cont("no PMU driver, software events only.\n");
1380 /* sanity check that the hardware exists or is emulated */
1381 if (!check_hw_exists()) {
1382 pr_cont("Broken PMU hardware detected, software events only.\n");
1386 pr_cont("%s PMU driver.\n", x86_pmu.name);
1391 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1392 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1393 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1394 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1396 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1398 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1399 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1400 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1401 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1404 x86_pmu.intel_ctrl |=
1405 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1407 perf_events_lapic_init();
1408 register_die_notifier(&perf_event_nmi_notifier);
1410 unconstrained = (struct event_constraint)
1411 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1412 0, x86_pmu.num_counters);
1414 if (x86_pmu.event_constraints) {
1415 for_each_event_constraint(c, x86_pmu.event_constraints) {
1416 if (c->cmask != X86_RAW_EVENT_MASK)
1419 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1420 c->weight += x86_pmu.num_counters;
1424 pr_info("... version: %d\n", x86_pmu.version);
1425 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1426 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1427 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1428 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1429 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1430 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1432 perf_pmu_register(&pmu);
1433 perf_cpu_notifier(x86_pmu_notifier);
1436 static inline void x86_pmu_read(struct perf_event *event)
1438 x86_perf_event_update(event);
1442 * Start group events scheduling transaction
1443 * Set the flag to make pmu::enable() not perform the
1444 * schedulability test, it will be performed at commit time
1446 static void x86_pmu_start_txn(struct pmu *pmu)
1448 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1450 perf_pmu_disable(pmu);
1451 cpuc->group_flag |= PERF_EVENT_TXN;
1456 * Stop group events scheduling transaction
1457 * Clear the flag and pmu::enable() will perform the
1458 * schedulability test.
1460 static void x86_pmu_cancel_txn(struct pmu *pmu)
1462 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1464 cpuc->group_flag &= ~PERF_EVENT_TXN;
1466 * Truncate the collected events.
1468 cpuc->n_added -= cpuc->n_txn;
1469 cpuc->n_events -= cpuc->n_txn;
1470 perf_pmu_enable(pmu);
1474 * Commit group events scheduling transaction
1475 * Perform the group schedulability test as a whole
1476 * Return 0 if success
1478 static int x86_pmu_commit_txn(struct pmu *pmu)
1480 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1481 int assign[X86_PMC_IDX_MAX];
1486 if (!x86_pmu_initialized())
1489 ret = x86_pmu.schedule_events(cpuc, n, assign);
1494 * copy new assignment, now we know it is possible
1495 * will be used by hw_perf_enable()
1497 memcpy(cpuc->assign, assign, n*sizeof(int));
1499 cpuc->group_flag &= ~PERF_EVENT_TXN;
1500 perf_pmu_enable(pmu);
1505 * validate that we can schedule this event
1507 static int validate_event(struct perf_event *event)
1509 struct cpu_hw_events *fake_cpuc;
1510 struct event_constraint *c;
1513 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1517 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1519 if (!c || !c->weight)
1522 if (x86_pmu.put_event_constraints)
1523 x86_pmu.put_event_constraints(fake_cpuc, event);
1531 * validate a single event group
1533 * validation include:
1534 * - check events are compatible which each other
1535 * - events do not compete for the same counter
1536 * - number of events <= number of counters
1538 * validation ensures the group can be loaded onto the
1539 * PMU if it was the only group available.
1541 static int validate_group(struct perf_event *event)
1543 struct perf_event *leader = event->group_leader;
1544 struct cpu_hw_events *fake_cpuc;
1548 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1553 * the event is not yet connected with its
1554 * siblings therefore we must first collect
1555 * existing siblings, then add the new event
1556 * before we can simulate the scheduling
1559 n = collect_events(fake_cpuc, leader, true);
1563 fake_cpuc->n_events = n;
1564 n = collect_events(fake_cpuc, event, false);
1568 fake_cpuc->n_events = n;
1570 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1578 int x86_pmu_event_init(struct perf_event *event)
1583 switch (event->attr.type) {
1585 case PERF_TYPE_HARDWARE:
1586 case PERF_TYPE_HW_CACHE:
1593 err = __x86_pmu_event_init(event);
1596 * we temporarily connect event to its pmu
1597 * such that validate_group() can classify
1598 * it as an x86 event using is_x86_event()
1603 if (event->group_leader != event)
1604 err = validate_group(event);
1606 err = validate_event(event);
1612 event->destroy(event);
1618 static struct pmu pmu = {
1619 .pmu_enable = x86_pmu_enable,
1620 .pmu_disable = x86_pmu_disable,
1622 .event_init = x86_pmu_event_init,
1626 .start = x86_pmu_start,
1627 .stop = x86_pmu_stop,
1628 .read = x86_pmu_read,
1630 .start_txn = x86_pmu_start_txn,
1631 .cancel_txn = x86_pmu_cancel_txn,
1632 .commit_txn = x86_pmu_commit_txn,
1640 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1642 /* Ignore warnings */
1645 static void backtrace_warning(void *data, char *msg)
1647 /* Ignore warnings */
1650 static int backtrace_stack(void *data, char *name)
1655 static void backtrace_address(void *data, unsigned long addr, int reliable)
1657 struct perf_callchain_entry *entry = data;
1659 perf_callchain_store(entry, addr);
1662 static const struct stacktrace_ops backtrace_ops = {
1663 .warning = backtrace_warning,
1664 .warning_symbol = backtrace_warning_symbol,
1665 .stack = backtrace_stack,
1666 .address = backtrace_address,
1667 .walk_stack = print_context_stack_bp,
1671 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1673 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1674 /* TODO: We don't support guest os callchain now */
1678 perf_callchain_store(entry, regs->ip);
1680 dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1683 #ifdef CONFIG_COMPAT
1685 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1687 /* 32-bit process in 64-bit kernel. */
1688 struct stack_frame_ia32 frame;
1689 const void __user *fp;
1691 if (!test_thread_flag(TIF_IA32))
1694 fp = compat_ptr(regs->bp);
1695 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1696 unsigned long bytes;
1697 frame.next_frame = 0;
1698 frame.return_address = 0;
1700 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1701 if (bytes != sizeof(frame))
1704 if (fp < compat_ptr(regs->sp))
1707 perf_callchain_store(entry, frame.return_address);
1708 fp = compat_ptr(frame.next_frame);
1714 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1721 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1723 struct stack_frame frame;
1724 const void __user *fp;
1726 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1727 /* TODO: We don't support guest os callchain now */
1731 fp = (void __user *)regs->bp;
1733 perf_callchain_store(entry, regs->ip);
1735 if (perf_callchain_user32(regs, entry))
1738 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1739 unsigned long bytes;
1740 frame.next_frame = NULL;
1741 frame.return_address = 0;
1743 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1744 if (bytes != sizeof(frame))
1747 if ((unsigned long)fp < regs->sp)
1750 perf_callchain_store(entry, frame.return_address);
1751 fp = frame.next_frame;
1755 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1759 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1760 ip = perf_guest_cbs->get_guest_ip();
1762 ip = instruction_pointer(regs);
1767 unsigned long perf_misc_flags(struct pt_regs *regs)
1771 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1772 if (perf_guest_cbs->is_user_mode())
1773 misc |= PERF_RECORD_MISC_GUEST_USER;
1775 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1777 if (user_mode(regs))
1778 misc |= PERF_RECORD_MISC_USER;
1780 misc |= PERF_RECORD_MISC_KERNEL;
1783 if (regs->flags & PERF_EFLAGS_EXACT)
1784 misc |= PERF_RECORD_MISC_EXACT_IP;