2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
28 #include <asm/stacktrace.h>
31 static u64 perf_event_mask __read_mostly;
33 /* The maximal number of PEBS events: */
34 #define MAX_PEBS_EVENTS 4
36 /* The size of a BTS record in bytes: */
37 #define BTS_RECORD_SIZE 24
39 /* The size of a per-cpu BTS buffer in bytes: */
40 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
42 /* The BTS overflow threshold in bytes from the end of the buffer: */
43 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
47 * Bits in the debugctlmsr controlling branch tracing.
49 #define X86_DEBUGCTL_TR (1 << 6)
50 #define X86_DEBUGCTL_BTS (1 << 7)
51 #define X86_DEBUGCTL_BTINT (1 << 8)
52 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
53 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
56 * A debug store configuration.
58 * We only support architectures that use 64bit fields.
63 u64 bts_absolute_maximum;
64 u64 bts_interrupt_threshold;
67 u64 pebs_absolute_maximum;
68 u64 pebs_interrupt_threshold;
69 u64 pebs_event_reset[MAX_PEBS_EVENTS];
72 struct event_constraint {
74 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
81 struct cpu_hw_events {
82 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
83 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
84 unsigned long interrupts;
86 struct debug_store *ds;
90 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
91 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
94 #define EVENT_CONSTRAINT(c, n, m) { \
95 { .idxmsk64[0] = (n) }, \
100 #define EVENT_CONSTRAINT_END \
101 EVENT_CONSTRAINT(0, 0, 0)
103 #define for_each_event_constraint(e, c) \
104 for ((e) = (c); (e)->cmask; (e)++)
107 * struct x86_pmu - generic x86 pmu
112 int (*handle_irq)(struct pt_regs *);
113 void (*disable_all)(void);
114 void (*enable_all)(void);
115 void (*enable)(struct hw_perf_event *, int);
116 void (*disable)(struct hw_perf_event *, int);
119 u64 (*event_map)(int);
120 u64 (*raw_event)(u64);
123 int num_events_fixed;
129 void (*enable_bts)(u64 config);
130 void (*disable_bts)(void);
131 void (*get_event_constraints)(struct cpu_hw_events *cpuc,
132 struct perf_event *event,
133 unsigned long *idxmsk);
134 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
135 struct perf_event *event);
136 const struct event_constraint *event_constraints;
139 static struct x86_pmu x86_pmu __read_mostly;
141 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
145 static int x86_perf_event_set_period(struct perf_event *event,
146 struct hw_perf_event *hwc, int idx);
149 * Not sure about some of these
151 static const u64 p6_perfmon_event_map[] =
153 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
154 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
155 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
156 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
157 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
158 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
159 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
162 static u64 p6_pmu_event_map(int hw_event)
164 return p6_perfmon_event_map[hw_event];
168 * Event setting that is specified not to count anything.
169 * We use this to effectively disable a counter.
171 * L2_RQSTS with 0 MESI unit mask.
173 #define P6_NOP_EVENT 0x0000002EULL
175 static u64 p6_pmu_raw_event(u64 hw_event)
177 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
178 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
179 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
180 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
181 #define P6_EVNTSEL_REG_MASK 0xFF000000ULL
183 #define P6_EVNTSEL_MASK \
184 (P6_EVNTSEL_EVENT_MASK | \
185 P6_EVNTSEL_UNIT_MASK | \
186 P6_EVNTSEL_EDGE_MASK | \
187 P6_EVNTSEL_INV_MASK | \
190 return hw_event & P6_EVNTSEL_MASK;
193 static struct event_constraint intel_p6_event_constraints[] =
195 EVENT_CONSTRAINT(0xc1, 0x1, INTEL_ARCH_EVENT_MASK), /* FLOPS */
196 EVENT_CONSTRAINT(0x10, 0x1, INTEL_ARCH_EVENT_MASK), /* FP_COMP_OPS_EXE */
197 EVENT_CONSTRAINT(0x11, 0x1, INTEL_ARCH_EVENT_MASK), /* FP_ASSIST */
198 EVENT_CONSTRAINT(0x12, 0x2, INTEL_ARCH_EVENT_MASK), /* MUL */
199 EVENT_CONSTRAINT(0x13, 0x2, INTEL_ARCH_EVENT_MASK), /* DIV */
200 EVENT_CONSTRAINT(0x14, 0x1, INTEL_ARCH_EVENT_MASK), /* CYCLES_DIV_BUSY */
205 * Intel PerfMon v3. Used on Core2 and later.
207 static const u64 intel_perfmon_event_map[] =
209 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
210 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
211 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
212 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
213 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
214 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
215 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
218 static struct event_constraint intel_core_event_constraints[] =
220 EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32)), INTEL_ARCH_FIXED_MASK), /* INSTRUCTIONS_RETIRED */
221 EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33)), INTEL_ARCH_FIXED_MASK), /* UNHALTED_CORE_CYCLES */
222 EVENT_CONSTRAINT(0x10, 0x1, INTEL_ARCH_EVENT_MASK), /* FP_COMP_OPS_EXE */
223 EVENT_CONSTRAINT(0x11, 0x2, INTEL_ARCH_EVENT_MASK), /* FP_ASSIST */
224 EVENT_CONSTRAINT(0x12, 0x2, INTEL_ARCH_EVENT_MASK), /* MUL */
225 EVENT_CONSTRAINT(0x13, 0x2, INTEL_ARCH_EVENT_MASK), /* DIV */
226 EVENT_CONSTRAINT(0x14, 0x1, INTEL_ARCH_EVENT_MASK), /* CYCLES_DIV_BUSY */
227 EVENT_CONSTRAINT(0x18, 0x1, INTEL_ARCH_EVENT_MASK), /* IDLE_DURING_DIV */
228 EVENT_CONSTRAINT(0x19, 0x2, INTEL_ARCH_EVENT_MASK), /* DELAYED_BYPASS */
229 EVENT_CONSTRAINT(0xa1, 0x1, INTEL_ARCH_EVENT_MASK), /* RS_UOPS_DISPATCH_CYCLES */
230 EVENT_CONSTRAINT(0xcb, 0x1, INTEL_ARCH_EVENT_MASK), /* MEM_LOAD_RETIRED */
234 static struct event_constraint intel_nehalem_event_constraints[] =
236 EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32)), INTEL_ARCH_FIXED_MASK), /* INSTRUCTIONS_RETIRED */
237 EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33)), INTEL_ARCH_FIXED_MASK), /* UNHALTED_CORE_CYCLES */
238 EVENT_CONSTRAINT(0x40, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_CACHE_LD */
239 EVENT_CONSTRAINT(0x41, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_CACHE_ST */
240 EVENT_CONSTRAINT(0x42, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_CACHE_LOCK */
241 EVENT_CONSTRAINT(0x43, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_ALL_REF */
242 EVENT_CONSTRAINT(0x4e, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_PREFETCH */
243 EVENT_CONSTRAINT(0x4c, 0x3, INTEL_ARCH_EVENT_MASK), /* LOAD_HIT_PRE */
244 EVENT_CONSTRAINT(0x51, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D */
245 EVENT_CONSTRAINT(0x52, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
246 EVENT_CONSTRAINT(0x53, 0x3, INTEL_ARCH_EVENT_MASK), /* L1D_CACHE_LOCK_FB_HIT */
247 EVENT_CONSTRAINT(0xc5, 0x3, INTEL_ARCH_EVENT_MASK), /* CACHE_LOCK_CYCLES */
251 static struct event_constraint intel_gen_event_constraints[] =
253 EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32)), INTEL_ARCH_FIXED_MASK), /* INSTRUCTIONS_RETIRED */
254 EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33)), INTEL_ARCH_FIXED_MASK), /* UNHALTED_CORE_CYCLES */
258 static u64 intel_pmu_event_map(int hw_event)
260 return intel_perfmon_event_map[hw_event];
264 * Generalized hw caching related hw_event table, filled
265 * in on a per model basis. A value of 0 means
266 * 'not supported', -1 means 'hw_event makes no sense on
267 * this CPU', any other value means the raw hw_event
271 #define C(x) PERF_COUNT_HW_CACHE_##x
273 static u64 __read_mostly hw_cache_event_ids
274 [PERF_COUNT_HW_CACHE_MAX]
275 [PERF_COUNT_HW_CACHE_OP_MAX]
276 [PERF_COUNT_HW_CACHE_RESULT_MAX];
278 static __initconst u64 nehalem_hw_cache_event_ids
279 [PERF_COUNT_HW_CACHE_MAX]
280 [PERF_COUNT_HW_CACHE_OP_MAX]
281 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
285 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
286 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
289 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
290 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
292 [ C(OP_PREFETCH) ] = {
293 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
294 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
299 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
300 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
303 [ C(RESULT_ACCESS) ] = -1,
304 [ C(RESULT_MISS) ] = -1,
306 [ C(OP_PREFETCH) ] = {
307 [ C(RESULT_ACCESS) ] = 0x0,
308 [ C(RESULT_MISS) ] = 0x0,
313 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
314 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
317 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
318 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
320 [ C(OP_PREFETCH) ] = {
321 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
322 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
327 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
328 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
331 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
332 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
334 [ C(OP_PREFETCH) ] = {
335 [ C(RESULT_ACCESS) ] = 0x0,
336 [ C(RESULT_MISS) ] = 0x0,
341 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
342 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
345 [ C(RESULT_ACCESS) ] = -1,
346 [ C(RESULT_MISS) ] = -1,
348 [ C(OP_PREFETCH) ] = {
349 [ C(RESULT_ACCESS) ] = -1,
350 [ C(RESULT_MISS) ] = -1,
355 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
356 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
359 [ C(RESULT_ACCESS) ] = -1,
360 [ C(RESULT_MISS) ] = -1,
362 [ C(OP_PREFETCH) ] = {
363 [ C(RESULT_ACCESS) ] = -1,
364 [ C(RESULT_MISS) ] = -1,
369 static __initconst u64 core2_hw_cache_event_ids
370 [PERF_COUNT_HW_CACHE_MAX]
371 [PERF_COUNT_HW_CACHE_OP_MAX]
372 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
376 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
377 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
380 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
381 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
385 [ C(RESULT_MISS) ] = 0,
390 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
391 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
394 [ C(RESULT_ACCESS) ] = -1,
395 [ C(RESULT_MISS) ] = -1,
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = 0,
399 [ C(RESULT_MISS) ] = 0,
404 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
405 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
408 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
409 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
411 [ C(OP_PREFETCH) ] = {
412 [ C(RESULT_ACCESS) ] = 0,
413 [ C(RESULT_MISS) ] = 0,
418 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
419 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
422 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
423 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
425 [ C(OP_PREFETCH) ] = {
426 [ C(RESULT_ACCESS) ] = 0,
427 [ C(RESULT_MISS) ] = 0,
432 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
433 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
436 [ C(RESULT_ACCESS) ] = -1,
437 [ C(RESULT_MISS) ] = -1,
439 [ C(OP_PREFETCH) ] = {
440 [ C(RESULT_ACCESS) ] = -1,
441 [ C(RESULT_MISS) ] = -1,
446 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
447 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
450 [ C(RESULT_ACCESS) ] = -1,
451 [ C(RESULT_MISS) ] = -1,
453 [ C(OP_PREFETCH) ] = {
454 [ C(RESULT_ACCESS) ] = -1,
455 [ C(RESULT_MISS) ] = -1,
460 static __initconst u64 atom_hw_cache_event_ids
461 [PERF_COUNT_HW_CACHE_MAX]
462 [PERF_COUNT_HW_CACHE_OP_MAX]
463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
467 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
468 [ C(RESULT_MISS) ] = 0,
471 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
472 [ C(RESULT_MISS) ] = 0,
474 [ C(OP_PREFETCH) ] = {
475 [ C(RESULT_ACCESS) ] = 0x0,
476 [ C(RESULT_MISS) ] = 0,
481 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
482 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
485 [ C(RESULT_ACCESS) ] = -1,
486 [ C(RESULT_MISS) ] = -1,
488 [ C(OP_PREFETCH) ] = {
489 [ C(RESULT_ACCESS) ] = 0,
490 [ C(RESULT_MISS) ] = 0,
495 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
496 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
499 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
500 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
502 [ C(OP_PREFETCH) ] = {
503 [ C(RESULT_ACCESS) ] = 0,
504 [ C(RESULT_MISS) ] = 0,
509 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
510 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
513 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
514 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
516 [ C(OP_PREFETCH) ] = {
517 [ C(RESULT_ACCESS) ] = 0,
518 [ C(RESULT_MISS) ] = 0,
523 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
524 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
527 [ C(RESULT_ACCESS) ] = -1,
528 [ C(RESULT_MISS) ] = -1,
530 [ C(OP_PREFETCH) ] = {
531 [ C(RESULT_ACCESS) ] = -1,
532 [ C(RESULT_MISS) ] = -1,
537 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
538 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
541 [ C(RESULT_ACCESS) ] = -1,
542 [ C(RESULT_MISS) ] = -1,
544 [ C(OP_PREFETCH) ] = {
545 [ C(RESULT_ACCESS) ] = -1,
546 [ C(RESULT_MISS) ] = -1,
551 static u64 intel_pmu_raw_event(u64 hw_event)
553 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
554 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
555 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
556 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
557 #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
559 #define CORE_EVNTSEL_MASK \
560 (INTEL_ARCH_EVTSEL_MASK | \
561 INTEL_ARCH_UNIT_MASK | \
562 INTEL_ARCH_EDGE_MASK | \
563 INTEL_ARCH_INV_MASK | \
566 return hw_event & CORE_EVNTSEL_MASK;
569 static __initconst u64 amd_hw_cache_event_ids
570 [PERF_COUNT_HW_CACHE_MAX]
571 [PERF_COUNT_HW_CACHE_OP_MAX]
572 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
576 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
577 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
580 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
581 [ C(RESULT_MISS) ] = 0,
583 [ C(OP_PREFETCH) ] = {
584 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
585 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
590 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
591 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
594 [ C(RESULT_ACCESS) ] = -1,
595 [ C(RESULT_MISS) ] = -1,
597 [ C(OP_PREFETCH) ] = {
598 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
599 [ C(RESULT_MISS) ] = 0,
604 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
605 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
608 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
609 [ C(RESULT_MISS) ] = 0,
611 [ C(OP_PREFETCH) ] = {
612 [ C(RESULT_ACCESS) ] = 0,
613 [ C(RESULT_MISS) ] = 0,
618 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
619 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
622 [ C(RESULT_ACCESS) ] = 0,
623 [ C(RESULT_MISS) ] = 0,
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = 0,
627 [ C(RESULT_MISS) ] = 0,
632 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
633 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
636 [ C(RESULT_ACCESS) ] = -1,
637 [ C(RESULT_MISS) ] = -1,
639 [ C(OP_PREFETCH) ] = {
640 [ C(RESULT_ACCESS) ] = -1,
641 [ C(RESULT_MISS) ] = -1,
646 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
647 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
650 [ C(RESULT_ACCESS) ] = -1,
651 [ C(RESULT_MISS) ] = -1,
653 [ C(OP_PREFETCH) ] = {
654 [ C(RESULT_ACCESS) ] = -1,
655 [ C(RESULT_MISS) ] = -1,
661 * AMD Performance Monitor K7 and later.
663 static const u64 amd_perfmon_event_map[] =
665 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
666 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
667 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
668 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
669 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
670 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
673 static u64 amd_pmu_event_map(int hw_event)
675 return amd_perfmon_event_map[hw_event];
678 static u64 amd_pmu_raw_event(u64 hw_event)
680 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
681 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
682 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
683 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
684 #define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
686 #define K7_EVNTSEL_MASK \
687 (K7_EVNTSEL_EVENT_MASK | \
688 K7_EVNTSEL_UNIT_MASK | \
689 K7_EVNTSEL_EDGE_MASK | \
690 K7_EVNTSEL_INV_MASK | \
693 return hw_event & K7_EVNTSEL_MASK;
697 * Propagate event elapsed time into the generic event.
698 * Can only be executed on the CPU where the event is active.
699 * Returns the delta events processed.
702 x86_perf_event_update(struct perf_event *event,
703 struct hw_perf_event *hwc, int idx)
705 int shift = 64 - x86_pmu.event_bits;
706 u64 prev_raw_count, new_raw_count;
709 if (idx == X86_PMC_IDX_FIXED_BTS)
713 * Careful: an NMI might modify the previous event value.
715 * Our tactic to handle this is to first atomically read and
716 * exchange a new raw count - then add that new-prev delta
717 * count to the generic event atomically:
720 prev_raw_count = atomic64_read(&hwc->prev_count);
721 rdmsrl(hwc->event_base + idx, new_raw_count);
723 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
724 new_raw_count) != prev_raw_count)
728 * Now we have the new raw value and have updated the prev
729 * timestamp already. We can now calculate the elapsed delta
730 * (event-)time and add that to the generic event.
732 * Careful, not all hw sign-extends above the physical width
735 delta = (new_raw_count << shift) - (prev_raw_count << shift);
738 atomic64_add(delta, &event->count);
739 atomic64_sub(delta, &hwc->period_left);
741 return new_raw_count;
744 static atomic_t active_events;
745 static DEFINE_MUTEX(pmc_reserve_mutex);
747 static bool reserve_pmc_hardware(void)
749 #ifdef CONFIG_X86_LOCAL_APIC
752 if (nmi_watchdog == NMI_LOCAL_APIC)
753 disable_lapic_nmi_watchdog();
755 for (i = 0; i < x86_pmu.num_events; i++) {
756 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
760 for (i = 0; i < x86_pmu.num_events; i++) {
761 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
768 #ifdef CONFIG_X86_LOCAL_APIC
770 for (i--; i >= 0; i--)
771 release_evntsel_nmi(x86_pmu.eventsel + i);
773 i = x86_pmu.num_events;
776 for (i--; i >= 0; i--)
777 release_perfctr_nmi(x86_pmu.perfctr + i);
779 if (nmi_watchdog == NMI_LOCAL_APIC)
780 enable_lapic_nmi_watchdog();
786 static void release_pmc_hardware(void)
788 #ifdef CONFIG_X86_LOCAL_APIC
791 for (i = 0; i < x86_pmu.num_events; i++) {
792 release_perfctr_nmi(x86_pmu.perfctr + i);
793 release_evntsel_nmi(x86_pmu.eventsel + i);
796 if (nmi_watchdog == NMI_LOCAL_APIC)
797 enable_lapic_nmi_watchdog();
801 static inline bool bts_available(void)
803 return x86_pmu.enable_bts != NULL;
806 static inline void init_debug_store_on_cpu(int cpu)
808 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
813 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
814 (u32)((u64)(unsigned long)ds),
815 (u32)((u64)(unsigned long)ds >> 32));
818 static inline void fini_debug_store_on_cpu(int cpu)
820 if (!per_cpu(cpu_hw_events, cpu).ds)
823 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
826 static void release_bts_hardware(void)
830 if (!bts_available())
835 for_each_online_cpu(cpu)
836 fini_debug_store_on_cpu(cpu);
838 for_each_possible_cpu(cpu) {
839 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
844 per_cpu(cpu_hw_events, cpu).ds = NULL;
846 kfree((void *)(unsigned long)ds->bts_buffer_base);
853 static int reserve_bts_hardware(void)
857 if (!bts_available())
862 for_each_possible_cpu(cpu) {
863 struct debug_store *ds;
867 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
868 if (unlikely(!buffer))
871 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
877 ds->bts_buffer_base = (u64)(unsigned long)buffer;
878 ds->bts_index = ds->bts_buffer_base;
879 ds->bts_absolute_maximum =
880 ds->bts_buffer_base + BTS_BUFFER_SIZE;
881 ds->bts_interrupt_threshold =
882 ds->bts_absolute_maximum - BTS_OVFL_TH;
884 per_cpu(cpu_hw_events, cpu).ds = ds;
889 release_bts_hardware();
891 for_each_online_cpu(cpu)
892 init_debug_store_on_cpu(cpu);
900 static void hw_perf_event_destroy(struct perf_event *event)
902 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
903 release_pmc_hardware();
904 release_bts_hardware();
905 mutex_unlock(&pmc_reserve_mutex);
909 static inline int x86_pmu_initialized(void)
911 return x86_pmu.handle_irq != NULL;
915 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
917 unsigned int cache_type, cache_op, cache_result;
920 config = attr->config;
922 cache_type = (config >> 0) & 0xff;
923 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
926 cache_op = (config >> 8) & 0xff;
927 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
930 cache_result = (config >> 16) & 0xff;
931 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
934 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
947 static void intel_pmu_enable_bts(u64 config)
949 unsigned long debugctlmsr;
951 debugctlmsr = get_debugctlmsr();
953 debugctlmsr |= X86_DEBUGCTL_TR;
954 debugctlmsr |= X86_DEBUGCTL_BTS;
955 debugctlmsr |= X86_DEBUGCTL_BTINT;
957 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
958 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
960 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
961 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
963 update_debugctlmsr(debugctlmsr);
966 static void intel_pmu_disable_bts(void)
968 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
969 unsigned long debugctlmsr;
974 debugctlmsr = get_debugctlmsr();
977 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
978 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
980 update_debugctlmsr(debugctlmsr);
984 * Setup the hardware configuration for a given attr_type
986 static int __hw_perf_event_init(struct perf_event *event)
988 struct perf_event_attr *attr = &event->attr;
989 struct hw_perf_event *hwc = &event->hw;
993 if (!x86_pmu_initialized())
997 if (!atomic_inc_not_zero(&active_events)) {
998 mutex_lock(&pmc_reserve_mutex);
999 if (atomic_read(&active_events) == 0) {
1000 if (!reserve_pmc_hardware())
1003 err = reserve_bts_hardware();
1006 atomic_inc(&active_events);
1007 mutex_unlock(&pmc_reserve_mutex);
1012 event->destroy = hw_perf_event_destroy;
1015 * Generate PMC IRQs:
1016 * (keep 'enabled' bit clear for now)
1018 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
1023 * Count user and OS events unless requested not to.
1025 if (!attr->exclude_user)
1026 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
1027 if (!attr->exclude_kernel)
1028 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
1030 if (!hwc->sample_period) {
1031 hwc->sample_period = x86_pmu.max_period;
1032 hwc->last_period = hwc->sample_period;
1033 atomic64_set(&hwc->period_left, hwc->sample_period);
1036 * If we have a PMU initialized but no APIC
1037 * interrupts, we cannot sample hardware
1038 * events (user-space has to fall back and
1039 * sample via a hrtimer based software event):
1046 * Raw hw_event type provide the config in the hw_event structure
1048 if (attr->type == PERF_TYPE_RAW) {
1049 hwc->config |= x86_pmu.raw_event(attr->config);
1053 if (attr->type == PERF_TYPE_HW_CACHE)
1054 return set_ext_hw_attr(hwc, attr);
1056 if (attr->config >= x86_pmu.max_events)
1062 config = x86_pmu.event_map(attr->config);
1073 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
1074 (hwc->sample_period == 1)) {
1075 /* BTS is not supported by this architecture. */
1076 if (!bts_available())
1079 /* BTS is currently only allowed for user-mode. */
1080 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1084 hwc->config |= config;
1089 static void p6_pmu_disable_all(void)
1091 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1100 /* p6 only has one enable register */
1101 rdmsrl(MSR_P6_EVNTSEL0, val);
1102 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1103 wrmsrl(MSR_P6_EVNTSEL0, val);
1106 static void intel_pmu_disable_all(void)
1108 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1116 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1118 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1119 intel_pmu_disable_bts();
1122 static void amd_pmu_disable_all(void)
1124 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1132 * ensure we write the disable before we start disabling the
1133 * events proper, so that amd_pmu_enable_event() does the
1138 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1141 if (!test_bit(idx, cpuc->active_mask))
1143 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
1144 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1146 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1147 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1151 void hw_perf_disable(void)
1153 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1155 if (!x86_pmu_initialized())
1161 x86_pmu.disable_all();
1164 static void p6_pmu_enable_all(void)
1166 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1175 /* p6 only has one enable register */
1176 rdmsrl(MSR_P6_EVNTSEL0, val);
1177 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1178 wrmsrl(MSR_P6_EVNTSEL0, val);
1181 static void intel_pmu_enable_all(void)
1183 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1191 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1193 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1194 struct perf_event *event =
1195 cpuc->events[X86_PMC_IDX_FIXED_BTS];
1197 if (WARN_ON_ONCE(!event))
1200 intel_pmu_enable_bts(event->hw.config);
1204 static void amd_pmu_enable_all(void)
1206 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1215 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1216 struct perf_event *event = cpuc->events[idx];
1219 if (!test_bit(idx, cpuc->active_mask))
1222 val = event->hw.config;
1223 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1224 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1228 static const struct pmu pmu;
1230 static inline int is_x86_event(struct perf_event *event)
1232 return event->pmu == &pmu;
1235 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1240 unsigned long constraints[X86_PMC_IDX_MAX][BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1241 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1242 struct hw_perf_event *hwc;
1244 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1246 for (i = 0; i < n; i++) {
1247 x86_pmu.get_event_constraints(cpuc,
1248 cpuc->event_list[i],
1253 * fastpath, try to reuse previous register
1255 for (i = 0, num = n; i < n; i++, num--) {
1256 hwc = &cpuc->event_list[i]->hw;
1259 /* never assigned */
1263 /* constraint still honored */
1264 if (!test_bit(hwc->idx, c))
1267 /* not already used */
1268 if (test_bit(hwc->idx, used_mask))
1272 pr_debug("CPU%d fast config=0x%llx idx=%d assign=%c\n",
1276 assign ? 'y' : 'n');
1279 set_bit(hwc->idx, used_mask);
1281 assign[i] = hwc->idx;
1290 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1293 * weight = number of possible counters
1295 * 1 = most constrained, only works on one counter
1296 * wmax = least constrained, works on any counter
1298 * assign events to counters starting with most
1299 * constrained events.
1301 wmax = x86_pmu.num_events;
1304 * when fixed event counters are present,
1305 * wmax is incremented by 1 to account
1306 * for one more choice
1308 if (x86_pmu.num_events_fixed)
1311 for (w = 1, num = n; num && w <= wmax; w++) {
1312 /* for each event */
1313 for (i = 0; num && i < n; i++) {
1315 hwc = &cpuc->event_list[i]->hw;
1317 weight = bitmap_weight(c, X86_PMC_IDX_MAX);
1321 for_each_bit(j, c, X86_PMC_IDX_MAX) {
1322 if (!test_bit(j, used_mask))
1326 if (j == X86_PMC_IDX_MAX)
1330 pr_debug("CPU%d slow config=0x%llx idx=%d assign=%c\n",
1334 assign ? 'y' : 'n');
1337 set_bit(j, used_mask);
1346 * scheduling failed or is just a simulation,
1347 * free resources if necessary
1349 if (!assign || num) {
1350 for (i = 0; i < n; i++) {
1351 if (x86_pmu.put_event_constraints)
1352 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
1355 return num ? -ENOSPC : 0;
1359 * dogrp: true if must collect siblings events (group)
1360 * returns total number of events and error code
1362 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1364 struct perf_event *event;
1367 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
1369 /* current number of events already accepted */
1372 if (is_x86_event(leader)) {
1375 cpuc->event_list[n] = leader;
1381 list_for_each_entry(event, &leader->sibling_list, group_entry) {
1382 if (!is_x86_event(event) ||
1383 event->state <= PERF_EVENT_STATE_OFF)
1389 cpuc->event_list[n] = event;
1396 static inline void x86_assign_hw_event(struct perf_event *event,
1397 struct hw_perf_event *hwc, int idx)
1401 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
1402 hwc->config_base = 0;
1403 hwc->event_base = 0;
1404 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
1405 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1407 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1408 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1411 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1413 hwc->config_base = x86_pmu.eventsel;
1414 hwc->event_base = x86_pmu.perfctr;
1418 void hw_perf_enable(void)
1420 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1421 struct perf_event *event;
1422 struct hw_perf_event *hwc;
1425 if (!x86_pmu_initialized())
1427 if (cpuc->n_added) {
1429 * apply assignment obtained either from
1430 * hw_perf_group_sched_in() or x86_pmu_enable()
1432 * step1: save events moving to new counters
1433 * step2: reprogram moved events into new counters
1435 for (i = 0; i < cpuc->n_events; i++) {
1437 event = cpuc->event_list[i];
1440 if (hwc->idx == -1 || hwc->idx == cpuc->assign[i])
1443 x86_pmu.disable(hwc, hwc->idx);
1445 clear_bit(hwc->idx, cpuc->active_mask);
1447 cpuc->events[hwc->idx] = NULL;
1449 x86_perf_event_update(event, hwc, hwc->idx);
1454 for (i = 0; i < cpuc->n_events; i++) {
1456 event = cpuc->event_list[i];
1459 if (hwc->idx == -1) {
1460 x86_assign_hw_event(event, hwc, cpuc->assign[i]);
1461 x86_perf_event_set_period(event, hwc, hwc->idx);
1464 * need to mark as active because x86_pmu_disable()
1465 * clear active_mask and eventsp[] yet it preserves
1468 set_bit(hwc->idx, cpuc->active_mask);
1469 cpuc->events[hwc->idx] = event;
1471 x86_pmu.enable(hwc, hwc->idx);
1472 perf_event_update_userpage(event);
1475 perf_events_lapic_init();
1477 x86_pmu.enable_all();
1480 static inline u64 intel_pmu_get_status(void)
1484 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1489 static inline void intel_pmu_ack_status(u64 ack)
1491 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1494 static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1496 (void)checking_wrmsrl(hwc->config_base + idx,
1497 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1500 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1502 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1506 intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
1508 int idx = __idx - X86_PMC_IDX_FIXED;
1511 mask = 0xfULL << (idx * 4);
1513 rdmsrl(hwc->config_base, ctrl_val);
1515 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1519 p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1521 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1522 u64 val = P6_NOP_EVENT;
1525 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1527 (void)checking_wrmsrl(hwc->config_base + idx, val);
1531 intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1533 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1534 intel_pmu_disable_bts();
1538 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1539 intel_pmu_disable_fixed(hwc, idx);
1543 x86_pmu_disable_event(hwc, idx);
1547 amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1549 x86_pmu_disable_event(hwc, idx);
1552 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1555 * Set the next IRQ period, based on the hwc->period_left value.
1556 * To be called with the event disabled in hw:
1559 x86_perf_event_set_period(struct perf_event *event,
1560 struct hw_perf_event *hwc, int idx)
1562 s64 left = atomic64_read(&hwc->period_left);
1563 s64 period = hwc->sample_period;
1566 if (idx == X86_PMC_IDX_FIXED_BTS)
1570 * If we are way outside a reasonable range then just skip forward:
1572 if (unlikely(left <= -period)) {
1574 atomic64_set(&hwc->period_left, left);
1575 hwc->last_period = period;
1579 if (unlikely(left <= 0)) {
1581 atomic64_set(&hwc->period_left, left);
1582 hwc->last_period = period;
1586 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1588 if (unlikely(left < 2))
1591 if (left > x86_pmu.max_period)
1592 left = x86_pmu.max_period;
1594 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1597 * The hw event starts counting from this event offset,
1598 * mark it to be able to extra future deltas:
1600 atomic64_set(&hwc->prev_count, (u64)-left);
1602 err = checking_wrmsrl(hwc->event_base + idx,
1603 (u64)(-left) & x86_pmu.event_mask);
1605 perf_event_update_userpage(event);
1611 intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1613 int idx = __idx - X86_PMC_IDX_FIXED;
1614 u64 ctrl_val, bits, mask;
1618 * Enable IRQ generation (0x8),
1619 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1623 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1625 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1628 mask = 0xfULL << (idx * 4);
1630 rdmsrl(hwc->config_base, ctrl_val);
1633 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1636 static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1638 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1643 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1645 (void)checking_wrmsrl(hwc->config_base + idx, val);
1649 static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1651 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1652 if (!__get_cpu_var(cpu_hw_events).enabled)
1655 intel_pmu_enable_bts(hwc->config);
1659 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1660 intel_pmu_enable_fixed(hwc, idx);
1664 x86_pmu_enable_event(hwc, idx);
1667 static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1669 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1672 x86_pmu_enable_event(hwc, idx);
1676 * activate a single event
1678 * The event is added to the group of enabled events
1679 * but only if it can be scehduled with existing events.
1681 * Called with PMU disabled. If successful and return value 1,
1682 * then guaranteed to call perf_enable() and hw_perf_enable()
1684 static int x86_pmu_enable(struct perf_event *event)
1686 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1687 struct hw_perf_event *hwc;
1688 int assign[X86_PMC_IDX_MAX];
1693 n0 = cpuc->n_events;
1694 n = collect_events(cpuc, event, false);
1698 ret = x86_schedule_events(cpuc, n, assign);
1702 * copy new assignment, now we know it is possible
1703 * will be used by hw_perf_enable()
1705 memcpy(cpuc->assign, assign, n*sizeof(int));
1708 cpuc->n_added = n - n0;
1711 x86_perf_event_set_period(event, hwc, hwc->idx);
1716 static void x86_pmu_unthrottle(struct perf_event *event)
1718 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1719 struct hw_perf_event *hwc = &event->hw;
1721 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1722 cpuc->events[hwc->idx] != event))
1725 x86_pmu.enable(hwc, hwc->idx);
1728 void perf_event_print_debug(void)
1730 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1731 struct cpu_hw_events *cpuc;
1732 unsigned long flags;
1735 if (!x86_pmu.num_events)
1738 local_irq_save(flags);
1740 cpu = smp_processor_id();
1741 cpuc = &per_cpu(cpu_hw_events, cpu);
1743 if (x86_pmu.version >= 2) {
1744 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1745 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1746 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1747 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1750 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1751 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1752 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1753 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1755 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1757 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1758 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1759 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1761 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1763 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1764 cpu, idx, pmc_ctrl);
1765 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1766 cpu, idx, pmc_count);
1767 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1768 cpu, idx, prev_left);
1770 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1771 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1773 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1774 cpu, idx, pmc_count);
1776 local_irq_restore(flags);
1779 static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
1781 struct debug_store *ds = cpuc->ds;
1787 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1788 struct bts_record *at, *top;
1789 struct perf_output_handle handle;
1790 struct perf_event_header header;
1791 struct perf_sample_data data;
1792 struct pt_regs regs;
1800 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1801 top = (struct bts_record *)(unsigned long)ds->bts_index;
1806 ds->bts_index = ds->bts_buffer_base;
1809 data.period = event->hw.last_period;
1815 * Prepare a generic sample, i.e. fill in the invariant fields.
1816 * We will overwrite the from and to address before we output
1819 perf_prepare_sample(&header, &data, event, ®s);
1821 if (perf_output_begin(&handle, event,
1822 header.size * (top - at), 1, 1))
1825 for (; at < top; at++) {
1829 perf_output_sample(&handle, &header, &data, event);
1832 perf_output_end(&handle);
1834 /* There's new data available. */
1835 event->hw.interrupts++;
1836 event->pending_kill = POLL_IN;
1839 static void x86_pmu_disable(struct perf_event *event)
1841 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1842 struct hw_perf_event *hwc = &event->hw;
1843 int i, idx = hwc->idx;
1846 * Must be done before we disable, otherwise the nmi handler
1847 * could reenable again:
1849 clear_bit(idx, cpuc->active_mask);
1850 x86_pmu.disable(hwc, idx);
1853 * Make sure the cleared pointer becomes visible before we
1854 * (potentially) free the event:
1859 * Drain the remaining delta count out of a event
1860 * that we are disabling:
1862 x86_perf_event_update(event, hwc, idx);
1864 /* Drain the remaining BTS records. */
1865 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1866 intel_pmu_drain_bts_buffer(cpuc);
1868 cpuc->events[idx] = NULL;
1870 for (i = 0; i < cpuc->n_events; i++) {
1871 if (event == cpuc->event_list[i]) {
1873 if (x86_pmu.put_event_constraints)
1874 x86_pmu.put_event_constraints(cpuc, event);
1876 while (++i < cpuc->n_events)
1877 cpuc->event_list[i-1] = cpuc->event_list[i];
1882 perf_event_update_userpage(event);
1886 * Save and restart an expired event. Called by NMI contexts,
1887 * so it has to be careful about preempting normal event ops:
1889 static int intel_pmu_save_and_restart(struct perf_event *event)
1891 struct hw_perf_event *hwc = &event->hw;
1895 x86_perf_event_update(event, hwc, idx);
1896 ret = x86_perf_event_set_period(event, hwc, idx);
1898 if (event->state == PERF_EVENT_STATE_ACTIVE)
1899 intel_pmu_enable_event(hwc, idx);
1904 static void intel_pmu_reset(void)
1906 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1907 unsigned long flags;
1910 if (!x86_pmu.num_events)
1913 local_irq_save(flags);
1915 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1917 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1918 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1919 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1921 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1922 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1925 ds->bts_index = ds->bts_buffer_base;
1927 local_irq_restore(flags);
1930 static int p6_pmu_handle_irq(struct pt_regs *regs)
1932 struct perf_sample_data data;
1933 struct cpu_hw_events *cpuc;
1934 struct perf_event *event;
1935 struct hw_perf_event *hwc;
1936 int idx, handled = 0;
1942 cpuc = &__get_cpu_var(cpu_hw_events);
1944 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1945 if (!test_bit(idx, cpuc->active_mask))
1948 event = cpuc->events[idx];
1951 val = x86_perf_event_update(event, hwc, idx);
1952 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1959 data.period = event->hw.last_period;
1961 if (!x86_perf_event_set_period(event, hwc, idx))
1964 if (perf_event_overflow(event, 1, &data, regs))
1965 p6_pmu_disable_event(hwc, idx);
1969 inc_irq_stat(apic_perf_irqs);
1975 * This handler is triggered by the local APIC, so the APIC IRQ handling
1978 static int intel_pmu_handle_irq(struct pt_regs *regs)
1980 struct perf_sample_data data;
1981 struct cpu_hw_events *cpuc;
1988 cpuc = &__get_cpu_var(cpu_hw_events);
1991 intel_pmu_drain_bts_buffer(cpuc);
1992 status = intel_pmu_get_status();
2000 if (++loops > 100) {
2001 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
2002 perf_event_print_debug();
2008 inc_irq_stat(apic_perf_irqs);
2010 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2011 struct perf_event *event = cpuc->events[bit];
2013 clear_bit(bit, (unsigned long *) &status);
2014 if (!test_bit(bit, cpuc->active_mask))
2017 if (!intel_pmu_save_and_restart(event))
2020 data.period = event->hw.last_period;
2022 if (perf_event_overflow(event, 1, &data, regs))
2023 intel_pmu_disable_event(&event->hw, bit);
2026 intel_pmu_ack_status(ack);
2029 * Repeat if there is more work to be done:
2031 status = intel_pmu_get_status();
2040 static int amd_pmu_handle_irq(struct pt_regs *regs)
2042 struct perf_sample_data data;
2043 struct cpu_hw_events *cpuc;
2044 struct perf_event *event;
2045 struct hw_perf_event *hwc;
2046 int idx, handled = 0;
2052 cpuc = &__get_cpu_var(cpu_hw_events);
2054 for (idx = 0; idx < x86_pmu.num_events; idx++) {
2055 if (!test_bit(idx, cpuc->active_mask))
2058 event = cpuc->events[idx];
2061 val = x86_perf_event_update(event, hwc, idx);
2062 if (val & (1ULL << (x86_pmu.event_bits - 1)))
2069 data.period = event->hw.last_period;
2071 if (!x86_perf_event_set_period(event, hwc, idx))
2074 if (perf_event_overflow(event, 1, &data, regs))
2075 amd_pmu_disable_event(hwc, idx);
2079 inc_irq_stat(apic_perf_irqs);
2084 void smp_perf_pending_interrupt(struct pt_regs *regs)
2088 inc_irq_stat(apic_pending_irqs);
2089 perf_event_do_pending();
2093 void set_perf_event_pending(void)
2095 #ifdef CONFIG_X86_LOCAL_APIC
2096 if (!x86_pmu.apic || !x86_pmu_initialized())
2099 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
2103 void perf_events_lapic_init(void)
2105 #ifdef CONFIG_X86_LOCAL_APIC
2106 if (!x86_pmu.apic || !x86_pmu_initialized())
2110 * Always use NMI for PMU
2112 apic_write(APIC_LVTPC, APIC_DM_NMI);
2116 static int __kprobes
2117 perf_event_nmi_handler(struct notifier_block *self,
2118 unsigned long cmd, void *__args)
2120 struct die_args *args = __args;
2121 struct pt_regs *regs;
2123 if (!atomic_read(&active_events))
2137 #ifdef CONFIG_X86_LOCAL_APIC
2138 apic_write(APIC_LVTPC, APIC_DM_NMI);
2141 * Can't rely on the handled return value to say it was our NMI, two
2142 * events could trigger 'simultaneously' raising two back-to-back NMIs.
2144 * If the first NMI handles both, the latter will be empty and daze
2147 x86_pmu.handle_irq(regs);
2152 static struct event_constraint bts_constraint =
2153 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
2155 static int intel_special_constraints(struct perf_event *event,
2156 unsigned long *idxmsk)
2158 unsigned int hw_event;
2160 hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
2162 if (unlikely((hw_event ==
2163 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
2164 (event->hw.sample_period == 1))) {
2166 bitmap_copy((unsigned long *)idxmsk,
2167 (unsigned long *)bts_constraint.idxmsk,
2174 static void intel_get_event_constraints(struct cpu_hw_events *cpuc,
2175 struct perf_event *event,
2176 unsigned long *idxmsk)
2178 const struct event_constraint *c;
2183 bitmap_zero(idxmsk, X86_PMC_IDX_MAX);
2185 if (intel_special_constraints(event, idxmsk))
2188 if (x86_pmu.event_constraints) {
2189 for_each_event_constraint(c, x86_pmu.event_constraints) {
2190 if ((event->hw.config & c->cmask) == c->code) {
2191 bitmap_copy(idxmsk, c->idxmsk, X86_PMC_IDX_MAX);
2196 /* no constraints, means supports all generic counters */
2197 bitmap_fill((unsigned long *)idxmsk, x86_pmu.num_events);
2200 static void amd_get_event_constraints(struct cpu_hw_events *cpuc,
2201 struct perf_event *event,
2202 unsigned long *idxmsk)
2204 /* no constraints, means supports all generic counters */
2205 bitmap_fill(idxmsk, x86_pmu.num_events);
2208 static int x86_event_sched_in(struct perf_event *event,
2209 struct perf_cpu_context *cpuctx, int cpu)
2213 event->state = PERF_EVENT_STATE_ACTIVE;
2215 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
2217 if (!is_x86_event(event))
2218 ret = event->pmu->enable(event);
2220 if (!ret && !is_software_event(event))
2221 cpuctx->active_oncpu++;
2223 if (!ret && event->attr.exclusive)
2224 cpuctx->exclusive = 1;
2229 static void x86_event_sched_out(struct perf_event *event,
2230 struct perf_cpu_context *cpuctx, int cpu)
2232 event->state = PERF_EVENT_STATE_INACTIVE;
2235 if (!is_x86_event(event))
2236 event->pmu->disable(event);
2238 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
2240 if (!is_software_event(event))
2241 cpuctx->active_oncpu--;
2243 if (event->attr.exclusive || !cpuctx->active_oncpu)
2244 cpuctx->exclusive = 0;
2248 * Called to enable a whole group of events.
2249 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
2250 * Assumes the caller has disabled interrupts and has
2251 * frozen the PMU with hw_perf_save_disable.
2253 * called with PMU disabled. If successful and return value 1,
2254 * then guaranteed to call perf_enable() and hw_perf_enable()
2256 int hw_perf_group_sched_in(struct perf_event *leader,
2257 struct perf_cpu_context *cpuctx,
2258 struct perf_event_context *ctx, int cpu)
2260 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2261 struct perf_event *sub;
2262 int assign[X86_PMC_IDX_MAX];
2265 /* n0 = total number of events */
2266 n0 = collect_events(cpuc, leader, true);
2270 ret = x86_schedule_events(cpuc, n0, assign);
2274 ret = x86_event_sched_in(leader, cpuctx, cpu);
2279 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2280 if (sub->state > PERF_EVENT_STATE_OFF) {
2281 ret = x86_event_sched_in(sub, cpuctx, cpu);
2288 * copy new assignment, now we know it is possible
2289 * will be used by hw_perf_enable()
2291 memcpy(cpuc->assign, assign, n0*sizeof(int));
2293 cpuc->n_events = n0;
2295 ctx->nr_active += n1;
2298 * 1 means successful and events are active
2299 * This is not quite true because we defer
2300 * actual activation until hw_perf_enable() but
2301 * this way we* ensure caller won't try to enable
2306 x86_event_sched_out(leader, cpuctx, cpu);
2308 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2309 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
2310 x86_event_sched_out(sub, cpuctx, cpu);
2318 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
2319 .notifier_call = perf_event_nmi_handler,
2324 static __initconst struct x86_pmu p6_pmu = {
2326 .handle_irq = p6_pmu_handle_irq,
2327 .disable_all = p6_pmu_disable_all,
2328 .enable_all = p6_pmu_enable_all,
2329 .enable = p6_pmu_enable_event,
2330 .disable = p6_pmu_disable_event,
2331 .eventsel = MSR_P6_EVNTSEL0,
2332 .perfctr = MSR_P6_PERFCTR0,
2333 .event_map = p6_pmu_event_map,
2334 .raw_event = p6_pmu_raw_event,
2335 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
2337 .max_period = (1ULL << 31) - 1,
2341 * Events have 40 bits implemented. However they are designed such
2342 * that bits [32-39] are sign extensions of bit 31. As such the
2343 * effective width of a event for P6-like PMU is 32 bits only.
2345 * See IA-32 Intel Architecture Software developer manual Vol 3B
2348 .event_mask = (1ULL << 32) - 1,
2349 .get_event_constraints = intel_get_event_constraints,
2350 .event_constraints = intel_p6_event_constraints
2353 static __initconst struct x86_pmu intel_pmu = {
2355 .handle_irq = intel_pmu_handle_irq,
2356 .disable_all = intel_pmu_disable_all,
2357 .enable_all = intel_pmu_enable_all,
2358 .enable = intel_pmu_enable_event,
2359 .disable = intel_pmu_disable_event,
2360 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2361 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2362 .event_map = intel_pmu_event_map,
2363 .raw_event = intel_pmu_raw_event,
2364 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2367 * Intel PMCs cannot be accessed sanely above 32 bit width,
2368 * so we install an artificial 1<<31 period regardless of
2369 * the generic event period:
2371 .max_period = (1ULL << 31) - 1,
2372 .enable_bts = intel_pmu_enable_bts,
2373 .disable_bts = intel_pmu_disable_bts,
2374 .get_event_constraints = intel_get_event_constraints
2377 static __initconst struct x86_pmu amd_pmu = {
2379 .handle_irq = amd_pmu_handle_irq,
2380 .disable_all = amd_pmu_disable_all,
2381 .enable_all = amd_pmu_enable_all,
2382 .enable = amd_pmu_enable_event,
2383 .disable = amd_pmu_disable_event,
2384 .eventsel = MSR_K7_EVNTSEL0,
2385 .perfctr = MSR_K7_PERFCTR0,
2386 .event_map = amd_pmu_event_map,
2387 .raw_event = amd_pmu_raw_event,
2388 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
2391 .event_mask = (1ULL << 48) - 1,
2393 /* use highest bit to detect overflow */
2394 .max_period = (1ULL << 47) - 1,
2395 .get_event_constraints = amd_get_event_constraints
2398 static __init int p6_pmu_init(void)
2400 switch (boot_cpu_data.x86_model) {
2402 case 3: /* Pentium Pro */
2404 case 6: /* Pentium II */
2407 case 11: /* Pentium III */
2413 pr_cont("unsupported p6 CPU model %d ",
2414 boot_cpu_data.x86_model);
2423 static __init int intel_pmu_init(void)
2425 union cpuid10_edx edx;
2426 union cpuid10_eax eax;
2427 unsigned int unused;
2431 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2432 /* check for P6 processor family */
2433 if (boot_cpu_data.x86 == 6) {
2434 return p6_pmu_init();
2441 * Check whether the Architectural PerfMon supports
2442 * Branch Misses Retired hw_event or not.
2444 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
2445 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
2448 version = eax.split.version_id;
2452 x86_pmu = intel_pmu;
2453 x86_pmu.version = version;
2454 x86_pmu.num_events = eax.split.num_events;
2455 x86_pmu.event_bits = eax.split.bit_width;
2456 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
2459 * Quirk: v2 perfmon does not report fixed-purpose events, so
2460 * assume at least 3 events:
2462 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
2465 * Install the hw-cache-events table:
2467 switch (boot_cpu_data.x86_model) {
2468 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2469 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2470 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2471 case 29: /* six-core 45 nm xeon "Dunnington" */
2472 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2473 sizeof(hw_cache_event_ids));
2475 x86_pmu.event_constraints = intel_core_event_constraints;
2476 pr_cont("Core2 events, ");
2479 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2480 sizeof(hw_cache_event_ids));
2482 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2483 pr_cont("Nehalem/Corei7 events, ");
2486 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2487 sizeof(hw_cache_event_ids));
2489 x86_pmu.event_constraints = intel_gen_event_constraints;
2490 pr_cont("Atom events, ");
2494 * default constraints for v2 and up
2496 x86_pmu.event_constraints = intel_gen_event_constraints;
2497 pr_cont("generic architected perfmon, ");
2502 static __init int amd_pmu_init(void)
2504 /* Performance-monitoring supported from K7 and later: */
2505 if (boot_cpu_data.x86 < 6)
2510 /* Events are common for all AMDs */
2511 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2512 sizeof(hw_cache_event_ids));
2517 static void __init pmu_check_apic(void)
2523 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
2524 pr_info("no hardware sampling interrupt available.\n");
2527 void __init init_hw_perf_events(void)
2531 pr_info("Performance Events: ");
2533 switch (boot_cpu_data.x86_vendor) {
2534 case X86_VENDOR_INTEL:
2535 err = intel_pmu_init();
2537 case X86_VENDOR_AMD:
2538 err = amd_pmu_init();
2544 pr_cont("no PMU driver, software events only.\n");
2550 pr_cont("%s PMU driver.\n", x86_pmu.name);
2552 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2553 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2554 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2555 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
2557 perf_event_mask = (1 << x86_pmu.num_events) - 1;
2558 perf_max_events = x86_pmu.num_events;
2560 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2561 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2562 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2563 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
2567 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2568 x86_pmu.intel_ctrl = perf_event_mask;
2570 perf_events_lapic_init();
2571 register_die_notifier(&perf_event_nmi_notifier);
2573 pr_info("... version: %d\n", x86_pmu.version);
2574 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2575 pr_info("... generic registers: %d\n", x86_pmu.num_events);
2576 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
2577 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2578 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
2579 pr_info("... event mask: %016Lx\n", perf_event_mask);
2582 static inline void x86_pmu_read(struct perf_event *event)
2584 x86_perf_event_update(event, &event->hw, event->hw.idx);
2587 static const struct pmu pmu = {
2588 .enable = x86_pmu_enable,
2589 .disable = x86_pmu_disable,
2590 .read = x86_pmu_read,
2591 .unthrottle = x86_pmu_unthrottle,
2595 * validate a single event group
2597 * validation include:
2598 * - check events are compatible which each other
2599 * - events do not compete for the same counter
2600 * - number of events <= number of counters
2602 * validation ensures the group can be loaded onto the
2603 * PMU if it was the only group available.
2605 static int validate_group(struct perf_event *event)
2607 struct perf_event *leader = event->group_leader;
2608 struct cpu_hw_events *fake_cpuc;
2612 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
2617 * the event is not yet connected with its
2618 * siblings therefore we must first collect
2619 * existing siblings, then add the new event
2620 * before we can simulate the scheduling
2623 n = collect_events(fake_cpuc, leader, true);
2627 fake_cpuc->n_events = n;
2628 n = collect_events(fake_cpuc, event, false);
2632 fake_cpuc->n_events = n;
2634 ret = x86_schedule_events(fake_cpuc, n, NULL);
2642 const struct pmu *hw_perf_event_init(struct perf_event *event)
2644 const struct pmu *tmp;
2647 err = __hw_perf_event_init(event);
2650 * we temporarily connect event to its pmu
2651 * such that validate_group() can classify
2652 * it as an x86 event using is_x86_event()
2657 if (event->group_leader != event)
2658 err = validate_group(event);
2664 event->destroy(event);
2665 return ERR_PTR(err);
2676 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2678 if (entry->nr < PERF_MAX_STACK_DEPTH)
2679 entry->ip[entry->nr++] = ip;
2682 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2683 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
2687 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2689 /* Ignore warnings */
2692 static void backtrace_warning(void *data, char *msg)
2694 /* Ignore warnings */
2697 static int backtrace_stack(void *data, char *name)
2702 static void backtrace_address(void *data, unsigned long addr, int reliable)
2704 struct perf_callchain_entry *entry = data;
2707 callchain_store(entry, addr);
2710 static const struct stacktrace_ops backtrace_ops = {
2711 .warning = backtrace_warning,
2712 .warning_symbol = backtrace_warning_symbol,
2713 .stack = backtrace_stack,
2714 .address = backtrace_address,
2715 .walk_stack = print_context_stack_bp,
2718 #include "../dumpstack.h"
2721 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2723 callchain_store(entry, PERF_CONTEXT_KERNEL);
2724 callchain_store(entry, regs->ip);
2726 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
2730 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2732 static unsigned long
2733 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
2735 unsigned long offset, addr = (unsigned long)from;
2736 int type = in_nmi() ? KM_NMI : KM_IRQ0;
2737 unsigned long size, len = 0;
2743 ret = __get_user_pages_fast(addr, 1, 0, &page);
2747 offset = addr & (PAGE_SIZE - 1);
2748 size = min(PAGE_SIZE - offset, n - len);
2750 map = kmap_atomic(page, type);
2751 memcpy(to, map+offset, size);
2752 kunmap_atomic(map, type);
2764 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2766 unsigned long bytes;
2768 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2770 return bytes == sizeof(*frame);
2774 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2776 struct stack_frame frame;
2777 const void __user *fp;
2779 if (!user_mode(regs))
2780 regs = task_pt_regs(current);
2782 fp = (void __user *)regs->bp;
2784 callchain_store(entry, PERF_CONTEXT_USER);
2785 callchain_store(entry, regs->ip);
2787 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2788 frame.next_frame = NULL;
2789 frame.return_address = 0;
2791 if (!copy_stack_frame(fp, &frame))
2794 if ((unsigned long)fp < regs->sp)
2797 callchain_store(entry, frame.return_address);
2798 fp = frame.next_frame;
2803 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2810 is_user = user_mode(regs);
2812 if (is_user && current->state != TASK_RUNNING)
2816 perf_callchain_kernel(regs, entry);
2819 perf_callchain_user(regs, entry);
2822 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2824 struct perf_callchain_entry *entry;
2827 entry = &__get_cpu_var(pmc_nmi_entry);
2829 entry = &__get_cpu_var(pmc_irq_entry);
2833 perf_do_callchain(regs, entry);
2838 void hw_perf_event_setup_online(int cpu)
2840 init_debug_store_on_cpu(cpu);