arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         unsigned long size, len = 0;
  53         struct page *page;
  54         void *map;
  55         int ret;
  56
  57         do {
  58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  59                 if (!ret)
  60                         break;
  61
  62                 offset = addr & (PAGE_SIZE - 1);
  63                 size = min(PAGE_SIZE - offset, n - len);
  64
  65                 map = kmap_atomic(page);
  66                 memcpy(to, map+offset, size);
  67                 kunmap_atomic(map);
  68                 put_page(page);
  69
  70                 len  += size;
  71                 to   += size;
  72                 addr += size;
  73
  74         } while (len < n);
  75
  76         return len;
  77 }
  78
  79 struct event_constraint {
  80         union {
  81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  82                 u64             idxmsk64;
  83         };
  84         u64     code;
  85         u64     cmask;
  86         int     weight;
  87 };
  88
  89 struct amd_nb {
  90         int nb_id;  /* NorthBridge id */
  91         int refcnt; /* reference count */
  92         struct perf_event *owners[X86_PMC_IDX_MAX];
  93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  94 };
  95
  96 #define MAX_LBR_ENTRIES         16
  97
  98 struct cpu_hw_events {
  99         /*
 100          * Generic x86 PMC bits
 101          */
 102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171
 172 #define EVENT_CONSTRAINT_END            \
 173         EVENT_CONSTRAINT(0, 0, 0)
 174
 175 #define for_each_event_constraint(e, c) \
 176         for ((e) = (c); (e)->weight; (e)++)
 177
 178 union perf_capabilities {
 179         struct {
 180                 u64     lbr_format    : 6;
 181                 u64     pebs_trap     : 1;
 182                 u64     pebs_arch_reg : 1;
 183                 u64     pebs_format   : 4;
 184                 u64     smm_freeze    : 1;
 185         };
 186         u64     capabilities;
 187 };
 188
 189 /*
 190  * struct x86_pmu - generic x86 pmu
 191  */
 192 struct x86_pmu {
 193         /*
 194          * Generic x86 PMC bits
 195          */
 196         const char      *name;
 197         int             version;
 198         int             (*handle_irq)(struct pt_regs *);
 199         void            (*disable_all)(void);
 200         void            (*enable_all)(int added);
 201         void            (*enable)(struct perf_event *);
 202         void            (*disable)(struct perf_event *);
 203         int             (*hw_config)(struct perf_event *event);
 204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 205         unsigned        eventsel;
 206         unsigned        perfctr;
 207         u64             (*event_map)(int);
 208         int             max_events;
 209         int             num_counters;
 210         int             num_counters_fixed;
 211         int             cntval_bits;
 212         u64             cntval_mask;
 213         int             apic;
 214         u64             max_period;
 215         struct event_constraint *
 216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218
 219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 220                                                  struct perf_event *event);
 221         struct event_constraint *event_constraints;
 222         void            (*quirks)(void);
 223         int             perfctr_second_write;
 224
 225         int             (*cpu_prepare)(int cpu);
 226         void            (*cpu_starting)(int cpu);
 227         void            (*cpu_dying)(int cpu);
 228         void            (*cpu_dead)(int cpu);
 229
 230         /*
 231          * Intel Arch Perfmon v2+
 232          */
 233         u64                     intel_ctrl;
 234         union perf_capabilities intel_cap;
 235
 236         /*
 237          * Intel DebugStore bits
 238          */
 239         int             bts, pebs;
 240         int             bts_active, pebs_active;
 241         int             pebs_record_size;
 242         void            (*drain_pebs)(struct pt_regs *regs);
 243         struct event_constraint *pebs_constraints;
 244
 245         /*
 246          * Intel LBR
 247          */
 248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 249         int             lbr_nr;                    /* hardware stack size */
 250 };
 251
 252 static struct x86_pmu x86_pmu __read_mostly;
 253
 254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 255         .enabled = 1,
 256 };
 257
 258 static int x86_perf_event_set_period(struct perf_event *event);
 259
 260 /*
 261  * Generalized hw caching related hw_event table, filled
 262  * in on a per model basis. A value of 0 means
 263  * 'not supported', -1 means 'hw_event makes no sense on
 264  * this CPU', any other value means the raw hw_event
 265  * ID.
 266  */
 267
 268 #define C(x) PERF_COUNT_HW_CACHE_##x
 269
 270 static u64 __read_mostly hw_cache_event_ids
 271                                 [PERF_COUNT_HW_CACHE_MAX]
 272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 274
 275 /*
 276  * Propagate event elapsed time into the generic event.
 277  * Can only be executed on the CPU where the event is active.
 278  * Returns the delta events processed.
 279  */
 280 static u64
 281 x86_perf_event_update(struct perf_event *event)
 282 {
 283         struct hw_perf_event *hwc = &event->hw;
 284         int shift = 64 - x86_pmu.cntval_bits;
 285         u64 prev_raw_count, new_raw_count;
 286         int idx = hwc->idx;
 287         s64 delta;
 288
 289         if (idx == X86_PMC_IDX_FIXED_BTS)
 290                 return 0;
 291
 292         /*
 293          * Careful: an NMI might modify the previous event value.
 294          *
 295          * Our tactic to handle this is to first atomically read and
 296          * exchange a new raw count - then add that new-prev delta
 297          * count to the generic event atomically:
 298          */
 299 again:
 300         prev_raw_count = local64_read(&hwc->prev_count);
 301         rdmsrl(hwc->event_base + idx, new_raw_count);
 302
 303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 304                                         new_raw_count) != prev_raw_count)
 305                 goto again;
 306
 307         /*
 308          * Now we have the new raw value and have updated the prev
 309          * timestamp already. We can now calculate the elapsed delta
 310          * (event-)time and add that to the generic event.
 311          *
 312          * Careful, not all hw sign-extends above the physical width
 313          * of the count.
 314          */
 315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 316         delta >>= shift;
 317
 318         local64_add(delta, &event->count);
 319         local64_sub(delta, &hwc->period_left);
 320
 321         return new_raw_count;
 322 }
 323
 324 static atomic_t active_events;
 325 static DEFINE_MUTEX(pmc_reserve_mutex);
 326
 327 #ifdef CONFIG_X86_LOCAL_APIC
 328
 329 static bool reserve_pmc_hardware(void)
 330 {
 331         int i;
 332
 333         for (i = 0; i < x86_pmu.num_counters; i++) {
 334                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 335                         goto perfctr_fail;
 336         }
 337
 338         for (i = 0; i < x86_pmu.num_counters; i++) {
 339                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 340                         goto eventsel_fail;
 341         }
 342
 343         return true;
 344
 345 eventsel_fail:
 346         for (i--; i >= 0; i--)
 347                 release_evntsel_nmi(x86_pmu.eventsel + i);
 348
 349         i = x86_pmu.num_counters;
 350
 351 perfctr_fail:
 352         for (i--; i >= 0; i--)
 353                 release_perfctr_nmi(x86_pmu.perfctr + i);
 354
 355         return false;
 356 }
 357
 358 static void release_pmc_hardware(void)
 359 {
 360         int i;
 361
 362         for (i = 0; i < x86_pmu.num_counters; i++) {
 363                 release_perfctr_nmi(x86_pmu.perfctr + i);
 364                 release_evntsel_nmi(x86_pmu.eventsel + i);
 365         }
 366 }
 367
 368 #else
 369
 370 static bool reserve_pmc_hardware(void) { return true; }
 371 static void release_pmc_hardware(void) {}
 372
 373 #endif
 374
 375 static bool check_hw_exists(void)
 376 {
 377         u64 val, val_new = 0;
 378         int ret = 0;
 379
 380         val = 0xabcdUL;
 381         ret |= checking_wrmsrl(x86_pmu.perfctr, val);
 382         ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new);
 383         if (ret || val != val_new)
 384                 return false;
 385
 386         return true;
 387 }
 388
 389 static void reserve_ds_buffers(void);
 390 static void release_ds_buffers(void);
 391
 392 static void hw_perf_event_destroy(struct perf_event *event)
 393 {
 394         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 395                 release_pmc_hardware();
 396                 release_ds_buffers();
 397                 mutex_unlock(&pmc_reserve_mutex);
 398         }
 399 }
 400
 401 static inline int x86_pmu_initialized(void)
 402 {
 403         return x86_pmu.handle_irq != NULL;
 404 }
 405
 406 static inline int
 407 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 408 {
 409         unsigned int cache_type, cache_op, cache_result;
 410         u64 config, val;
 411
 412         config = attr->config;
 413
 414         cache_type = (config >>  0) & 0xff;
 415         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 416                 return -EINVAL;
 417
 418         cache_op = (config >>  8) & 0xff;
 419         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 420                 return -EINVAL;
 421
 422         cache_result = (config >> 16) & 0xff;
 423         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 424                 return -EINVAL;
 425
 426         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 427
 428         if (val == 0)
 429                 return -ENOENT;
 430
 431         if (val == -1)
 432                 return -EINVAL;
 433
 434         hwc->config |= val;
 435
 436         return 0;
 437 }
 438
 439 static int x86_setup_perfctr(struct perf_event *event)
 440 {
 441         struct perf_event_attr *attr = &event->attr;
 442         struct hw_perf_event *hwc = &event->hw;
 443         u64 config;
 444
 445         if (!is_sampling_event(event)) {
 446                 hwc->sample_period = x86_pmu.max_period;
 447                 hwc->last_period = hwc->sample_period;
 448                 local64_set(&hwc->period_left, hwc->sample_period);
 449         } else {
 450                 /*
 451                  * If we have a PMU initialized but no APIC
 452                  * interrupts, we cannot sample hardware
 453                  * events (user-space has to fall back and
 454                  * sample via a hrtimer based software event):
 455                  */
 456                 if (!x86_pmu.apic)
 457                         return -EOPNOTSUPP;
 458         }
 459
 460         if (attr->type == PERF_TYPE_RAW)
 461                 return 0;
 462
 463         if (attr->type == PERF_TYPE_HW_CACHE)
 464                 return set_ext_hw_attr(hwc, attr);
 465
 466         if (attr->config >= x86_pmu.max_events)
 467                 return -EINVAL;
 468
 469         /*
 470          * The generic map:
 471          */
 472         config = x86_pmu.event_map(attr->config);
 473
 474         if (config == 0)
 475                 return -ENOENT;
 476
 477         if (config == -1LL)
 478                 return -EINVAL;
 479
 480         /*
 481          * Branch tracing:
 482          */
 483         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 484             (hwc->sample_period == 1)) {
 485                 /* BTS is not supported by this architecture. */
 486                 if (!x86_pmu.bts_active)
 487                         return -EOPNOTSUPP;
 488
 489                 /* BTS is currently only allowed for user-mode. */
 490                 if (!attr->exclude_kernel)
 491                         return -EOPNOTSUPP;
 492         }
 493
 494         hwc->config |= config;
 495
 496         return 0;
 497 }
 498
 499 static int x86_pmu_hw_config(struct perf_event *event)
 500 {
 501         if (event->attr.precise_ip) {
 502                 int precise = 0;
 503
 504                 /* Support for constant skid */
 505                 if (x86_pmu.pebs_active) {
 506                         precise++;
 507
 508                         /* Support for IP fixup */
 509                         if (x86_pmu.lbr_nr)
 510                                 precise++;
 511                 }
 512
 513                 if (event->attr.precise_ip > precise)
 514                         return -EOPNOTSUPP;
 515         }
 516
 517         /*
 518          * Generate PMC IRQs:
 519          * (keep 'enabled' bit clear for now)
 520          */
 521         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 522
 523         /*
 524          * Count user and OS events unless requested not to
 525          */
 526         if (!event->attr.exclude_user)
 527                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 528         if (!event->attr.exclude_kernel)
 529                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 530
 531         if (event->attr.type == PERF_TYPE_RAW)
 532                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 533
 534         return x86_setup_perfctr(event);
 535 }
 536
 537 /*
 538  * Setup the hardware configuration for a given attr_type
 539  */
 540 static int __x86_pmu_event_init(struct perf_event *event)
 541 {
 542         int err;
 543
 544         if (!x86_pmu_initialized())
 545                 return -ENODEV;
 546
 547         err = 0;
 548         if (!atomic_inc_not_zero(&active_events)) {
 549                 mutex_lock(&pmc_reserve_mutex);
 550                 if (atomic_read(&active_events) == 0) {
 551                         if (!reserve_pmc_hardware())
 552                                 err = -EBUSY;
 553                         else
 554                                 reserve_ds_buffers();
 555                 }
 556                 if (!err)
 557                         atomic_inc(&active_events);
 558                 mutex_unlock(&pmc_reserve_mutex);
 559         }
 560         if (err)
 561                 return err;
 562
 563         event->destroy = hw_perf_event_destroy;
 564
 565         event->hw.idx = -1;
 566         event->hw.last_cpu = -1;
 567         event->hw.last_tag = ~0ULL;
 568
 569         return x86_pmu.hw_config(event);
 570 }
 571
 572 static void x86_pmu_disable_all(void)
 573 {
 574         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 575         int idx;
 576
 577         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 578                 u64 val;
 579
 580                 if (!test_bit(idx, cpuc->active_mask))
 581                         continue;
 582                 rdmsrl(x86_pmu.eventsel + idx, val);
 583                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 584                         continue;
 585                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 586                 wrmsrl(x86_pmu.eventsel + idx, val);
 587         }
 588 }
 589
 590 static void x86_pmu_disable(struct pmu *pmu)
 591 {
 592         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 593
 594         if (!x86_pmu_initialized())
 595                 return;
 596
 597         if (!cpuc->enabled)
 598                 return;
 599
 600         cpuc->n_added = 0;
 601         cpuc->enabled = 0;
 602         barrier();
 603
 604         x86_pmu.disable_all();
 605 }
 606
 607 static void x86_pmu_enable_all(int added)
 608 {
 609         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 610         int idx;
 611
 612         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 613                 struct perf_event *event = cpuc->events[idx];
 614                 u64 val;
 615
 616                 if (!test_bit(idx, cpuc->active_mask))
 617                         continue;
 618
 619                 val = event->hw.config;
 620                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 621                 wrmsrl(x86_pmu.eventsel + idx, val);
 622         }
 623 }
 624
 625 static struct pmu pmu;
 626
 627 static inline int is_x86_event(struct perf_event *event)
 628 {
 629         return event->pmu == &pmu;
 630 }
 631
 632 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 633 {
 634         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 635         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 636         int i, j, w, wmax, num = 0;
 637         struct hw_perf_event *hwc;
 638
 639         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 640
 641         for (i = 0; i < n; i++) {
 642                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 643                 constraints[i] = c;
 644         }
 645
 646         /*
 647          * fastpath, try to reuse previous register
 648          */
 649         for (i = 0; i < n; i++) {
 650                 hwc = &cpuc->event_list[i]->hw;
 651                 c = constraints[i];
 652
 653                 /* never assigned */
 654                 if (hwc->idx == -1)
 655                         break;
 656
 657                 /* constraint still honored */
 658                 if (!test_bit(hwc->idx, c->idxmsk))
 659                         break;
 660
 661                 /* not already used */
 662                 if (test_bit(hwc->idx, used_mask))
 663                         break;
 664
 665                 __set_bit(hwc->idx, used_mask);
 666                 if (assign)
 667                         assign[i] = hwc->idx;
 668         }
 669         if (i == n)
 670                 goto done;
 671
 672         /*
 673          * begin slow path
 674          */
 675
 676         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 677
 678         /*
 679          * weight = number of possible counters
 680          *
 681          * 1    = most constrained, only works on one counter
 682          * wmax = least constrained, works on any counter
 683          *
 684          * assign events to counters starting with most
 685          * constrained events.
 686          */
 687         wmax = x86_pmu.num_counters;
 688
 689         /*
 690          * when fixed event counters are present,
 691          * wmax is incremented by 1 to account
 692          * for one more choice
 693          */
 694         if (x86_pmu.num_counters_fixed)
 695                 wmax++;
 696
 697         for (w = 1, num = n; num && w <= wmax; w++) {
 698                 /* for each event */
 699                 for (i = 0; num && i < n; i++) {
 700                         c = constraints[i];
 701                         hwc = &cpuc->event_list[i]->hw;
 702
 703                         if (c->weight != w)
 704                                 continue;
 705
 706                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 707                                 if (!test_bit(j, used_mask))
 708                                         break;
 709                         }
 710
 711                         if (j == X86_PMC_IDX_MAX)
 712                                 break;
 713
 714                         __set_bit(j, used_mask);
 715
 716                         if (assign)
 717                                 assign[i] = j;
 718                         num--;
 719                 }
 720         }
 721 done:
 722         /*
 723          * scheduling failed or is just a simulation,
 724          * free resources if necessary
 725          */
 726         if (!assign || num) {
 727                 for (i = 0; i < n; i++) {
 728                         if (x86_pmu.put_event_constraints)
 729                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 730                 }
 731         }
 732         return num ? -ENOSPC : 0;
 733 }
 734
 735 /*
 736  * dogrp: true if must collect siblings events (group)
 737  * returns total number of events and error code
 738  */
 739 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 740 {
 741         struct perf_event *event;
 742         int n, max_count;
 743
 744         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 745
 746         /* current number of events already accepted */
 747         n = cpuc->n_events;
 748
 749         if (is_x86_event(leader)) {
 750                 if (n >= max_count)
 751                         return -ENOSPC;
 752                 cpuc->event_list[n] = leader;
 753                 n++;
 754         }
 755         if (!dogrp)
 756                 return n;
 757
 758         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 759                 if (!is_x86_event(event) ||
 760                     event->state <= PERF_EVENT_STATE_OFF)
 761                         continue;
 762
 763                 if (n >= max_count)
 764                         return -ENOSPC;
 765
 766                 cpuc->event_list[n] = event;
 767                 n++;
 768         }
 769         return n;
 770 }
 771
 772 static inline void x86_assign_hw_event(struct perf_event *event,
 773                                 struct cpu_hw_events *cpuc, int i)
 774 {
 775         struct hw_perf_event *hwc = &event->hw;
 776
 777         hwc->idx = cpuc->assign[i];
 778         hwc->last_cpu = smp_processor_id();
 779         hwc->last_tag = ++cpuc->tags[i];
 780
 781         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 782                 hwc->config_base = 0;
 783                 hwc->event_base = 0;
 784         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 785                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 786                 /*
 787                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 788                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 789                  */
 790                 hwc->event_base =
 791                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 792         } else {
 793                 hwc->config_base = x86_pmu.eventsel;
 794                 hwc->event_base  = x86_pmu.perfctr;
 795         }
 796 }
 797
 798 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 799                                         struct cpu_hw_events *cpuc,
 800                                         int i)
 801 {
 802         return hwc->idx == cpuc->assign[i] &&
 803                 hwc->last_cpu == smp_processor_id() &&
 804                 hwc->last_tag == cpuc->tags[i];
 805 }
 806
 807 static void x86_pmu_start(struct perf_event *event, int flags);
 808 static void x86_pmu_stop(struct perf_event *event, int flags);
 809
 810 static void x86_pmu_enable(struct pmu *pmu)
 811 {
 812         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 813         struct perf_event *event;
 814         struct hw_perf_event *hwc;
 815         int i, added = cpuc->n_added;
 816
 817         if (!x86_pmu_initialized())
 818                 return;
 819
 820         if (cpuc->enabled)
 821                 return;
 822
 823         if (cpuc->n_added) {
 824                 int n_running = cpuc->n_events - cpuc->n_added;
 825                 /*
 826                  * apply assignment obtained either from
 827                  * hw_perf_group_sched_in() or x86_pmu_enable()
 828                  *
 829                  * step1: save events moving to new counters
 830                  * step2: reprogram moved events into new counters
 831                  */
 832                 for (i = 0; i < n_running; i++) {
 833                         event = cpuc->event_list[i];
 834                         hwc = &event->hw;
 835
 836                         /*
 837                          * we can avoid reprogramming counter if:
 838                          * - assigned same counter as last time
 839                          * - running on same CPU as last time
 840                          * - no other event has used the counter since
 841                          */
 842                         if (hwc->idx == -1 ||
 843                             match_prev_assignment(hwc, cpuc, i))
 844                                 continue;
 845
 846                         /*
 847                          * Ensure we don't accidentally enable a stopped
 848                          * counter simply because we rescheduled.
 849                          */
 850                         if (hwc->state & PERF_HES_STOPPED)
 851                                 hwc->state |= PERF_HES_ARCH;
 852
 853                         x86_pmu_stop(event, PERF_EF_UPDATE);
 854                 }
 855
 856                 for (i = 0; i < cpuc->n_events; i++) {
 857                         event = cpuc->event_list[i];
 858                         hwc = &event->hw;
 859
 860                         if (!match_prev_assignment(hwc, cpuc, i))
 861                                 x86_assign_hw_event(event, cpuc, i);
 862                         else if (i < n_running)
 863                                 continue;
 864
 865                         if (hwc->state & PERF_HES_ARCH)
 866                                 continue;
 867
 868                         x86_pmu_start(event, PERF_EF_RELOAD);
 869                 }
 870                 cpuc->n_added = 0;
 871                 perf_events_lapic_init();
 872         }
 873
 874         cpuc->enabled = 1;
 875         barrier();
 876
 877         x86_pmu.enable_all(added);
 878 }
 879
 880 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 881                                           u64 enable_mask)
 882 {
 883         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
 884 }
 885
 886 static inline void x86_pmu_disable_event(struct perf_event *event)
 887 {
 888         struct hw_perf_event *hwc = &event->hw;
 889
 890         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 891 }
 892
 893 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 894
 895 /*
 896  * Set the next IRQ period, based on the hwc->period_left value.
 897  * To be called with the event disabled in hw:
 898  */
 899 static int
 900 x86_perf_event_set_period(struct perf_event *event)
 901 {
 902         struct hw_perf_event *hwc = &event->hw;
 903         s64 left = local64_read(&hwc->period_left);
 904         s64 period = hwc->sample_period;
 905         int ret = 0, idx = hwc->idx;
 906
 907         if (idx == X86_PMC_IDX_FIXED_BTS)
 908                 return 0;
 909
 910         /*
 911          * If we are way outside a reasonable range then just skip forward:
 912          */
 913         if (unlikely(left <= -period)) {
 914                 left = period;
 915                 local64_set(&hwc->period_left, left);
 916                 hwc->last_period = period;
 917                 ret = 1;
 918         }
 919
 920         if (unlikely(left <= 0)) {
 921                 left += period;
 922                 local64_set(&hwc->period_left, left);
 923                 hwc->last_period = period;
 924                 ret = 1;
 925         }
 926         /*
 927          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 928          */
 929         if (unlikely(left < 2))
 930                 left = 2;
 931
 932         if (left > x86_pmu.max_period)
 933                 left = x86_pmu.max_period;
 934
 935         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 936
 937         /*
 938          * The hw event starts counting from this event offset,
 939          * mark it to be able to extra future deltas:
 940          */
 941         local64_set(&hwc->prev_count, (u64)-left);
 942
 943         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
 944
 945         /*
 946          * Due to erratum on certan cpu we need
 947          * a second write to be sure the register
 948          * is updated properly
 949          */
 950         if (x86_pmu.perfctr_second_write) {
 951                 wrmsrl(hwc->event_base + idx,
 952                         (u64)(-left) & x86_pmu.cntval_mask);
 953         }
 954
 955         perf_event_update_userpage(event);
 956
 957         return ret;
 958 }
 959
 960 static void x86_pmu_enable_event(struct perf_event *event)
 961 {
 962         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 963         if (cpuc->enabled)
 964                 __x86_pmu_enable_event(&event->hw,
 965                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 966 }
 967
 968 /*
 969  * Add a single event to the PMU.
 970  *
 971  * The event is added to the group of enabled events
 972  * but only if it can be scehduled with existing events.
 973  */
 974 static int x86_pmu_add(struct perf_event *event, int flags)
 975 {
 976         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 977         struct hw_perf_event *hwc;
 978         int assign[X86_PMC_IDX_MAX];
 979         int n, n0, ret;
 980
 981         hwc = &event->hw;
 982
 983         perf_pmu_disable(event->pmu);
 984         n0 = cpuc->n_events;
 985         ret = n = collect_events(cpuc, event, false);
 986         if (ret < 0)
 987                 goto out;
 988
 989         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 990         if (!(flags & PERF_EF_START))
 991                 hwc->state |= PERF_HES_ARCH;
 992
 993         /*
 994          * If group events scheduling transaction was started,
 995          * skip the schedulability test here, it will be peformed
 996          * at commit time (->commit_txn) as a whole
 997          */
 998         if (cpuc->group_flag & PERF_EVENT_TXN)
 999                 goto done_collect;
1000
1001         ret = x86_pmu.schedule_events(cpuc, n, assign);
1002         if (ret)
1003                 goto out;
1004         /*
1005          * copy new assignment, now we know it is possible
1006          * will be used by hw_perf_enable()
1007          */
1008         memcpy(cpuc->assign, assign, n*sizeof(int));
1009
1010 done_collect:
1011         cpuc->n_events = n;
1012         cpuc->n_added += n - n0;
1013         cpuc->n_txn += n - n0;
1014
1015         ret = 0;
1016 out:
1017         perf_pmu_enable(event->pmu);
1018         return ret;
1019 }
1020
1021 static void x86_pmu_start(struct perf_event *event, int flags)
1022 {
1023         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1024         int idx = event->hw.idx;
1025
1026         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1027                 return;
1028
1029         if (WARN_ON_ONCE(idx == -1))
1030                 return;
1031
1032         if (flags & PERF_EF_RELOAD) {
1033                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1034                 x86_perf_event_set_period(event);
1035         }
1036
1037         event->hw.state = 0;
1038
1039         cpuc->events[idx] = event;
1040         __set_bit(idx, cpuc->active_mask);
1041         __set_bit(idx, cpuc->running);
1042         x86_pmu.enable(event);
1043         perf_event_update_userpage(event);
1044 }
1045
1046 void perf_event_print_debug(void)
1047 {
1048         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1049         u64 pebs;
1050         struct cpu_hw_events *cpuc;
1051         unsigned long flags;
1052         int cpu, idx;
1053
1054         if (!x86_pmu.num_counters)
1055                 return;
1056
1057         local_irq_save(flags);
1058
1059         cpu = smp_processor_id();
1060         cpuc = &per_cpu(cpu_hw_events, cpu);
1061
1062         if (x86_pmu.version >= 2) {
1063                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1064                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1065                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1066                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1067                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1068
1069                 pr_info("\n");
1070                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1071                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1072                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1073                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1074                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1075         }
1076         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1077
1078         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1079                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1080                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1081
1082                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1083
1084                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1085                         cpu, idx, pmc_ctrl);
1086                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1087                         cpu, idx, pmc_count);
1088                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1089                         cpu, idx, prev_left);
1090         }
1091         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1092                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1093
1094                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1095                         cpu, idx, pmc_count);
1096         }
1097         local_irq_restore(flags);
1098 }
1099
1100 static void x86_pmu_stop(struct perf_event *event, int flags)
1101 {
1102         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1103         struct hw_perf_event *hwc = &event->hw;
1104
1105         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1106                 x86_pmu.disable(event);
1107                 cpuc->events[hwc->idx] = NULL;
1108                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1109                 hwc->state |= PERF_HES_STOPPED;
1110         }
1111
1112         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1113                 /*
1114                  * Drain the remaining delta count out of a event
1115                  * that we are disabling:
1116                  */
1117                 x86_perf_event_update(event);
1118                 hwc->state |= PERF_HES_UPTODATE;
1119         }
1120 }
1121
1122 static void x86_pmu_del(struct perf_event *event, int flags)
1123 {
1124         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1125         int i;
1126
1127         /*
1128          * If we're called during a txn, we don't need to do anything.
1129          * The events never got scheduled and ->cancel_txn will truncate
1130          * the event_list.
1131          */
1132         if (cpuc->group_flag & PERF_EVENT_TXN)
1133                 return;
1134
1135         x86_pmu_stop(event, PERF_EF_UPDATE);
1136
1137         for (i = 0; i < cpuc->n_events; i++) {
1138                 if (event == cpuc->event_list[i]) {
1139
1140                         if (x86_pmu.put_event_constraints)
1141                                 x86_pmu.put_event_constraints(cpuc, event);
1142
1143                         while (++i < cpuc->n_events)
1144                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1145
1146                         --cpuc->n_events;
1147                         break;
1148                 }
1149         }
1150         perf_event_update_userpage(event);
1151 }
1152
1153 static int x86_pmu_handle_irq(struct pt_regs *regs)
1154 {
1155         struct perf_sample_data data;
1156         struct cpu_hw_events *cpuc;
1157         struct perf_event *event;
1158         int idx, handled = 0;
1159         u64 val;
1160
1161         perf_sample_data_init(&data, 0);
1162
1163         cpuc = &__get_cpu_var(cpu_hw_events);
1164
1165         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1166                 if (!test_bit(idx, cpuc->active_mask)) {
1167                         /*
1168                          * Though we deactivated the counter some cpus
1169                          * might still deliver spurious interrupts still
1170                          * in flight. Catch them:
1171                          */
1172                         if (__test_and_clear_bit(idx, cpuc->running))
1173                                 handled++;
1174                         continue;
1175                 }
1176
1177                 event = cpuc->events[idx];
1178
1179                 val = x86_perf_event_update(event);
1180                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1181                         continue;
1182
1183                 /*
1184                  * event overflow
1185                  */
1186                 handled++;
1187                 data.period     = event->hw.last_period;
1188
1189                 if (!x86_perf_event_set_period(event))
1190                         continue;
1191
1192                 if (perf_event_overflow(event, 1, &data, regs))
1193                         x86_pmu_stop(event, 0);
1194         }
1195
1196         if (handled)
1197                 inc_irq_stat(apic_perf_irqs);
1198
1199         return handled;
1200 }
1201
1202 void perf_events_lapic_init(void)
1203 {
1204         if (!x86_pmu.apic || !x86_pmu_initialized())
1205                 return;
1206
1207         /*
1208          * Always use NMI for PMU
1209          */
1210         apic_write(APIC_LVTPC, APIC_DM_NMI);
1211 }
1212
1213 struct pmu_nmi_state {
1214         unsigned int    marked;
1215         int             handled;
1216 };
1217
1218 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1219
1220 static int __kprobes
1221 perf_event_nmi_handler(struct notifier_block *self,
1222                          unsigned long cmd, void *__args)
1223 {
1224         struct die_args *args = __args;
1225         unsigned int this_nmi;
1226         int handled;
1227
1228         if (!atomic_read(&active_events))
1229                 return NOTIFY_DONE;
1230
1231         switch (cmd) {
1232         case DIE_NMI:
1233         case DIE_NMI_IPI:
1234                 break;
1235         case DIE_NMIUNKNOWN:
1236                 this_nmi = percpu_read(irq_stat.__nmi_count);
1237                 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1238                         /* let the kernel handle the unknown nmi */
1239                         return NOTIFY_DONE;
1240                 /*
1241                  * This one is a PMU back-to-back nmi. Two events
1242                  * trigger 'simultaneously' raising two back-to-back
1243                  * NMIs. If the first NMI handles both, the latter
1244                  * will be empty and daze the CPU. So, we drop it to
1245                  * avoid false-positive 'unknown nmi' messages.
1246                  */
1247                 return NOTIFY_STOP;
1248         default:
1249                 return NOTIFY_DONE;
1250         }
1251
1252         apic_write(APIC_LVTPC, APIC_DM_NMI);
1253
1254         handled = x86_pmu.handle_irq(args->regs);
1255         if (!handled)
1256                 return NOTIFY_DONE;
1257
1258         this_nmi = percpu_read(irq_stat.__nmi_count);
1259         if ((handled > 1) ||
1260                 /* the next nmi could be a back-to-back nmi */
1261             ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1262              (__get_cpu_var(pmu_nmi).handled > 1))) {
1263                 /*
1264                  * We could have two subsequent back-to-back nmis: The
1265                  * first handles more than one counter, the 2nd
1266                  * handles only one counter and the 3rd handles no
1267                  * counter.
1268                  *
1269                  * This is the 2nd nmi because the previous was
1270                  * handling more than one counter. We will mark the
1271                  * next (3rd) and then drop it if unhandled.
1272                  */
1273                 __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
1274                 __get_cpu_var(pmu_nmi).handled  = handled;
1275         }
1276
1277         return NOTIFY_STOP;
1278 }
1279
1280 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1281         .notifier_call          = perf_event_nmi_handler,
1282         .next                   = NULL,
1283         .priority               = 1
1284 };
1285
1286 static struct event_constraint unconstrained;
1287 static struct event_constraint emptyconstraint;
1288
1289 static struct event_constraint *
1290 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1291 {
1292         struct event_constraint *c;
1293
1294         if (x86_pmu.event_constraints) {
1295                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1296                         if ((event->hw.config & c->cmask) == c->code)
1297                                 return c;
1298                 }
1299         }
1300
1301         return &unconstrained;
1302 }
1303
1304 #include "perf_event_amd.c"
1305 #include "perf_event_p6.c"
1306 #include "perf_event_p4.c"
1307 #include "perf_event_intel_lbr.c"
1308 #include "perf_event_intel_ds.c"
1309 #include "perf_event_intel.c"
1310
1311 static int __cpuinit
1312 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1313 {
1314         unsigned int cpu = (long)hcpu;
1315         int ret = NOTIFY_OK;
1316
1317         switch (action & ~CPU_TASKS_FROZEN) {
1318         case CPU_UP_PREPARE:
1319                 if (x86_pmu.cpu_prepare)
1320                         ret = x86_pmu.cpu_prepare(cpu);
1321                 break;
1322
1323         case CPU_STARTING:
1324                 if (x86_pmu.cpu_starting)
1325                         x86_pmu.cpu_starting(cpu);
1326                 break;
1327
1328         case CPU_DYING:
1329                 if (x86_pmu.cpu_dying)
1330                         x86_pmu.cpu_dying(cpu);
1331                 break;
1332
1333         case CPU_UP_CANCELED:
1334         case CPU_DEAD:
1335                 if (x86_pmu.cpu_dead)
1336                         x86_pmu.cpu_dead(cpu);
1337                 break;
1338
1339         default:
1340                 break;
1341         }
1342
1343         return ret;
1344 }
1345
1346 static void __init pmu_check_apic(void)
1347 {
1348         if (cpu_has_apic)
1349                 return;
1350
1351         x86_pmu.apic = 0;
1352         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1353         pr_info("no hardware sampling interrupt available.\n");
1354 }
1355
1356 int __init init_hw_perf_events(void)
1357 {
1358         struct event_constraint *c;
1359         int err;
1360
1361         pr_info("Performance Events: ");
1362
1363         switch (boot_cpu_data.x86_vendor) {
1364         case X86_VENDOR_INTEL:
1365                 err = intel_pmu_init();
1366                 break;
1367         case X86_VENDOR_AMD:
1368                 err = amd_pmu_init();
1369                 break;
1370         default:
1371                 return 0;
1372         }
1373         if (err != 0) {
1374                 pr_cont("no PMU driver, software events only.\n");
1375                 return 0;
1376         }
1377
1378         pmu_check_apic();
1379
1380         /* sanity check that the hardware exists or is emulated */
1381         if (!check_hw_exists()) {
1382                 pr_cont("Broken PMU hardware detected, software events only.\n");
1383                 return 0;
1384         }
1385
1386         pr_cont("%s PMU driver.\n", x86_pmu.name);
1387
1388         if (x86_pmu.quirks)
1389                 x86_pmu.quirks();
1390
1391         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1392                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1393                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1394                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1395         }
1396         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1397
1398         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1399                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1400                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1401                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1402         }
1403
1404         x86_pmu.intel_ctrl |=
1405                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1406
1407         perf_events_lapic_init();
1408         register_die_notifier(&perf_event_nmi_notifier);
1409
1410         unconstrained = (struct event_constraint)
1411                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1412                                    0, x86_pmu.num_counters);
1413
1414         if (x86_pmu.event_constraints) {
1415                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1416                         if (c->cmask != X86_RAW_EVENT_MASK)
1417                                 continue;
1418
1419                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1420                         c->weight += x86_pmu.num_counters;
1421                 }
1422         }
1423
1424         pr_info("... version:                %d\n",     x86_pmu.version);
1425         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1426         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1427         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1428         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1429         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1430         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1431
1432         perf_pmu_register(&pmu);
1433         perf_cpu_notifier(x86_pmu_notifier);
1434
1435         return 0;
1436 }
1437 early_initcall(init_hw_perf_events);
1438
1439 static inline void x86_pmu_read(struct perf_event *event)
1440 {
1441         x86_perf_event_update(event);
1442 }
1443
1444 /*
1445  * Start group events scheduling transaction
1446  * Set the flag to make pmu::enable() not perform the
1447  * schedulability test, it will be performed at commit time
1448  */
1449 static void x86_pmu_start_txn(struct pmu *pmu)
1450 {
1451         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1452
1453         perf_pmu_disable(pmu);
1454         cpuc->group_flag |= PERF_EVENT_TXN;
1455         cpuc->n_txn = 0;
1456 }
1457
1458 /*
1459  * Stop group events scheduling transaction
1460  * Clear the flag and pmu::enable() will perform the
1461  * schedulability test.
1462  */
1463 static void x86_pmu_cancel_txn(struct pmu *pmu)
1464 {
1465         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1466
1467         cpuc->group_flag &= ~PERF_EVENT_TXN;
1468         /*
1469          * Truncate the collected events.
1470          */
1471         cpuc->n_added -= cpuc->n_txn;
1472         cpuc->n_events -= cpuc->n_txn;
1473         perf_pmu_enable(pmu);
1474 }
1475
1476 /*
1477  * Commit group events scheduling transaction
1478  * Perform the group schedulability test as a whole
1479  * Return 0 if success
1480  */
1481 static int x86_pmu_commit_txn(struct pmu *pmu)
1482 {
1483         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1484         int assign[X86_PMC_IDX_MAX];
1485         int n, ret;
1486
1487         n = cpuc->n_events;
1488
1489         if (!x86_pmu_initialized())
1490                 return -EAGAIN;
1491
1492         ret = x86_pmu.schedule_events(cpuc, n, assign);
1493         if (ret)
1494                 return ret;
1495
1496         /*
1497          * copy new assignment, now we know it is possible
1498          * will be used by hw_perf_enable()
1499          */
1500         memcpy(cpuc->assign, assign, n*sizeof(int));
1501
1502         cpuc->group_flag &= ~PERF_EVENT_TXN;
1503         perf_pmu_enable(pmu);
1504         return 0;
1505 }
1506
1507 /*
1508  * validate that we can schedule this event
1509  */
1510 static int validate_event(struct perf_event *event)
1511 {
1512         struct cpu_hw_events *fake_cpuc;
1513         struct event_constraint *c;
1514         int ret = 0;
1515
1516         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1517         if (!fake_cpuc)
1518                 return -ENOMEM;
1519
1520         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1521
1522         if (!c || !c->weight)
1523                 ret = -ENOSPC;
1524
1525         if (x86_pmu.put_event_constraints)
1526                 x86_pmu.put_event_constraints(fake_cpuc, event);
1527
1528         kfree(fake_cpuc);
1529
1530         return ret;
1531 }
1532
1533 /*
1534  * validate a single event group
1535  *
1536  * validation include:
1537  *      - check events are compatible which each other
1538  *      - events do not compete for the same counter
1539  *      - number of events <= number of counters
1540  *
1541  * validation ensures the group can be loaded onto the
1542  * PMU if it was the only group available.
1543  */
1544 static int validate_group(struct perf_event *event)
1545 {
1546         struct perf_event *leader = event->group_leader;
1547         struct cpu_hw_events *fake_cpuc;
1548         int ret, n;
1549
1550         ret = -ENOMEM;
1551         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1552         if (!fake_cpuc)
1553                 goto out;
1554
1555         /*
1556          * the event is not yet connected with its
1557          * siblings therefore we must first collect
1558          * existing siblings, then add the new event
1559          * before we can simulate the scheduling
1560          */
1561         ret = -ENOSPC;
1562         n = collect_events(fake_cpuc, leader, true);
1563         if (n < 0)
1564                 goto out_free;
1565
1566         fake_cpuc->n_events = n;
1567         n = collect_events(fake_cpuc, event, false);
1568         if (n < 0)
1569                 goto out_free;
1570
1571         fake_cpuc->n_events = n;
1572
1573         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1574
1575 out_free:
1576         kfree(fake_cpuc);
1577 out:
1578         return ret;
1579 }
1580
1581 int x86_pmu_event_init(struct perf_event *event)
1582 {
1583         struct pmu *tmp;
1584         int err;
1585
1586         switch (event->attr.type) {
1587         case PERF_TYPE_RAW:
1588         case PERF_TYPE_HARDWARE:
1589         case PERF_TYPE_HW_CACHE:
1590                 break;
1591
1592         default:
1593                 return -ENOENT;
1594         }
1595
1596         err = __x86_pmu_event_init(event);
1597         if (!err) {
1598                 /*
1599                  * we temporarily connect event to its pmu
1600                  * such that validate_group() can classify
1601                  * it as an x86 event using is_x86_event()
1602                  */
1603                 tmp = event->pmu;
1604                 event->pmu = &pmu;
1605
1606                 if (event->group_leader != event)
1607                         err = validate_group(event);
1608                 else
1609                         err = validate_event(event);
1610
1611                 event->pmu = tmp;
1612         }
1613         if (err) {
1614                 if (event->destroy)
1615                         event->destroy(event);
1616         }
1617
1618         return err;
1619 }
1620
1621 static struct pmu pmu = {
1622         .pmu_enable     = x86_pmu_enable,
1623         .pmu_disable    = x86_pmu_disable,
1624
1625         .event_init     = x86_pmu_event_init,
1626
1627         .add            = x86_pmu_add,
1628         .del            = x86_pmu_del,
1629         .start          = x86_pmu_start,
1630         .stop           = x86_pmu_stop,
1631         .read           = x86_pmu_read,
1632
1633         .start_txn      = x86_pmu_start_txn,
1634         .cancel_txn     = x86_pmu_cancel_txn,
1635         .commit_txn     = x86_pmu_commit_txn,
1636 };
1637
1638 /*
1639  * callchain support
1640  */
1641
1642 static void
1643 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1644 {
1645         /* Ignore warnings */
1646 }
1647
1648 static void backtrace_warning(void *data, char *msg)
1649 {
1650         /* Ignore warnings */
1651 }
1652
1653 static int backtrace_stack(void *data, char *name)
1654 {
1655         return 0;
1656 }
1657
1658 static void backtrace_address(void *data, unsigned long addr, int reliable)
1659 {
1660         struct perf_callchain_entry *entry = data;
1661
1662         perf_callchain_store(entry, addr);
1663 }
1664
1665 static const struct stacktrace_ops backtrace_ops = {
1666         .warning                = backtrace_warning,
1667         .warning_symbol         = backtrace_warning_symbol,
1668         .stack                  = backtrace_stack,
1669         .address                = backtrace_address,
1670         .walk_stack             = print_context_stack_bp,
1671 };
1672
1673 void
1674 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1675 {
1676         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1677                 /* TODO: We don't support guest os callchain now */
1678                 return;
1679         }
1680
1681         perf_callchain_store(entry, regs->ip);
1682
1683         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1684 }
1685
1686 #ifdef CONFIG_COMPAT
1687 static inline int
1688 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1689 {
1690         /* 32-bit process in 64-bit kernel. */
1691         struct stack_frame_ia32 frame;
1692         const void __user *fp;
1693
1694         if (!test_thread_flag(TIF_IA32))
1695                 return 0;
1696
1697         fp = compat_ptr(regs->bp);
1698         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1699                 unsigned long bytes;
1700                 frame.next_frame     = 0;
1701                 frame.return_address = 0;
1702
1703                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1704                 if (bytes != sizeof(frame))
1705                         break;
1706
1707                 if (fp < compat_ptr(regs->sp))
1708                         break;
1709
1710                 perf_callchain_store(entry, frame.return_address);
1711                 fp = compat_ptr(frame.next_frame);
1712         }
1713         return 1;
1714 }
1715 #else
1716 static inline int
1717 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1718 {
1719     return 0;
1720 }
1721 #endif
1722
1723 void
1724 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1725 {
1726         struct stack_frame frame;
1727         const void __user *fp;
1728
1729         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1730                 /* TODO: We don't support guest os callchain now */
1731                 return;
1732         }
1733
1734         fp = (void __user *)regs->bp;
1735
1736         perf_callchain_store(entry, regs->ip);
1737
1738         if (perf_callchain_user32(regs, entry))
1739                 return;
1740
1741         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1742                 unsigned long bytes;
1743                 frame.next_frame             = NULL;
1744                 frame.return_address = 0;
1745
1746                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1747                 if (bytes != sizeof(frame))
1748                         break;
1749
1750                 if ((unsigned long)fp < regs->sp)
1751                         break;
1752
1753                 perf_callchain_store(entry, frame.return_address);
1754                 fp = frame.next_frame;
1755         }
1756 }
1757
1758 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1759 {
1760         unsigned long ip;
1761
1762         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1763                 ip = perf_guest_cbs->get_guest_ip();
1764         else
1765                 ip = instruction_pointer(regs);
1766
1767         return ip;
1768 }
1769
1770 unsigned long perf_misc_flags(struct pt_regs *regs)
1771 {
1772         int misc = 0;
1773
1774         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1775                 if (perf_guest_cbs->is_user_mode())
1776                         misc |= PERF_RECORD_MISC_GUEST_USER;
1777                 else
1778                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1779         } else {
1780                 if (user_mode(regs))
1781                         misc |= PERF_RECORD_MISC_USER;
1782                 else
1783                         misc |= PERF_RECORD_MISC_KERNEL;
1784         }
1785
1786         if (regs->flags & PERF_EFLAGS_EXACT)
1787                 misc |= PERF_RECORD_MISC_EXACT_IP;
1788
1789         return misc;
1790 }