arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33 #include <asm/smp.h>
  34 #include <asm/alternative.h>
  35
  36 #if 0
  37 #undef wrmsrl
  38 #define wrmsrl(msr, val)                                        \
  39 do {                                                            \
  40         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  41                         (unsigned long)(val));                  \
  42         native_write_msr((msr), (u32)((u64)(val)),              \
  43                         (u32)((u64)(val) >> 32));               \
  44 } while (0)
  45 #endif
  46
  47 /*
  48  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  49  */
  50 static unsigned long
  51 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  52 {
  53         unsigned long offset, addr = (unsigned long)from;
  54         unsigned long size, len = 0;
  55         struct page *page;
  56         void *map;
  57         int ret;
  58
  59         do {
  60                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  61                 if (!ret)
  62                         break;
  63
  64                 offset = addr & (PAGE_SIZE - 1);
  65                 size = min(PAGE_SIZE - offset, n - len);
  66
  67                 map = kmap_atomic(page);
  68                 memcpy(to, map+offset, size);
  69                 kunmap_atomic(map);
  70                 put_page(page);
  71
  72                 len  += size;
  73                 to   += size;
  74                 addr += size;
  75
  76         } while (len < n);
  77
  78         return len;
  79 }
  80
  81 struct event_constraint {
  82         union {
  83                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  84                 u64             idxmsk64;
  85         };
  86         u64     code;
  87         u64     cmask;
  88         int     weight;
  89 };
  90
  91 struct amd_nb {
  92         int nb_id;  /* NorthBridge id */
  93         int refcnt; /* reference count */
  94         struct perf_event *owners[X86_PMC_IDX_MAX];
  95         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  96 };
  97
  98 struct intel_percore;
  99
 100 #define MAX_LBR_ENTRIES         16
 101
 102 struct cpu_hw_events {
 103         /*
 104          * Generic x86 PMC bits
 105          */
 106         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 107         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 108         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 109         int                     enabled;
 110
 111         int                     n_events;
 112         int                     n_added;
 113         int                     n_txn;
 114         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 115         u64                     tags[X86_PMC_IDX_MAX];
 116         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 117
 118         unsigned int            group_flag;
 119
 120         /*
 121          * Intel DebugStore bits
 122          */
 123         struct debug_store      *ds;
 124         u64                     pebs_enabled;
 125
 126         /*
 127          * Intel LBR bits
 128          */
 129         int                             lbr_users;
 130         void                            *lbr_context;
 131         struct perf_branch_stack        lbr_stack;
 132         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 133
 134         /*
 135          * Intel percore register state.
 136          * Coordinate shared resources between HT threads.
 137          */
 138         int                             percore_used; /* Used by this CPU? */
 139         struct intel_percore            *per_core;
 140
 141         /*
 142          * AMD specific bits
 143          */
 144         struct amd_nb           *amd_nb;
 145 };
 146
 147 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 148         { .idxmsk64 = (n) },            \
 149         .code = (c),                    \
 150         .cmask = (m),                   \
 151         .weight = (w),                  \
 152 }
 153
 154 #define EVENT_CONSTRAINT(c, n, m)       \
 155         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 156
 157 /*
 158  * Constraint on the Event code.
 159  */
 160 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 161         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 162
 163 /*
 164  * Constraint on the Event code + UMask + fixed-mask
 165  *
 166  * filter mask to validate fixed counter events.
 167  * the following filters disqualify for fixed counters:
 168  *  - inv
 169  *  - edge
 170  *  - cnt-mask
 171  *  The other filters are supported by fixed counters.
 172  *  The any-thread option is supported starting with v3.
 173  */
 174 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 175         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 176
 177 /*
 178  * Constraint on the Event code + UMask
 179  */
 180 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 181         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 182
 183 #define EVENT_CONSTRAINT_END            \
 184         EVENT_CONSTRAINT(0, 0, 0)
 185
 186 #define for_each_event_constraint(e, c) \
 187         for ((e) = (c); (e)->weight; (e)++)
 188
 189 /*
 190  * Extra registers for specific events.
 191  * Some events need large masks and require external MSRs.
 192  * Define a mapping to these extra registers.
 193  */
 194 struct extra_reg {
 195         unsigned int            event;
 196         unsigned int            msr;
 197         u64                     config_mask;
 198         u64                     valid_mask;
 199 };
 200
 201 #define EVENT_EXTRA_REG(e, ms, m, vm) { \
 202         .event = (e),           \
 203         .msr = (ms),            \
 204         .config_mask = (m),     \
 205         .valid_mask = (vm),     \
 206         }
 207 #define INTEL_EVENT_EXTRA_REG(event, msr, vm)   \
 208         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
 209 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
 210
 211 union perf_capabilities {
 212         struct {
 213                 u64     lbr_format    : 6;
 214                 u64     pebs_trap     : 1;
 215                 u64     pebs_arch_reg : 1;
 216                 u64     pebs_format   : 4;
 217                 u64     smm_freeze    : 1;
 218         };
 219         u64     capabilities;
 220 };
 221
 222 /*
 223  * struct x86_pmu - generic x86 pmu
 224  */
 225 struct x86_pmu {
 226         /*
 227          * Generic x86 PMC bits
 228          */
 229         const char      *name;
 230         int             version;
 231         int             (*handle_irq)(struct pt_regs *);
 232         void            (*disable_all)(void);
 233         void            (*enable_all)(int added);
 234         void            (*enable)(struct perf_event *);
 235         void            (*disable)(struct perf_event *);
 236         void            (*hw_watchdog_set_attr)(struct perf_event_attr *attr);
 237         int             (*hw_config)(struct perf_event *event);
 238         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 239         unsigned        eventsel;
 240         unsigned        perfctr;
 241         u64             (*event_map)(int);
 242         int             max_events;
 243         int             num_counters;
 244         int             num_counters_fixed;
 245         int             cntval_bits;
 246         u64             cntval_mask;
 247         int             apic;
 248         u64             max_period;
 249         struct event_constraint *
 250                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 251                                                  struct perf_event *event);
 252
 253         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 254                                                  struct perf_event *event);
 255         struct event_constraint *event_constraints;
 256         struct event_constraint *percore_constraints;
 257         void            (*quirks)(void);
 258         int             perfctr_second_write;
 259
 260         int             (*cpu_prepare)(int cpu);
 261         void            (*cpu_starting)(int cpu);
 262         void            (*cpu_dying)(int cpu);
 263         void            (*cpu_dead)(int cpu);
 264
 265         /*
 266          * Intel Arch Perfmon v2+
 267          */
 268         u64                     intel_ctrl;
 269         union perf_capabilities intel_cap;
 270
 271         /*
 272          * Intel DebugStore bits
 273          */
 274         int             bts, pebs;
 275         int             bts_active, pebs_active;
 276         int             pebs_record_size;
 277         void            (*drain_pebs)(struct pt_regs *regs);
 278         struct event_constraint *pebs_constraints;
 279
 280         /*
 281          * Intel LBR
 282          */
 283         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 284         int             lbr_nr;                    /* hardware stack size */
 285
 286         /*
 287          * Extra registers for events
 288          */
 289         struct extra_reg *extra_regs;
 290 };
 291
 292 static struct x86_pmu x86_pmu __read_mostly;
 293
 294 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 295         .enabled = 1,
 296 };
 297
 298 static int x86_perf_event_set_period(struct perf_event *event);
 299
 300 /*
 301  * Generalized hw caching related hw_event table, filled
 302  * in on a per model basis. A value of 0 means
 303  * 'not supported', -1 means 'hw_event makes no sense on
 304  * this CPU', any other value means the raw hw_event
 305  * ID.
 306  */
 307
 308 #define C(x) PERF_COUNT_HW_CACHE_##x
 309
 310 static u64 __read_mostly hw_cache_event_ids
 311                                 [PERF_COUNT_HW_CACHE_MAX]
 312                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 313                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 314 static u64 __read_mostly hw_cache_extra_regs
 315                                 [PERF_COUNT_HW_CACHE_MAX]
 316                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 317                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 318
 319 void hw_nmi_watchdog_set_attr(struct perf_event_attr *wd_attr)
 320 {
 321         if (x86_pmu.hw_watchdog_set_attr)
 322                 x86_pmu.hw_watchdog_set_attr(wd_attr);
 323 }
 324
 325 /*
 326  * Propagate event elapsed time into the generic event.
 327  * Can only be executed on the CPU where the event is active.
 328  * Returns the delta events processed.
 329  */
 330 static u64
 331 x86_perf_event_update(struct perf_event *event)
 332 {
 333         struct hw_perf_event *hwc = &event->hw;
 334         int shift = 64 - x86_pmu.cntval_bits;
 335         u64 prev_raw_count, new_raw_count;
 336         int idx = hwc->idx;
 337         s64 delta;
 338
 339         if (idx == X86_PMC_IDX_FIXED_BTS)
 340                 return 0;
 341
 342         /*
 343          * Careful: an NMI might modify the previous event value.
 344          *
 345          * Our tactic to handle this is to first atomically read and
 346          * exchange a new raw count - then add that new-prev delta
 347          * count to the generic event atomically:
 348          */
 349 again:
 350         prev_raw_count = local64_read(&hwc->prev_count);
 351         rdmsrl(hwc->event_base, new_raw_count);
 352
 353         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 354                                         new_raw_count) != prev_raw_count)
 355                 goto again;
 356
 357         /*
 358          * Now we have the new raw value and have updated the prev
 359          * timestamp already. We can now calculate the elapsed delta
 360          * (event-)time and add that to the generic event.
 361          *
 362          * Careful, not all hw sign-extends above the physical width
 363          * of the count.
 364          */
 365         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 366         delta >>= shift;
 367
 368         local64_add(delta, &event->count);
 369         local64_sub(delta, &hwc->period_left);
 370
 371         return new_raw_count;
 372 }
 373
 374 static inline int x86_pmu_addr_offset(int index)
 375 {
 376         int offset;
 377
 378         /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
 379         alternative_io(ASM_NOP2,
 380                        "shll $1, %%eax",
 381                        X86_FEATURE_PERFCTR_CORE,
 382                        "=a" (offset),
 383                        "a"  (index));
 384
 385         return offset;
 386 }
 387
 388 static inline unsigned int x86_pmu_config_addr(int index)
 389 {
 390         return x86_pmu.eventsel + x86_pmu_addr_offset(index);
 391 }
 392
 393 static inline unsigned int x86_pmu_event_addr(int index)
 394 {
 395         return x86_pmu.perfctr + x86_pmu_addr_offset(index);
 396 }
 397
 398 /*
 399  * Find and validate any extra registers to set up.
 400  */
 401 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 402 {
 403         struct extra_reg *er;
 404
 405         event->hw.extra_reg = 0;
 406         event->hw.extra_config = 0;
 407
 408         if (!x86_pmu.extra_regs)
 409                 return 0;
 410
 411         for (er = x86_pmu.extra_regs; er->msr; er++) {
 412                 if (er->event != (config & er->config_mask))
 413                         continue;
 414                 if (event->attr.config1 & ~er->valid_mask)
 415                         return -EINVAL;
 416                 event->hw.extra_reg = er->msr;
 417                 event->hw.extra_config = event->attr.config1;
 418                 break;
 419         }
 420         return 0;
 421 }
 422
 423 static atomic_t active_events;
 424 static DEFINE_MUTEX(pmc_reserve_mutex);
 425
 426 #ifdef CONFIG_X86_LOCAL_APIC
 427
 428 static bool reserve_pmc_hardware(void)
 429 {
 430         int i;
 431
 432         for (i = 0; i < x86_pmu.num_counters; i++) {
 433                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 434                         goto perfctr_fail;
 435         }
 436
 437         for (i = 0; i < x86_pmu.num_counters; i++) {
 438                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 439                         goto eventsel_fail;
 440         }
 441
 442         return true;
 443
 444 eventsel_fail:
 445         for (i--; i >= 0; i--)
 446                 release_evntsel_nmi(x86_pmu_config_addr(i));
 447
 448         i = x86_pmu.num_counters;
 449
 450 perfctr_fail:
 451         for (i--; i >= 0; i--)
 452                 release_perfctr_nmi(x86_pmu_event_addr(i));
 453
 454         return false;
 455 }
 456
 457 static void release_pmc_hardware(void)
 458 {
 459         int i;
 460
 461         for (i = 0; i < x86_pmu.num_counters; i++) {
 462                 release_perfctr_nmi(x86_pmu_event_addr(i));
 463                 release_evntsel_nmi(x86_pmu_config_addr(i));
 464         }
 465 }
 466
 467 #else
 468
 469 static bool reserve_pmc_hardware(void) { return true; }
 470 static void release_pmc_hardware(void) {}
 471
 472 #endif
 473
 474 static bool check_hw_exists(void)
 475 {
 476         u64 val, val_new = 0;
 477         int i, reg, ret = 0;
 478
 479         /*
 480          * Check to see if the BIOS enabled any of the counters, if so
 481          * complain and bail.
 482          */
 483         for (i = 0; i < x86_pmu.num_counters; i++) {
 484                 reg = x86_pmu_config_addr(i);
 485                 ret = rdmsrl_safe(reg, &val);
 486                 if (ret)
 487                         goto msr_fail;
 488                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 489                         goto bios_fail;
 490         }
 491
 492         if (x86_pmu.num_counters_fixed) {
 493                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 494                 ret = rdmsrl_safe(reg, &val);
 495                 if (ret)
 496                         goto msr_fail;
 497                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 498                         if (val & (0x03 << i*4))
 499                                 goto bios_fail;
 500                 }
 501         }
 502
 503         /*
 504          * Now write a value and read it back to see if it matches,
 505          * this is needed to detect certain hardware emulators (qemu/kvm)
 506          * that don't trap on the MSR access and always return 0s.
 507          */
 508         val = 0xabcdUL;
 509         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 510         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 511         if (ret || val != val_new)
 512                 goto msr_fail;
 513
 514         return true;
 515
 516 bios_fail:
 517         /*
 518          * We still allow the PMU driver to operate:
 519          */
 520         printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 521         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 522
 523         return true;
 524
 525 msr_fail:
 526         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 527
 528         return false;
 529 }
 530
 531 static void reserve_ds_buffers(void);
 532 static void release_ds_buffers(void);
 533
 534 static void hw_perf_event_destroy(struct perf_event *event)
 535 {
 536         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 537                 release_pmc_hardware();
 538                 release_ds_buffers();
 539                 mutex_unlock(&pmc_reserve_mutex);
 540         }
 541 }
 542
 543 static inline int x86_pmu_initialized(void)
 544 {
 545         return x86_pmu.handle_irq != NULL;
 546 }
 547
 548 static inline int
 549 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 550 {
 551         struct perf_event_attr *attr = &event->attr;
 552         unsigned int cache_type, cache_op, cache_result;
 553         u64 config, val;
 554
 555         config = attr->config;
 556
 557         cache_type = (config >>  0) & 0xff;
 558         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 559                 return -EINVAL;
 560
 561         cache_op = (config >>  8) & 0xff;
 562         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 563                 return -EINVAL;
 564
 565         cache_result = (config >> 16) & 0xff;
 566         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 567                 return -EINVAL;
 568
 569         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 570
 571         if (val == 0)
 572                 return -ENOENT;
 573
 574         if (val == -1)
 575                 return -EINVAL;
 576
 577         hwc->config |= val;
 578         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 579         return x86_pmu_extra_regs(val, event);
 580 }
 581
 582 static int x86_setup_perfctr(struct perf_event *event)
 583 {
 584         struct perf_event_attr *attr = &event->attr;
 585         struct hw_perf_event *hwc = &event->hw;
 586         u64 config;
 587
 588         if (!is_sampling_event(event)) {
 589                 hwc->sample_period = x86_pmu.max_period;
 590                 hwc->last_period = hwc->sample_period;
 591                 local64_set(&hwc->period_left, hwc->sample_period);
 592         } else {
 593                 /*
 594                  * If we have a PMU initialized but no APIC
 595                  * interrupts, we cannot sample hardware
 596                  * events (user-space has to fall back and
 597                  * sample via a hrtimer based software event):
 598                  */
 599                 if (!x86_pmu.apic)
 600                         return -EOPNOTSUPP;
 601         }
 602
 603         /*
 604          * Do not allow config1 (extended registers) to propagate,
 605          * there's no sane user-space generalization yet:
 606          */
 607         if (attr->type == PERF_TYPE_RAW)
 608                 return 0;
 609
 610         if (attr->type == PERF_TYPE_HW_CACHE)
 611                 return set_ext_hw_attr(hwc, event);
 612
 613         if (attr->config >= x86_pmu.max_events)
 614                 return -EINVAL;
 615
 616         /*
 617          * The generic map:
 618          */
 619         config = x86_pmu.event_map(attr->config);
 620
 621         if (config == 0)
 622                 return -ENOENT;
 623
 624         if (config == -1LL)
 625                 return -EINVAL;
 626
 627         /*
 628          * Branch tracing:
 629          */
 630         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 631             !attr->freq && hwc->sample_period == 1) {
 632                 /* BTS is not supported by this architecture. */
 633                 if (!x86_pmu.bts_active)
 634                         return -EOPNOTSUPP;
 635
 636                 /* BTS is currently only allowed for user-mode. */
 637                 if (!attr->exclude_kernel)
 638                         return -EOPNOTSUPP;
 639         }
 640
 641         hwc->config |= config;
 642
 643         return 0;
 644 }
 645
 646 static int x86_pmu_hw_config(struct perf_event *event)
 647 {
 648         if (event->attr.precise_ip) {
 649                 int precise = 0;
 650
 651                 /* Support for constant skid */
 652                 if (x86_pmu.pebs_active) {
 653                         precise++;
 654
 655                         /* Support for IP fixup */
 656                         if (x86_pmu.lbr_nr)
 657                                 precise++;
 658                 }
 659
 660                 if (event->attr.precise_ip > precise)
 661                         return -EOPNOTSUPP;
 662         }
 663
 664         /*
 665          * Generate PMC IRQs:
 666          * (keep 'enabled' bit clear for now)
 667          */
 668         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 669
 670         /*
 671          * Count user and OS events unless requested not to
 672          */
 673         if (!event->attr.exclude_user)
 674                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 675         if (!event->attr.exclude_kernel)
 676                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 677
 678         if (event->attr.type == PERF_TYPE_RAW)
 679                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 680
 681         return x86_setup_perfctr(event);
 682 }
 683
 684 /*
 685  * Setup the hardware configuration for a given attr_type
 686  */
 687 static int __x86_pmu_event_init(struct perf_event *event)
 688 {
 689         int err;
 690
 691         if (!x86_pmu_initialized())
 692                 return -ENODEV;
 693
 694         err = 0;
 695         if (!atomic_inc_not_zero(&active_events)) {
 696                 mutex_lock(&pmc_reserve_mutex);
 697                 if (atomic_read(&active_events) == 0) {
 698                         if (!reserve_pmc_hardware())
 699                                 err = -EBUSY;
 700                         else
 701                                 reserve_ds_buffers();
 702                 }
 703                 if (!err)
 704                         atomic_inc(&active_events);
 705                 mutex_unlock(&pmc_reserve_mutex);
 706         }
 707         if (err)
 708                 return err;
 709
 710         event->destroy = hw_perf_event_destroy;
 711
 712         event->hw.idx = -1;
 713         event->hw.last_cpu = -1;
 714         event->hw.last_tag = ~0ULL;
 715
 716         return x86_pmu.hw_config(event);
 717 }
 718
 719 static void x86_pmu_disable_all(void)
 720 {
 721         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 722         int idx;
 723
 724         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 725                 u64 val;
 726
 727                 if (!test_bit(idx, cpuc->active_mask))
 728                         continue;
 729                 rdmsrl(x86_pmu_config_addr(idx), val);
 730                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 731                         continue;
 732                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 733                 wrmsrl(x86_pmu_config_addr(idx), val);
 734         }
 735 }
 736
 737 static void x86_pmu_disable(struct pmu *pmu)
 738 {
 739         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 740
 741         if (!x86_pmu_initialized())
 742                 return;
 743
 744         if (!cpuc->enabled)
 745                 return;
 746
 747         cpuc->n_added = 0;
 748         cpuc->enabled = 0;
 749         barrier();
 750
 751         x86_pmu.disable_all();
 752 }
 753
 754 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 755                                           u64 enable_mask)
 756 {
 757         if (hwc->extra_reg)
 758                 wrmsrl(hwc->extra_reg, hwc->extra_config);
 759         wrmsrl(hwc->config_base, hwc->config | enable_mask);
 760 }
 761
 762 static void x86_pmu_enable_all(int added)
 763 {
 764         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 765         int idx;
 766
 767         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 768                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 769
 770                 if (!test_bit(idx, cpuc->active_mask))
 771                         continue;
 772
 773                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 774         }
 775 }
 776
 777 static struct pmu pmu;
 778
 779 static inline int is_x86_event(struct perf_event *event)
 780 {
 781         return event->pmu == &pmu;
 782 }
 783
 784 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 785 {
 786         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 787         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 788         int i, j, w, wmax, num = 0;
 789         struct hw_perf_event *hwc;
 790
 791         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 792
 793         for (i = 0; i < n; i++) {
 794                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 795                 constraints[i] = c;
 796         }
 797
 798         /*
 799          * fastpath, try to reuse previous register
 800          */
 801         for (i = 0; i < n; i++) {
 802                 hwc = &cpuc->event_list[i]->hw;
 803                 c = constraints[i];
 804
 805                 /* never assigned */
 806                 if (hwc->idx == -1)
 807                         break;
 808
 809                 /* constraint still honored */
 810                 if (!test_bit(hwc->idx, c->idxmsk))
 811                         break;
 812
 813                 /* not already used */
 814                 if (test_bit(hwc->idx, used_mask))
 815                         break;
 816
 817                 __set_bit(hwc->idx, used_mask);
 818                 if (assign)
 819                         assign[i] = hwc->idx;
 820         }
 821         if (i == n)
 822                 goto done;
 823
 824         /*
 825          * begin slow path
 826          */
 827
 828         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 829
 830         /*
 831          * weight = number of possible counters
 832          *
 833          * 1    = most constrained, only works on one counter
 834          * wmax = least constrained, works on any counter
 835          *
 836          * assign events to counters starting with most
 837          * constrained events.
 838          */
 839         wmax = x86_pmu.num_counters;
 840
 841         /*
 842          * when fixed event counters are present,
 843          * wmax is incremented by 1 to account
 844          * for one more choice
 845          */
 846         if (x86_pmu.num_counters_fixed)
 847                 wmax++;
 848
 849         for (w = 1, num = n; num && w <= wmax; w++) {
 850                 /* for each event */
 851                 for (i = 0; num && i < n; i++) {
 852                         c = constraints[i];
 853                         hwc = &cpuc->event_list[i]->hw;
 854
 855                         if (c->weight != w)
 856                                 continue;
 857
 858                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 859                                 if (!test_bit(j, used_mask))
 860                                         break;
 861                         }
 862
 863                         if (j == X86_PMC_IDX_MAX)
 864                                 break;
 865
 866                         __set_bit(j, used_mask);
 867
 868                         if (assign)
 869                                 assign[i] = j;
 870                         num--;
 871                 }
 872         }
 873 done:
 874         /*
 875          * scheduling failed or is just a simulation,
 876          * free resources if necessary
 877          */
 878         if (!assign || num) {
 879                 for (i = 0; i < n; i++) {
 880                         if (x86_pmu.put_event_constraints)
 881                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 882                 }
 883         }
 884         return num ? -ENOSPC : 0;
 885 }
 886
 887 /*
 888  * dogrp: true if must collect siblings events (group)
 889  * returns total number of events and error code
 890  */
 891 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 892 {
 893         struct perf_event *event;
 894         int n, max_count;
 895
 896         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 897
 898         /* current number of events already accepted */
 899         n = cpuc->n_events;
 900
 901         if (is_x86_event(leader)) {
 902                 if (n >= max_count)
 903                         return -ENOSPC;
 904                 cpuc->event_list[n] = leader;
 905                 n++;
 906         }
 907         if (!dogrp)
 908                 return n;
 909
 910         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 911                 if (!is_x86_event(event) ||
 912                     event->state <= PERF_EVENT_STATE_OFF)
 913                         continue;
 914
 915                 if (n >= max_count)
 916                         return -ENOSPC;
 917
 918                 cpuc->event_list[n] = event;
 919                 n++;
 920         }
 921         return n;
 922 }
 923
 924 static inline void x86_assign_hw_event(struct perf_event *event,
 925                                 struct cpu_hw_events *cpuc, int i)
 926 {
 927         struct hw_perf_event *hwc = &event->hw;
 928
 929         hwc->idx = cpuc->assign[i];
 930         hwc->last_cpu = smp_processor_id();
 931         hwc->last_tag = ++cpuc->tags[i];
 932
 933         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 934                 hwc->config_base = 0;
 935                 hwc->event_base = 0;
 936         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 937                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 938                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
 939         } else {
 940                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 941                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 942         }
 943 }
 944
 945 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 946                                         struct cpu_hw_events *cpuc,
 947                                         int i)
 948 {
 949         return hwc->idx == cpuc->assign[i] &&
 950                 hwc->last_cpu == smp_processor_id() &&
 951                 hwc->last_tag == cpuc->tags[i];
 952 }
 953
 954 static void x86_pmu_start(struct perf_event *event, int flags);
 955 static void x86_pmu_stop(struct perf_event *event, int flags);
 956
 957 static void x86_pmu_enable(struct pmu *pmu)
 958 {
 959         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 960         struct perf_event *event;
 961         struct hw_perf_event *hwc;
 962         int i, added = cpuc->n_added;
 963
 964         if (!x86_pmu_initialized())
 965                 return;
 966
 967         if (cpuc->enabled)
 968                 return;
 969
 970         if (cpuc->n_added) {
 971                 int n_running = cpuc->n_events - cpuc->n_added;
 972                 /*
 973                  * apply assignment obtained either from
 974                  * hw_perf_group_sched_in() or x86_pmu_enable()
 975                  *
 976                  * step1: save events moving to new counters
 977                  * step2: reprogram moved events into new counters
 978                  */
 979                 for (i = 0; i < n_running; i++) {
 980                         event = cpuc->event_list[i];
 981                         hwc = &event->hw;
 982
 983                         /*
 984                          * we can avoid reprogramming counter if:
 985                          * - assigned same counter as last time
 986                          * - running on same CPU as last time
 987                          * - no other event has used the counter since
 988                          */
 989                         if (hwc->idx == -1 ||
 990                             match_prev_assignment(hwc, cpuc, i))
 991                                 continue;
 992
 993                         /*
 994                          * Ensure we don't accidentally enable a stopped
 995                          * counter simply because we rescheduled.
 996                          */
 997                         if (hwc->state & PERF_HES_STOPPED)
 998                                 hwc->state |= PERF_HES_ARCH;
 999
1000                         x86_pmu_stop(event, PERF_EF_UPDATE);
1001                 }
1002
1003                 for (i = 0; i < cpuc->n_events; i++) {
1004                         event = cpuc->event_list[i];
1005                         hwc = &event->hw;
1006
1007                         if (!match_prev_assignment(hwc, cpuc, i))
1008                                 x86_assign_hw_event(event, cpuc, i);
1009                         else if (i < n_running)
1010                                 continue;
1011
1012                         if (hwc->state & PERF_HES_ARCH)
1013                                 continue;
1014
1015                         x86_pmu_start(event, PERF_EF_RELOAD);
1016                 }
1017                 cpuc->n_added = 0;
1018                 perf_events_lapic_init();
1019         }
1020
1021         cpuc->enabled = 1;
1022         barrier();
1023
1024         x86_pmu.enable_all(added);
1025 }
1026
1027 static inline void x86_pmu_disable_event(struct perf_event *event)
1028 {
1029         struct hw_perf_event *hwc = &event->hw;
1030
1031         wrmsrl(hwc->config_base, hwc->config);
1032 }
1033
1034 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1035
1036 /*
1037  * Set the next IRQ period, based on the hwc->period_left value.
1038  * To be called with the event disabled in hw:
1039  */
1040 static int
1041 x86_perf_event_set_period(struct perf_event *event)
1042 {
1043         struct hw_perf_event *hwc = &event->hw;
1044         s64 left = local64_read(&hwc->period_left);
1045         s64 period = hwc->sample_period;
1046         int ret = 0, idx = hwc->idx;
1047
1048         if (idx == X86_PMC_IDX_FIXED_BTS)
1049                 return 0;
1050
1051         /*
1052          * If we are way outside a reasonable range then just skip forward:
1053          */
1054         if (unlikely(left <= -period)) {
1055                 left = period;
1056                 local64_set(&hwc->period_left, left);
1057                 hwc->last_period = period;
1058                 ret = 1;
1059         }
1060
1061         if (unlikely(left <= 0)) {
1062                 left += period;
1063                 local64_set(&hwc->period_left, left);
1064                 hwc->last_period = period;
1065                 ret = 1;
1066         }
1067         /*
1068          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1069          */
1070         if (unlikely(left < 2))
1071                 left = 2;
1072
1073         if (left > x86_pmu.max_period)
1074                 left = x86_pmu.max_period;
1075
1076         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1077
1078         /*
1079          * The hw event starts counting from this event offset,
1080          * mark it to be able to extra future deltas:
1081          */
1082         local64_set(&hwc->prev_count, (u64)-left);
1083
1084         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1085
1086         /*
1087          * Due to erratum on certan cpu we need
1088          * a second write to be sure the register
1089          * is updated properly
1090          */
1091         if (x86_pmu.perfctr_second_write) {
1092                 wrmsrl(hwc->event_base,
1093                         (u64)(-left) & x86_pmu.cntval_mask);
1094         }
1095
1096         perf_event_update_userpage(event);
1097
1098         return ret;
1099 }
1100
1101 static void x86_pmu_enable_event(struct perf_event *event)
1102 {
1103         if (__this_cpu_read(cpu_hw_events.enabled))
1104                 __x86_pmu_enable_event(&event->hw,
1105                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1106 }
1107
1108 /*
1109  * Add a single event to the PMU.
1110  *
1111  * The event is added to the group of enabled events
1112  * but only if it can be scehduled with existing events.
1113  */
1114 static int x86_pmu_add(struct perf_event *event, int flags)
1115 {
1116         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1117         struct hw_perf_event *hwc;
1118         int assign[X86_PMC_IDX_MAX];
1119         int n, n0, ret;
1120
1121         hwc = &event->hw;
1122
1123         perf_pmu_disable(event->pmu);
1124         n0 = cpuc->n_events;
1125         ret = n = collect_events(cpuc, event, false);
1126         if (ret < 0)
1127                 goto out;
1128
1129         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1130         if (!(flags & PERF_EF_START))
1131                 hwc->state |= PERF_HES_ARCH;
1132
1133         /*
1134          * If group events scheduling transaction was started,
1135          * skip the schedulability test here, it will be performed
1136          * at commit time (->commit_txn) as a whole
1137          */
1138         if (cpuc->group_flag & PERF_EVENT_TXN)
1139                 goto done_collect;
1140
1141         ret = x86_pmu.schedule_events(cpuc, n, assign);
1142         if (ret)
1143                 goto out;
1144         /*
1145          * copy new assignment, now we know it is possible
1146          * will be used by hw_perf_enable()
1147          */
1148         memcpy(cpuc->assign, assign, n*sizeof(int));
1149
1150 done_collect:
1151         cpuc->n_events = n;
1152         cpuc->n_added += n - n0;
1153         cpuc->n_txn += n - n0;
1154
1155         ret = 0;
1156 out:
1157         perf_pmu_enable(event->pmu);
1158         return ret;
1159 }
1160
1161 static void x86_pmu_start(struct perf_event *event, int flags)
1162 {
1163         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1164         int idx = event->hw.idx;
1165
1166         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1167                 return;
1168
1169         if (WARN_ON_ONCE(idx == -1))
1170                 return;
1171
1172         if (flags & PERF_EF_RELOAD) {
1173                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1174                 x86_perf_event_set_period(event);
1175         }
1176
1177         event->hw.state = 0;
1178
1179         cpuc->events[idx] = event;
1180         __set_bit(idx, cpuc->active_mask);
1181         __set_bit(idx, cpuc->running);
1182         x86_pmu.enable(event);
1183         perf_event_update_userpage(event);
1184 }
1185
1186 void perf_event_print_debug(void)
1187 {
1188         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1189         u64 pebs;
1190         struct cpu_hw_events *cpuc;
1191         unsigned long flags;
1192         int cpu, idx;
1193
1194         if (!x86_pmu.num_counters)
1195                 return;
1196
1197         local_irq_save(flags);
1198
1199         cpu = smp_processor_id();
1200         cpuc = &per_cpu(cpu_hw_events, cpu);
1201
1202         if (x86_pmu.version >= 2) {
1203                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1204                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1205                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1206                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1207                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1208
1209                 pr_info("\n");
1210                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1211                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1212                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1213                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1214                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1215         }
1216         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1217
1218         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1219                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1220                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1221
1222                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1223
1224                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1225                         cpu, idx, pmc_ctrl);
1226                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1227                         cpu, idx, pmc_count);
1228                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1229                         cpu, idx, prev_left);
1230         }
1231         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1232                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1233
1234                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1235                         cpu, idx, pmc_count);
1236         }
1237         local_irq_restore(flags);
1238 }
1239
1240 static void x86_pmu_stop(struct perf_event *event, int flags)
1241 {
1242         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1243         struct hw_perf_event *hwc = &event->hw;
1244
1245         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1246                 x86_pmu.disable(event);
1247                 cpuc->events[hwc->idx] = NULL;
1248                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1249                 hwc->state |= PERF_HES_STOPPED;
1250         }
1251
1252         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1253                 /*
1254                  * Drain the remaining delta count out of a event
1255                  * that we are disabling:
1256                  */
1257                 x86_perf_event_update(event);
1258                 hwc->state |= PERF_HES_UPTODATE;
1259         }
1260 }
1261
1262 static void x86_pmu_del(struct perf_event *event, int flags)
1263 {
1264         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1265         int i;
1266
1267         /*
1268          * If we're called during a txn, we don't need to do anything.
1269          * The events never got scheduled and ->cancel_txn will truncate
1270          * the event_list.
1271          */
1272         if (cpuc->group_flag & PERF_EVENT_TXN)
1273                 return;
1274
1275         x86_pmu_stop(event, PERF_EF_UPDATE);
1276
1277         for (i = 0; i < cpuc->n_events; i++) {
1278                 if (event == cpuc->event_list[i]) {
1279
1280                         if (x86_pmu.put_event_constraints)
1281                                 x86_pmu.put_event_constraints(cpuc, event);
1282
1283                         while (++i < cpuc->n_events)
1284                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1285
1286                         --cpuc->n_events;
1287                         break;
1288                 }
1289         }
1290         perf_event_update_userpage(event);
1291 }
1292
1293 static int x86_pmu_handle_irq(struct pt_regs *regs)
1294 {
1295         struct perf_sample_data data;
1296         struct cpu_hw_events *cpuc;
1297         struct perf_event *event;
1298         int idx, handled = 0;
1299         u64 val;
1300
1301         perf_sample_data_init(&data, 0);
1302
1303         cpuc = &__get_cpu_var(cpu_hw_events);
1304
1305         /*
1306          * Some chipsets need to unmask the LVTPC in a particular spot
1307          * inside the nmi handler.  As a result, the unmasking was pushed
1308          * into all the nmi handlers.
1309          *
1310          * This generic handler doesn't seem to have any issues where the
1311          * unmasking occurs so it was left at the top.
1312          */
1313         apic_write(APIC_LVTPC, APIC_DM_NMI);
1314
1315         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1316                 if (!test_bit(idx, cpuc->active_mask)) {
1317                         /*
1318                          * Though we deactivated the counter some cpus
1319                          * might still deliver spurious interrupts still
1320                          * in flight. Catch them:
1321                          */
1322                         if (__test_and_clear_bit(idx, cpuc->running))
1323                                 handled++;
1324                         continue;
1325                 }
1326
1327                 event = cpuc->events[idx];
1328
1329                 val = x86_perf_event_update(event);
1330                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1331                         continue;
1332
1333                 /*
1334                  * event overflow
1335                  */
1336                 handled++;
1337                 data.period     = event->hw.last_period;
1338
1339                 if (!x86_perf_event_set_period(event))
1340                         continue;
1341
1342                 if (perf_event_overflow(event, &data, regs))
1343                         x86_pmu_stop(event, 0);
1344         }
1345
1346         if (handled)
1347                 inc_irq_stat(apic_perf_irqs);
1348
1349         return handled;
1350 }
1351
1352 void perf_events_lapic_init(void)
1353 {
1354         if (!x86_pmu.apic || !x86_pmu_initialized())
1355                 return;
1356
1357         /*
1358          * Always use NMI for PMU
1359          */
1360         apic_write(APIC_LVTPC, APIC_DM_NMI);
1361 }
1362
1363 struct pmu_nmi_state {
1364         unsigned int    marked;
1365         int             handled;
1366 };
1367
1368 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1369
1370 static int __kprobes
1371 perf_event_nmi_handler(struct notifier_block *self,
1372                          unsigned long cmd, void *__args)
1373 {
1374         struct die_args *args = __args;
1375         unsigned int this_nmi;
1376         int handled;
1377
1378         if (!atomic_read(&active_events))
1379                 return NOTIFY_DONE;
1380
1381         switch (cmd) {
1382         case DIE_NMI:
1383                 break;
1384         case DIE_NMIUNKNOWN:
1385                 this_nmi = percpu_read(irq_stat.__nmi_count);
1386                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1387                         /* let the kernel handle the unknown nmi */
1388                         return NOTIFY_DONE;
1389                 /*
1390                  * This one is a PMU back-to-back nmi. Two events
1391                  * trigger 'simultaneously' raising two back-to-back
1392                  * NMIs. If the first NMI handles both, the latter
1393                  * will be empty and daze the CPU. So, we drop it to
1394                  * avoid false-positive 'unknown nmi' messages.
1395                  */
1396                 return NOTIFY_STOP;
1397         default:
1398                 return NOTIFY_DONE;
1399         }
1400
1401         handled = x86_pmu.handle_irq(args->regs);
1402         if (!handled)
1403                 return NOTIFY_DONE;
1404
1405         this_nmi = percpu_read(irq_stat.__nmi_count);
1406         if ((handled > 1) ||
1407                 /* the next nmi could be a back-to-back nmi */
1408             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1409              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1410                 /*
1411                  * We could have two subsequent back-to-back nmis: The
1412                  * first handles more than one counter, the 2nd
1413                  * handles only one counter and the 3rd handles no
1414                  * counter.
1415                  *
1416                  * This is the 2nd nmi because the previous was
1417                  * handling more than one counter. We will mark the
1418                  * next (3rd) and then drop it if unhandled.
1419                  */
1420                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1421                 __this_cpu_write(pmu_nmi.handled, handled);
1422         }
1423
1424         return NOTIFY_STOP;
1425 }
1426
1427 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1428         .notifier_call          = perf_event_nmi_handler,
1429         .next                   = NULL,
1430         .priority               = NMI_LOCAL_LOW_PRIOR,
1431 };
1432
1433 static struct event_constraint unconstrained;
1434 static struct event_constraint emptyconstraint;
1435
1436 static struct event_constraint *
1437 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1438 {
1439         struct event_constraint *c;
1440
1441         if (x86_pmu.event_constraints) {
1442                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1443                         if ((event->hw.config & c->cmask) == c->code)
1444                                 return c;
1445                 }
1446         }
1447
1448         return &unconstrained;
1449 }
1450
1451 #include "perf_event_amd.c"
1452 #include "perf_event_p6.c"
1453 #include "perf_event_p4.c"
1454 #include "perf_event_intel_lbr.c"
1455 #include "perf_event_intel_ds.c"
1456 #include "perf_event_intel.c"
1457
1458 static int __cpuinit
1459 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1460 {
1461         unsigned int cpu = (long)hcpu;
1462         int ret = NOTIFY_OK;
1463
1464         switch (action & ~CPU_TASKS_FROZEN) {
1465         case CPU_UP_PREPARE:
1466                 if (x86_pmu.cpu_prepare)
1467                         ret = x86_pmu.cpu_prepare(cpu);
1468                 break;
1469
1470         case CPU_STARTING:
1471                 if (x86_pmu.cpu_starting)
1472                         x86_pmu.cpu_starting(cpu);
1473                 break;
1474
1475         case CPU_DYING:
1476                 if (x86_pmu.cpu_dying)
1477                         x86_pmu.cpu_dying(cpu);
1478                 break;
1479
1480         case CPU_UP_CANCELED:
1481         case CPU_DEAD:
1482                 if (x86_pmu.cpu_dead)
1483                         x86_pmu.cpu_dead(cpu);
1484                 break;
1485
1486         default:
1487                 break;
1488         }
1489
1490         return ret;
1491 }
1492
1493 static void __init pmu_check_apic(void)
1494 {
1495         if (cpu_has_apic)
1496                 return;
1497
1498         x86_pmu.apic = 0;
1499         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1500         pr_info("no hardware sampling interrupt available.\n");
1501 }
1502
1503 static int __init init_hw_perf_events(void)
1504 {
1505         struct event_constraint *c;
1506         int err;
1507
1508         pr_info("Performance Events: ");
1509
1510         switch (boot_cpu_data.x86_vendor) {
1511         case X86_VENDOR_INTEL:
1512                 err = intel_pmu_init();
1513                 break;
1514         case X86_VENDOR_AMD:
1515                 err = amd_pmu_init();
1516                 break;
1517         default:
1518                 return 0;
1519         }
1520         if (err != 0) {
1521                 pr_cont("no PMU driver, software events only.\n");
1522                 return 0;
1523         }
1524
1525         pmu_check_apic();
1526
1527         /* sanity check that the hardware exists or is emulated */
1528         if (!check_hw_exists())
1529                 return 0;
1530
1531         pr_cont("%s PMU driver.\n", x86_pmu.name);
1532
1533         if (x86_pmu.quirks)
1534                 x86_pmu.quirks();
1535
1536         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1537                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1538                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1539                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1540         }
1541         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1542
1543         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1544                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1545                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1546                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1547         }
1548
1549         x86_pmu.intel_ctrl |=
1550                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1551
1552         perf_events_lapic_init();
1553         register_die_notifier(&perf_event_nmi_notifier);
1554
1555         unconstrained = (struct event_constraint)
1556                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1557                                    0, x86_pmu.num_counters);
1558
1559         if (x86_pmu.event_constraints) {
1560                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1561                         if (c->cmask != X86_RAW_EVENT_MASK)
1562                                 continue;
1563
1564                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1565                         c->weight += x86_pmu.num_counters;
1566                 }
1567         }
1568
1569         pr_info("... version:                %d\n",     x86_pmu.version);
1570         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1571         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1572         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1573         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1574         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1575         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1576
1577         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1578         perf_cpu_notifier(x86_pmu_notifier);
1579
1580         return 0;
1581 }
1582 early_initcall(init_hw_perf_events);
1583
1584 static inline void x86_pmu_read(struct perf_event *event)
1585 {
1586         x86_perf_event_update(event);
1587 }
1588
1589 /*
1590  * Start group events scheduling transaction
1591  * Set the flag to make pmu::enable() not perform the
1592  * schedulability test, it will be performed at commit time
1593  */
1594 static void x86_pmu_start_txn(struct pmu *pmu)
1595 {
1596         perf_pmu_disable(pmu);
1597         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1598         __this_cpu_write(cpu_hw_events.n_txn, 0);
1599 }
1600
1601 /*
1602  * Stop group events scheduling transaction
1603  * Clear the flag and pmu::enable() will perform the
1604  * schedulability test.
1605  */
1606 static void x86_pmu_cancel_txn(struct pmu *pmu)
1607 {
1608         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1609         /*
1610          * Truncate the collected events.
1611          */
1612         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1613         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1614         perf_pmu_enable(pmu);
1615 }
1616
1617 /*
1618  * Commit group events scheduling transaction
1619  * Perform the group schedulability test as a whole
1620  * Return 0 if success
1621  */
1622 static int x86_pmu_commit_txn(struct pmu *pmu)
1623 {
1624         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1625         int assign[X86_PMC_IDX_MAX];
1626         int n, ret;
1627
1628         n = cpuc->n_events;
1629
1630         if (!x86_pmu_initialized())
1631                 return -EAGAIN;
1632
1633         ret = x86_pmu.schedule_events(cpuc, n, assign);
1634         if (ret)
1635                 return ret;
1636
1637         /*
1638          * copy new assignment, now we know it is possible
1639          * will be used by hw_perf_enable()
1640          */
1641         memcpy(cpuc->assign, assign, n*sizeof(int));
1642
1643         cpuc->group_flag &= ~PERF_EVENT_TXN;
1644         perf_pmu_enable(pmu);
1645         return 0;
1646 }
1647
1648 /*
1649  * validate that we can schedule this event
1650  */
1651 static int validate_event(struct perf_event *event)
1652 {
1653         struct cpu_hw_events *fake_cpuc;
1654         struct event_constraint *c;
1655         int ret = 0;
1656
1657         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1658         if (!fake_cpuc)
1659                 return -ENOMEM;
1660
1661         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1662
1663         if (!c || !c->weight)
1664                 ret = -ENOSPC;
1665
1666         if (x86_pmu.put_event_constraints)
1667                 x86_pmu.put_event_constraints(fake_cpuc, event);
1668
1669         kfree(fake_cpuc);
1670
1671         return ret;
1672 }
1673
1674 /*
1675  * validate a single event group
1676  *
1677  * validation include:
1678  *      - check events are compatible which each other
1679  *      - events do not compete for the same counter
1680  *      - number of events <= number of counters
1681  *
1682  * validation ensures the group can be loaded onto the
1683  * PMU if it was the only group available.
1684  */
1685 static int validate_group(struct perf_event *event)
1686 {
1687         struct perf_event *leader = event->group_leader;
1688         struct cpu_hw_events *fake_cpuc;
1689         int ret, n;
1690
1691         ret = -ENOMEM;
1692         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1693         if (!fake_cpuc)
1694                 goto out;
1695
1696         /*
1697          * the event is not yet connected with its
1698          * siblings therefore we must first collect
1699          * existing siblings, then add the new event
1700          * before we can simulate the scheduling
1701          */
1702         ret = -ENOSPC;
1703         n = collect_events(fake_cpuc, leader, true);
1704         if (n < 0)
1705                 goto out_free;
1706
1707         fake_cpuc->n_events = n;
1708         n = collect_events(fake_cpuc, event, false);
1709         if (n < 0)
1710                 goto out_free;
1711
1712         fake_cpuc->n_events = n;
1713
1714         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1715
1716 out_free:
1717         kfree(fake_cpuc);
1718 out:
1719         return ret;
1720 }
1721
1722 static int x86_pmu_event_init(struct perf_event *event)
1723 {
1724         struct pmu *tmp;
1725         int err;
1726
1727         switch (event->attr.type) {
1728         case PERF_TYPE_RAW:
1729         case PERF_TYPE_HARDWARE:
1730         case PERF_TYPE_HW_CACHE:
1731                 break;
1732
1733         default:
1734                 return -ENOENT;
1735         }
1736
1737         err = __x86_pmu_event_init(event);
1738         if (!err) {
1739                 /*
1740                  * we temporarily connect event to its pmu
1741                  * such that validate_group() can classify
1742                  * it as an x86 event using is_x86_event()
1743                  */
1744                 tmp = event->pmu;
1745                 event->pmu = &pmu;
1746
1747                 if (event->group_leader != event)
1748                         err = validate_group(event);
1749                 else
1750                         err = validate_event(event);
1751
1752                 event->pmu = tmp;
1753         }
1754         if (err) {
1755                 if (event->destroy)
1756                         event->destroy(event);
1757         }
1758
1759         return err;
1760 }
1761
1762 static struct pmu pmu = {
1763         .pmu_enable     = x86_pmu_enable,
1764         .pmu_disable    = x86_pmu_disable,
1765
1766         .event_init     = x86_pmu_event_init,
1767
1768         .add            = x86_pmu_add,
1769         .del            = x86_pmu_del,
1770         .start          = x86_pmu_start,
1771         .stop           = x86_pmu_stop,
1772         .read           = x86_pmu_read,
1773
1774         .start_txn      = x86_pmu_start_txn,
1775         .cancel_txn     = x86_pmu_cancel_txn,
1776         .commit_txn     = x86_pmu_commit_txn,
1777 };
1778
1779 /*
1780  * callchain support
1781  */
1782
1783 static int backtrace_stack(void *data, char *name)
1784 {
1785         return 0;
1786 }
1787
1788 static void backtrace_address(void *data, unsigned long addr, int reliable)
1789 {
1790         struct perf_callchain_entry *entry = data;
1791
1792         perf_callchain_store(entry, addr);
1793 }
1794
1795 static const struct stacktrace_ops backtrace_ops = {
1796         .stack                  = backtrace_stack,
1797         .address                = backtrace_address,
1798         .walk_stack             = print_context_stack_bp,
1799 };
1800
1801 void
1802 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1803 {
1804         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1805                 /* TODO: We don't support guest os callchain now */
1806                 return;
1807         }
1808
1809         perf_callchain_store(entry, regs->ip);
1810
1811         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1812 }
1813
1814 #ifdef CONFIG_COMPAT
1815 static inline int
1816 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1817 {
1818         /* 32-bit process in 64-bit kernel. */
1819         struct stack_frame_ia32 frame;
1820         const void __user *fp;
1821
1822         if (!test_thread_flag(TIF_IA32))
1823                 return 0;
1824
1825         fp = compat_ptr(regs->bp);
1826         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1827                 unsigned long bytes;
1828                 frame.next_frame     = 0;
1829                 frame.return_address = 0;
1830
1831                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1832                 if (bytes != sizeof(frame))
1833                         break;
1834
1835                 if (fp < compat_ptr(regs->sp))
1836                         break;
1837
1838                 perf_callchain_store(entry, frame.return_address);
1839                 fp = compat_ptr(frame.next_frame);
1840         }
1841         return 1;
1842 }
1843 #else
1844 static inline int
1845 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1846 {
1847     return 0;
1848 }
1849 #endif
1850
1851 void
1852 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1853 {
1854         struct stack_frame frame;
1855         const void __user *fp;
1856
1857         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1858                 /* TODO: We don't support guest os callchain now */
1859                 return;
1860         }
1861
1862         fp = (void __user *)regs->bp;
1863
1864         perf_callchain_store(entry, regs->ip);
1865
1866         if (perf_callchain_user32(regs, entry))
1867                 return;
1868
1869         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1870                 unsigned long bytes;
1871                 frame.next_frame             = NULL;
1872                 frame.return_address = 0;
1873
1874                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1875                 if (bytes != sizeof(frame))
1876                         break;
1877
1878                 if ((unsigned long)fp < regs->sp)
1879                         break;
1880
1881                 perf_callchain_store(entry, frame.return_address);
1882                 fp = frame.next_frame;
1883         }
1884 }
1885
1886 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1887 {
1888         unsigned long ip;
1889
1890         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1891                 ip = perf_guest_cbs->get_guest_ip();
1892         else
1893                 ip = instruction_pointer(regs);
1894
1895         return ip;
1896 }
1897
1898 unsigned long perf_misc_flags(struct pt_regs *regs)
1899 {
1900         int misc = 0;
1901
1902         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1903                 if (perf_guest_cbs->is_user_mode())
1904                         misc |= PERF_RECORD_MISC_GUEST_USER;
1905                 else
1906                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1907         } else {
1908                 if (user_mode(regs))
1909                         misc |= PERF_RECORD_MISC_USER;
1910                 else
1911                         misc |= PERF_RECORD_MISC_KERNEL;
1912         }
1913
1914         if (regs->flags & PERF_EFLAGS_EXACT)
1915                 misc |= PERF_RECORD_MISC_EXACT_IP;
1916
1917         return misc;
1918 }