arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/timer.h>
  35
  36 #include "perf_event.h"
  37
  38 struct x86_pmu x86_pmu __read_mostly;
  39
  40 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  41         .enabled = 1,
  42 };
  43
  44 u64 __read_mostly hw_cache_event_ids
  45                                 [PERF_COUNT_HW_CACHE_MAX]
  46                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  47                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  48 u64 __read_mostly hw_cache_extra_regs
  49                                 [PERF_COUNT_HW_CACHE_MAX]
  50                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  51                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  52
  53 /*
  54  * Propagate event elapsed time into the generic event.
  55  * Can only be executed on the CPU where the event is active.
  56  * Returns the delta events processed.
  57  */
  58 u64 x86_perf_event_update(struct perf_event *event)
  59 {
  60         struct hw_perf_event *hwc = &event->hw;
  61         int shift = 64 - x86_pmu.cntval_bits;
  62         u64 prev_raw_count, new_raw_count;
  63         int idx = hwc->idx;
  64         s64 delta;
  65
  66         if (idx == X86_PMC_IDX_FIXED_BTS)
  67                 return 0;
  68
  69         /*
  70          * Careful: an NMI might modify the previous event value.
  71          *
  72          * Our tactic to handle this is to first atomically read and
  73          * exchange a new raw count - then add that new-prev delta
  74          * count to the generic event atomically:
  75          */
  76 again:
  77         prev_raw_count = local64_read(&hwc->prev_count);
  78         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  79
  80         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  81                                         new_raw_count) != prev_raw_count)
  82                 goto again;
  83
  84         /*
  85          * Now we have the new raw value and have updated the prev
  86          * timestamp already. We can now calculate the elapsed delta
  87          * (event-)time and add that to the generic event.
  88          *
  89          * Careful, not all hw sign-extends above the physical width
  90          * of the count.
  91          */
  92         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  93         delta >>= shift;
  94
  95         local64_add(delta, &event->count);
  96         local64_sub(delta, &hwc->period_left);
  97
  98         return new_raw_count;
  99 }
 100
 101 /*
 102  * Find and validate any extra registers to set up.
 103  */
 104 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 105 {
 106         struct hw_perf_event_extra *reg;
 107         struct extra_reg *er;
 108
 109         reg = &event->hw.extra_reg;
 110
 111         if (!x86_pmu.extra_regs)
 112                 return 0;
 113
 114         for (er = x86_pmu.extra_regs; er->msr; er++) {
 115                 if (er->event != (config & er->config_mask))
 116                         continue;
 117                 if (event->attr.config1 & ~er->valid_mask)
 118                         return -EINVAL;
 119
 120                 reg->idx = er->idx;
 121                 reg->config = event->attr.config1;
 122                 reg->reg = er->msr;
 123                 break;
 124         }
 125         return 0;
 126 }
 127
 128 static atomic_t active_events;
 129 static DEFINE_MUTEX(pmc_reserve_mutex);
 130
 131 #ifdef CONFIG_X86_LOCAL_APIC
 132
 133 static bool reserve_pmc_hardware(void)
 134 {
 135         int i;
 136
 137         for (i = 0; i < x86_pmu.num_counters; i++) {
 138                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 139                         goto perfctr_fail;
 140         }
 141
 142         for (i = 0; i < x86_pmu.num_counters; i++) {
 143                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 144                         goto eventsel_fail;
 145         }
 146
 147         return true;
 148
 149 eventsel_fail:
 150         for (i--; i >= 0; i--)
 151                 release_evntsel_nmi(x86_pmu_config_addr(i));
 152
 153         i = x86_pmu.num_counters;
 154
 155 perfctr_fail:
 156         for (i--; i >= 0; i--)
 157                 release_perfctr_nmi(x86_pmu_event_addr(i));
 158
 159         return false;
 160 }
 161
 162 static void release_pmc_hardware(void)
 163 {
 164         int i;
 165
 166         for (i = 0; i < x86_pmu.num_counters; i++) {
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168                 release_evntsel_nmi(x86_pmu_config_addr(i));
 169         }
 170 }
 171
 172 #else
 173
 174 static bool reserve_pmc_hardware(void) { return true; }
 175 static void release_pmc_hardware(void) {}
 176
 177 #endif
 178
 179 static bool check_hw_exists(void)
 180 {
 181         u64 val, val_new = 0;
 182         int i, reg, ret = 0;
 183
 184         /*
 185          * Check to see if the BIOS enabled any of the counters, if so
 186          * complain and bail.
 187          */
 188         for (i = 0; i < x86_pmu.num_counters; i++) {
 189                 reg = x86_pmu_config_addr(i);
 190                 ret = rdmsrl_safe(reg, &val);
 191                 if (ret)
 192                         goto msr_fail;
 193                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 194                         goto bios_fail;
 195         }
 196
 197         if (x86_pmu.num_counters_fixed) {
 198                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 199                 ret = rdmsrl_safe(reg, &val);
 200                 if (ret)
 201                         goto msr_fail;
 202                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 203                         if (val & (0x03 << i*4))
 204                                 goto bios_fail;
 205                 }
 206         }
 207
 208         /*
 209          * Now write a value and read it back to see if it matches,
 210          * this is needed to detect certain hardware emulators (qemu/kvm)
 211          * that don't trap on the MSR access and always return 0s.
 212          */
 213         val = 0xabcdUL;
 214         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 215         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 216         if (ret || val != val_new)
 217                 goto msr_fail;
 218
 219         return true;
 220
 221 bios_fail:
 222         /*
 223          * We still allow the PMU driver to operate:
 224          */
 225         printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 226         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 227
 228         return true;
 229
 230 msr_fail:
 231         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 232
 233         return false;
 234 }
 235
 236 static void hw_perf_event_destroy(struct perf_event *event)
 237 {
 238         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 239                 release_pmc_hardware();
 240                 release_ds_buffers();
 241                 mutex_unlock(&pmc_reserve_mutex);
 242         }
 243 }
 244
 245 static inline int x86_pmu_initialized(void)
 246 {
 247         return x86_pmu.handle_irq != NULL;
 248 }
 249
 250 static inline int
 251 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 252 {
 253         struct perf_event_attr *attr = &event->attr;
 254         unsigned int cache_type, cache_op, cache_result;
 255         u64 config, val;
 256
 257         config = attr->config;
 258
 259         cache_type = (config >>  0) & 0xff;
 260         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 261                 return -EINVAL;
 262
 263         cache_op = (config >>  8) & 0xff;
 264         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 265                 return -EINVAL;
 266
 267         cache_result = (config >> 16) & 0xff;
 268         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 269                 return -EINVAL;
 270
 271         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 272
 273         if (val == 0)
 274                 return -ENOENT;
 275
 276         if (val == -1)
 277                 return -EINVAL;
 278
 279         hwc->config |= val;
 280         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 281         return x86_pmu_extra_regs(val, event);
 282 }
 283
 284 int x86_setup_perfctr(struct perf_event *event)
 285 {
 286         struct perf_event_attr *attr = &event->attr;
 287         struct hw_perf_event *hwc = &event->hw;
 288         u64 config;
 289
 290         if (!is_sampling_event(event)) {
 291                 hwc->sample_period = x86_pmu.max_period;
 292                 hwc->last_period = hwc->sample_period;
 293                 local64_set(&hwc->period_left, hwc->sample_period);
 294         } else {
 295                 /*
 296                  * If we have a PMU initialized but no APIC
 297                  * interrupts, we cannot sample hardware
 298                  * events (user-space has to fall back and
 299                  * sample via a hrtimer based software event):
 300                  */
 301                 if (!x86_pmu.apic)
 302                         return -EOPNOTSUPP;
 303         }
 304
 305         if (attr->type == PERF_TYPE_RAW)
 306                 return x86_pmu_extra_regs(event->attr.config, event);
 307
 308         if (attr->type == PERF_TYPE_HW_CACHE)
 309                 return set_ext_hw_attr(hwc, event);
 310
 311         if (attr->config >= x86_pmu.max_events)
 312                 return -EINVAL;
 313
 314         /*
 315          * The generic map:
 316          */
 317         config = x86_pmu.event_map(attr->config);
 318
 319         if (config == 0)
 320                 return -ENOENT;
 321
 322         if (config == -1LL)
 323                 return -EINVAL;
 324
 325         /*
 326          * Branch tracing:
 327          */
 328         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 329             !attr->freq && hwc->sample_period == 1) {
 330                 /* BTS is not supported by this architecture. */
 331                 if (!x86_pmu.bts_active)
 332                         return -EOPNOTSUPP;
 333
 334                 /* BTS is currently only allowed for user-mode. */
 335                 if (!attr->exclude_kernel)
 336                         return -EOPNOTSUPP;
 337         }
 338
 339         hwc->config |= config;
 340
 341         return 0;
 342 }
 343
 344 /*
 345  * check that branch_sample_type is compatible with
 346  * settings needed for precise_ip > 1 which implies
 347  * using the LBR to capture ALL taken branches at the
 348  * priv levels of the measurement
 349  */
 350 static inline int precise_br_compat(struct perf_event *event)
 351 {
 352         u64 m = event->attr.branch_sample_type;
 353         u64 b = 0;
 354
 355         /* must capture all branches */
 356         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 357                 return 0;
 358
 359         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 360
 361         if (!event->attr.exclude_user)
 362                 b |= PERF_SAMPLE_BRANCH_USER;
 363
 364         if (!event->attr.exclude_kernel)
 365                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 366
 367         /*
 368          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 369          */
 370
 371         return m == b;
 372 }
 373
 374 int x86_pmu_hw_config(struct perf_event *event)
 375 {
 376         if (event->attr.precise_ip) {
 377                 int precise = 0;
 378
 379                 /* Support for constant skid */
 380                 if (x86_pmu.pebs_active) {
 381                         precise++;
 382
 383                         /* Support for IP fixup */
 384                         if (x86_pmu.lbr_nr)
 385                                 precise++;
 386                 }
 387
 388                 if (event->attr.precise_ip > precise)
 389                         return -EOPNOTSUPP;
 390                 /*
 391                  * check that PEBS LBR correction does not conflict with
 392                  * whatever the user is asking with attr->branch_sample_type
 393                  */
 394                 if (event->attr.precise_ip > 1) {
 395                         u64 *br_type = &event->attr.branch_sample_type;
 396
 397                         if (has_branch_stack(event)) {
 398                                 if (!precise_br_compat(event))
 399                                         return -EOPNOTSUPP;
 400
 401                                 /* branch_sample_type is compatible */
 402
 403                         } else {
 404                                 /*
 405                                  * user did not specify  branch_sample_type
 406                                  *
 407                                  * For PEBS fixups, we capture all
 408                                  * the branches at the priv level of the
 409                                  * event.
 410                                  */
 411                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 412
 413                                 if (!event->attr.exclude_user)
 414                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 415
 416                                 if (!event->attr.exclude_kernel)
 417                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 418                         }
 419                 }
 420         }
 421
 422         /*
 423          * Generate PMC IRQs:
 424          * (keep 'enabled' bit clear for now)
 425          */
 426         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 427
 428         /*
 429          * Count user and OS events unless requested not to
 430          */
 431         if (!event->attr.exclude_user)
 432                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 433         if (!event->attr.exclude_kernel)
 434                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 435
 436         if (event->attr.type == PERF_TYPE_RAW)
 437                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 438
 439         return x86_setup_perfctr(event);
 440 }
 441
 442 /*
 443  * Setup the hardware configuration for a given attr_type
 444  */
 445 static int __x86_pmu_event_init(struct perf_event *event)
 446 {
 447         int err;
 448
 449         if (!x86_pmu_initialized())
 450                 return -ENODEV;
 451
 452         err = 0;
 453         if (!atomic_inc_not_zero(&active_events)) {
 454                 mutex_lock(&pmc_reserve_mutex);
 455                 if (atomic_read(&active_events) == 0) {
 456                         if (!reserve_pmc_hardware())
 457                                 err = -EBUSY;
 458                         else
 459                                 reserve_ds_buffers();
 460                 }
 461                 if (!err)
 462                         atomic_inc(&active_events);
 463                 mutex_unlock(&pmc_reserve_mutex);
 464         }
 465         if (err)
 466                 return err;
 467
 468         event->destroy = hw_perf_event_destroy;
 469
 470         event->hw.idx = -1;
 471         event->hw.last_cpu = -1;
 472         event->hw.last_tag = ~0ULL;
 473
 474         /* mark unused */
 475         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 476         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 477
 478         return x86_pmu.hw_config(event);
 479 }
 480
 481 void x86_pmu_disable_all(void)
 482 {
 483         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 484         int idx;
 485
 486         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 487                 u64 val;
 488
 489                 if (!test_bit(idx, cpuc->active_mask))
 490                         continue;
 491                 rdmsrl(x86_pmu_config_addr(idx), val);
 492                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 493                         continue;
 494                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 495                 wrmsrl(x86_pmu_config_addr(idx), val);
 496         }
 497 }
 498
 499 static void x86_pmu_disable(struct pmu *pmu)
 500 {
 501         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 502
 503         if (!x86_pmu_initialized())
 504                 return;
 505
 506         if (!cpuc->enabled)
 507                 return;
 508
 509         cpuc->n_added = 0;
 510         cpuc->enabled = 0;
 511         barrier();
 512
 513         x86_pmu.disable_all();
 514 }
 515
 516 void x86_pmu_enable_all(int added)
 517 {
 518         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 519         int idx;
 520
 521         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 522                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 523
 524                 if (!test_bit(idx, cpuc->active_mask))
 525                         continue;
 526
 527                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 528         }
 529 }
 530
 531 static struct pmu pmu;
 532
 533 static inline int is_x86_event(struct perf_event *event)
 534 {
 535         return event->pmu == &pmu;
 536 }
 537
 538 /*
 539  * Event scheduler state:
 540  *
 541  * Assign events iterating over all events and counters, beginning
 542  * with events with least weights first. Keep the current iterator
 543  * state in struct sched_state.
 544  */
 545 struct sched_state {
 546         int     weight;
 547         int     event;          /* event index */
 548         int     counter;        /* counter index */
 549         int     unassigned;     /* number of events to be assigned left */
 550         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 551 };
 552
 553 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 554 #define SCHED_STATES_MAX        2
 555
 556 struct perf_sched {
 557         int                     max_weight;
 558         int                     max_events;
 559         struct event_constraint **constraints;
 560         struct sched_state      state;
 561         int                     saved_states;
 562         struct sched_state      saved[SCHED_STATES_MAX];
 563 };
 564
 565 /*
 566  * Initialize interator that runs through all events and counters.
 567  */
 568 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c,
 569                             int num, int wmin, int wmax)
 570 {
 571         int idx;
 572
 573         memset(sched, 0, sizeof(*sched));
 574         sched->max_events       = num;
 575         sched->max_weight       = wmax;
 576         sched->constraints      = c;
 577
 578         for (idx = 0; idx < num; idx++) {
 579                 if (c[idx]->weight == wmin)
 580                         break;
 581         }
 582
 583         sched->state.event      = idx;          /* start with min weight */
 584         sched->state.weight     = wmin;
 585         sched->state.unassigned = num;
 586 }
 587
 588 static void perf_sched_save_state(struct perf_sched *sched)
 589 {
 590         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 591                 return;
 592
 593         sched->saved[sched->saved_states] = sched->state;
 594         sched->saved_states++;
 595 }
 596
 597 static bool perf_sched_restore_state(struct perf_sched *sched)
 598 {
 599         if (!sched->saved_states)
 600                 return false;
 601
 602         sched->saved_states--;
 603         sched->state = sched->saved[sched->saved_states];
 604
 605         /* continue with next counter: */
 606         clear_bit(sched->state.counter++, sched->state.used);
 607
 608         return true;
 609 }
 610
 611 /*
 612  * Select a counter for the current event to schedule. Return true on
 613  * success.
 614  */
 615 static bool __perf_sched_find_counter(struct perf_sched *sched)
 616 {
 617         struct event_constraint *c;
 618         int idx;
 619
 620         if (!sched->state.unassigned)
 621                 return false;
 622
 623         if (sched->state.event >= sched->max_events)
 624                 return false;
 625
 626         c = sched->constraints[sched->state.event];
 627
 628         /* Prefer fixed purpose counters */
 629         if (x86_pmu.num_counters_fixed) {
 630                 idx = X86_PMC_IDX_FIXED;
 631                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 632                         if (!__test_and_set_bit(idx, sched->state.used))
 633                                 goto done;
 634                 }
 635         }
 636         /* Grab the first unused counter starting with idx */
 637         idx = sched->state.counter;
 638         for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
 639                 if (!__test_and_set_bit(idx, sched->state.used))
 640                         goto done;
 641         }
 642
 643         return false;
 644
 645 done:
 646         sched->state.counter = idx;
 647
 648         if (c->overlap)
 649                 perf_sched_save_state(sched);
 650
 651         return true;
 652 }
 653
 654 static bool perf_sched_find_counter(struct perf_sched *sched)
 655 {
 656         while (!__perf_sched_find_counter(sched)) {
 657                 if (!perf_sched_restore_state(sched))
 658                         return false;
 659         }
 660
 661         return true;
 662 }
 663
 664 /*
 665  * Go through all unassigned events and find the next one to schedule.
 666  * Take events with the least weight first. Return true on success.
 667  */
 668 static bool perf_sched_next_event(struct perf_sched *sched)
 669 {
 670         struct event_constraint *c;
 671
 672         if (!sched->state.unassigned || !--sched->state.unassigned)
 673                 return false;
 674
 675         do {
 676                 /* next event */
 677                 sched->state.event++;
 678                 if (sched->state.event >= sched->max_events) {
 679                         /* next weight */
 680                         sched->state.event = 0;
 681                         sched->state.weight++;
 682                         if (sched->state.weight > sched->max_weight)
 683                                 return false;
 684                 }
 685                 c = sched->constraints[sched->state.event];
 686         } while (c->weight != sched->state.weight);
 687
 688         sched->state.counter = 0;       /* start with first counter */
 689
 690         return true;
 691 }
 692
 693 /*
 694  * Assign a counter for each event.
 695  */
 696 static int perf_assign_events(struct event_constraint **constraints, int n,
 697                               int wmin, int wmax, int *assign)
 698 {
 699         struct perf_sched sched;
 700
 701         perf_sched_init(&sched, constraints, n, wmin, wmax);
 702
 703         do {
 704                 if (!perf_sched_find_counter(&sched))
 705                         break;  /* failed */
 706                 if (assign)
 707                         assign[sched.state.event] = sched.state.counter;
 708         } while (perf_sched_next_event(&sched));
 709
 710         return sched.state.unassigned;
 711 }
 712
 713 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 714 {
 715         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 716         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 717         int i, wmin, wmax, num = 0;
 718         struct hw_perf_event *hwc;
 719
 720         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 721
 722         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 723                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 724                 constraints[i] = c;
 725                 wmin = min(wmin, c->weight);
 726                 wmax = max(wmax, c->weight);
 727         }
 728
 729         /*
 730          * fastpath, try to reuse previous register
 731          */
 732         for (i = 0; i < n; i++) {
 733                 hwc = &cpuc->event_list[i]->hw;
 734                 c = constraints[i];
 735
 736                 /* never assigned */
 737                 if (hwc->idx == -1)
 738                         break;
 739
 740                 /* constraint still honored */
 741                 if (!test_bit(hwc->idx, c->idxmsk))
 742                         break;
 743
 744                 /* not already used */
 745                 if (test_bit(hwc->idx, used_mask))
 746                         break;
 747
 748                 __set_bit(hwc->idx, used_mask);
 749                 if (assign)
 750                         assign[i] = hwc->idx;
 751         }
 752
 753         /* slow path */
 754         if (i != n)
 755                 num = perf_assign_events(constraints, n, wmin, wmax, assign);
 756
 757         /*
 758          * scheduling failed or is just a simulation,
 759          * free resources if necessary
 760          */
 761         if (!assign || num) {
 762                 for (i = 0; i < n; i++) {
 763                         if (x86_pmu.put_event_constraints)
 764                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 765                 }
 766         }
 767         return num ? -EINVAL : 0;
 768 }
 769
 770 /*
 771  * dogrp: true if must collect siblings events (group)
 772  * returns total number of events and error code
 773  */
 774 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 775 {
 776         struct perf_event *event;
 777         int n, max_count;
 778
 779         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 780
 781         /* current number of events already accepted */
 782         n = cpuc->n_events;
 783
 784         if (is_x86_event(leader)) {
 785                 if (n >= max_count)
 786                         return -EINVAL;
 787                 cpuc->event_list[n] = leader;
 788                 n++;
 789         }
 790         if (!dogrp)
 791                 return n;
 792
 793         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 794                 if (!is_x86_event(event) ||
 795                     event->state <= PERF_EVENT_STATE_OFF)
 796                         continue;
 797
 798                 if (n >= max_count)
 799                         return -EINVAL;
 800
 801                 cpuc->event_list[n] = event;
 802                 n++;
 803         }
 804         return n;
 805 }
 806
 807 static inline void x86_assign_hw_event(struct perf_event *event,
 808                                 struct cpu_hw_events *cpuc, int i)
 809 {
 810         struct hw_perf_event *hwc = &event->hw;
 811
 812         hwc->idx = cpuc->assign[i];
 813         hwc->last_cpu = smp_processor_id();
 814         hwc->last_tag = ++cpuc->tags[i];
 815
 816         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 817                 hwc->config_base = 0;
 818                 hwc->event_base = 0;
 819         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 820                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 821                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
 822                 hwc->event_base_rdpmc = (hwc->idx - X86_PMC_IDX_FIXED) | 1<<30;
 823         } else {
 824                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 825                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 826                 hwc->event_base_rdpmc = x86_pmu_addr_offset(hwc->idx);
 827         }
 828 }
 829
 830 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 831                                         struct cpu_hw_events *cpuc,
 832                                         int i)
 833 {
 834         return hwc->idx == cpuc->assign[i] &&
 835                 hwc->last_cpu == smp_processor_id() &&
 836                 hwc->last_tag == cpuc->tags[i];
 837 }
 838
 839 static void x86_pmu_start(struct perf_event *event, int flags);
 840
 841 static void x86_pmu_enable(struct pmu *pmu)
 842 {
 843         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 844         struct perf_event *event;
 845         struct hw_perf_event *hwc;
 846         int i, added = cpuc->n_added;
 847
 848         if (!x86_pmu_initialized())
 849                 return;
 850
 851         if (cpuc->enabled)
 852                 return;
 853
 854         if (cpuc->n_added) {
 855                 int n_running = cpuc->n_events - cpuc->n_added;
 856                 /*
 857                  * apply assignment obtained either from
 858                  * hw_perf_group_sched_in() or x86_pmu_enable()
 859                  *
 860                  * step1: save events moving to new counters
 861                  * step2: reprogram moved events into new counters
 862                  */
 863                 for (i = 0; i < n_running; i++) {
 864                         event = cpuc->event_list[i];
 865                         hwc = &event->hw;
 866
 867                         /*
 868                          * we can avoid reprogramming counter if:
 869                          * - assigned same counter as last time
 870                          * - running on same CPU as last time
 871                          * - no other event has used the counter since
 872                          */
 873                         if (hwc->idx == -1 ||
 874                             match_prev_assignment(hwc, cpuc, i))
 875                                 continue;
 876
 877                         /*
 878                          * Ensure we don't accidentally enable a stopped
 879                          * counter simply because we rescheduled.
 880                          */
 881                         if (hwc->state & PERF_HES_STOPPED)
 882                                 hwc->state |= PERF_HES_ARCH;
 883
 884                         x86_pmu_stop(event, PERF_EF_UPDATE);
 885                 }
 886
 887                 for (i = 0; i < cpuc->n_events; i++) {
 888                         event = cpuc->event_list[i];
 889                         hwc = &event->hw;
 890
 891                         if (!match_prev_assignment(hwc, cpuc, i))
 892                                 x86_assign_hw_event(event, cpuc, i);
 893                         else if (i < n_running)
 894                                 continue;
 895
 896                         if (hwc->state & PERF_HES_ARCH)
 897                                 continue;
 898
 899                         x86_pmu_start(event, PERF_EF_RELOAD);
 900                 }
 901                 cpuc->n_added = 0;
 902                 perf_events_lapic_init();
 903         }
 904
 905         cpuc->enabled = 1;
 906         barrier();
 907
 908         x86_pmu.enable_all(added);
 909 }
 910
 911 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 912
 913 /*
 914  * Set the next IRQ period, based on the hwc->period_left value.
 915  * To be called with the event disabled in hw:
 916  */
 917 int x86_perf_event_set_period(struct perf_event *event)
 918 {
 919         struct hw_perf_event *hwc = &event->hw;
 920         s64 left = local64_read(&hwc->period_left);
 921         s64 period = hwc->sample_period;
 922         int ret = 0, idx = hwc->idx;
 923
 924         if (idx == X86_PMC_IDX_FIXED_BTS)
 925                 return 0;
 926
 927         /*
 928          * If we are way outside a reasonable range then just skip forward:
 929          */
 930         if (unlikely(left <= -period)) {
 931                 left = period;
 932                 local64_set(&hwc->period_left, left);
 933                 hwc->last_period = period;
 934                 ret = 1;
 935         }
 936
 937         if (unlikely(left <= 0)) {
 938                 left += period;
 939                 local64_set(&hwc->period_left, left);
 940                 hwc->last_period = period;
 941                 ret = 1;
 942         }
 943         /*
 944          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 945          */
 946         if (unlikely(left < 2))
 947                 left = 2;
 948
 949         if (left > x86_pmu.max_period)
 950                 left = x86_pmu.max_period;
 951
 952         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 953
 954         /*
 955          * The hw event starts counting from this event offset,
 956          * mark it to be able to extra future deltas:
 957          */
 958         local64_set(&hwc->prev_count, (u64)-left);
 959
 960         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 961
 962         /*
 963          * Due to erratum on certan cpu we need
 964          * a second write to be sure the register
 965          * is updated properly
 966          */
 967         if (x86_pmu.perfctr_second_write) {
 968                 wrmsrl(hwc->event_base,
 969                         (u64)(-left) & x86_pmu.cntval_mask);
 970         }
 971
 972         perf_event_update_userpage(event);
 973
 974         return ret;
 975 }
 976
 977 void x86_pmu_enable_event(struct perf_event *event)
 978 {
 979         if (__this_cpu_read(cpu_hw_events.enabled))
 980                 __x86_pmu_enable_event(&event->hw,
 981                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 982 }
 983
 984 /*
 985  * Add a single event to the PMU.
 986  *
 987  * The event is added to the group of enabled events
 988  * but only if it can be scehduled with existing events.
 989  */
 990 static int x86_pmu_add(struct perf_event *event, int flags)
 991 {
 992         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 993         struct hw_perf_event *hwc;
 994         int assign[X86_PMC_IDX_MAX];
 995         int n, n0, ret;
 996
 997         hwc = &event->hw;
 998
 999         perf_pmu_disable(event->pmu);
1000         n0 = cpuc->n_events;
1001         ret = n = collect_events(cpuc, event, false);
1002         if (ret < 0)
1003                 goto out;
1004
1005         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1006         if (!(flags & PERF_EF_START))
1007                 hwc->state |= PERF_HES_ARCH;
1008
1009         /*
1010          * If group events scheduling transaction was started,
1011          * skip the schedulability test here, it will be performed
1012          * at commit time (->commit_txn) as a whole
1013          */
1014         if (cpuc->group_flag & PERF_EVENT_TXN)
1015                 goto done_collect;
1016
1017         ret = x86_pmu.schedule_events(cpuc, n, assign);
1018         if (ret)
1019                 goto out;
1020         /*
1021          * copy new assignment, now we know it is possible
1022          * will be used by hw_perf_enable()
1023          */
1024         memcpy(cpuc->assign, assign, n*sizeof(int));
1025
1026 done_collect:
1027         cpuc->n_events = n;
1028         cpuc->n_added += n - n0;
1029         cpuc->n_txn += n - n0;
1030
1031         ret = 0;
1032 out:
1033         perf_pmu_enable(event->pmu);
1034         return ret;
1035 }
1036
1037 static void x86_pmu_start(struct perf_event *event, int flags)
1038 {
1039         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1040         int idx = event->hw.idx;
1041
1042         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1043                 return;
1044
1045         if (WARN_ON_ONCE(idx == -1))
1046                 return;
1047
1048         if (flags & PERF_EF_RELOAD) {
1049                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1050                 x86_perf_event_set_period(event);
1051         }
1052
1053         event->hw.state = 0;
1054
1055         cpuc->events[idx] = event;
1056         __set_bit(idx, cpuc->active_mask);
1057         __set_bit(idx, cpuc->running);
1058         x86_pmu.enable(event);
1059         perf_event_update_userpage(event);
1060 }
1061
1062 void perf_event_print_debug(void)
1063 {
1064         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1065         u64 pebs;
1066         struct cpu_hw_events *cpuc;
1067         unsigned long flags;
1068         int cpu, idx;
1069
1070         if (!x86_pmu.num_counters)
1071                 return;
1072
1073         local_irq_save(flags);
1074
1075         cpu = smp_processor_id();
1076         cpuc = &per_cpu(cpu_hw_events, cpu);
1077
1078         if (x86_pmu.version >= 2) {
1079                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1080                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1081                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1082                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1083                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1084
1085                 pr_info("\n");
1086                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1087                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1088                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1089                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1090                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1091         }
1092         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1093
1094         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1095                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1096                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1097
1098                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1099
1100                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1101                         cpu, idx, pmc_ctrl);
1102                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1103                         cpu, idx, pmc_count);
1104                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1105                         cpu, idx, prev_left);
1106         }
1107         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1108                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1109
1110                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1111                         cpu, idx, pmc_count);
1112         }
1113         local_irq_restore(flags);
1114 }
1115
1116 void x86_pmu_stop(struct perf_event *event, int flags)
1117 {
1118         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1119         struct hw_perf_event *hwc = &event->hw;
1120
1121         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1122                 x86_pmu.disable(event);
1123                 cpuc->events[hwc->idx] = NULL;
1124                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1125                 hwc->state |= PERF_HES_STOPPED;
1126         }
1127
1128         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1129                 /*
1130                  * Drain the remaining delta count out of a event
1131                  * that we are disabling:
1132                  */
1133                 x86_perf_event_update(event);
1134                 hwc->state |= PERF_HES_UPTODATE;
1135         }
1136 }
1137
1138 static void x86_pmu_del(struct perf_event *event, int flags)
1139 {
1140         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1141         int i;
1142
1143         /*
1144          * If we're called during a txn, we don't need to do anything.
1145          * The events never got scheduled and ->cancel_txn will truncate
1146          * the event_list.
1147          */
1148         if (cpuc->group_flag & PERF_EVENT_TXN)
1149                 return;
1150
1151         x86_pmu_stop(event, PERF_EF_UPDATE);
1152
1153         for (i = 0; i < cpuc->n_events; i++) {
1154                 if (event == cpuc->event_list[i]) {
1155
1156                         if (x86_pmu.put_event_constraints)
1157                                 x86_pmu.put_event_constraints(cpuc, event);
1158
1159                         while (++i < cpuc->n_events)
1160                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1161
1162                         --cpuc->n_events;
1163                         break;
1164                 }
1165         }
1166         perf_event_update_userpage(event);
1167 }
1168
1169 int x86_pmu_handle_irq(struct pt_regs *regs)
1170 {
1171         struct perf_sample_data data;
1172         struct cpu_hw_events *cpuc;
1173         struct perf_event *event;
1174         int idx, handled = 0;
1175         u64 val;
1176
1177         cpuc = &__get_cpu_var(cpu_hw_events);
1178
1179         /*
1180          * Some chipsets need to unmask the LVTPC in a particular spot
1181          * inside the nmi handler.  As a result, the unmasking was pushed
1182          * into all the nmi handlers.
1183          *
1184          * This generic handler doesn't seem to have any issues where the
1185          * unmasking occurs so it was left at the top.
1186          */
1187         apic_write(APIC_LVTPC, APIC_DM_NMI);
1188
1189         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1190                 if (!test_bit(idx, cpuc->active_mask)) {
1191                         /*
1192                          * Though we deactivated the counter some cpus
1193                          * might still deliver spurious interrupts still
1194                          * in flight. Catch them:
1195                          */
1196                         if (__test_and_clear_bit(idx, cpuc->running))
1197                                 handled++;
1198                         continue;
1199                 }
1200
1201                 event = cpuc->events[idx];
1202
1203                 val = x86_perf_event_update(event);
1204                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1205                         continue;
1206
1207                 /*
1208                  * event overflow
1209                  */
1210                 handled++;
1211                 perf_sample_data_init(&data, 0, event->hw.last_period);
1212
1213                 if (!x86_perf_event_set_period(event))
1214                         continue;
1215
1216                 if (perf_event_overflow(event, &data, regs))
1217                         x86_pmu_stop(event, 0);
1218         }
1219
1220         if (handled)
1221                 inc_irq_stat(apic_perf_irqs);
1222
1223         return handled;
1224 }
1225
1226 void perf_events_lapic_init(void)
1227 {
1228         if (!x86_pmu.apic || !x86_pmu_initialized())
1229                 return;
1230
1231         /*
1232          * Always use NMI for PMU
1233          */
1234         apic_write(APIC_LVTPC, APIC_DM_NMI);
1235 }
1236
1237 static int __kprobes
1238 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1239 {
1240         if (!atomic_read(&active_events))
1241                 return NMI_DONE;
1242
1243         return x86_pmu.handle_irq(regs);
1244 }
1245
1246 struct event_constraint emptyconstraint;
1247 struct event_constraint unconstrained;
1248
1249 static int __cpuinit
1250 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1251 {
1252         unsigned int cpu = (long)hcpu;
1253         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1254         int ret = NOTIFY_OK;
1255
1256         switch (action & ~CPU_TASKS_FROZEN) {
1257         case CPU_UP_PREPARE:
1258                 cpuc->kfree_on_online = NULL;
1259                 if (x86_pmu.cpu_prepare)
1260                         ret = x86_pmu.cpu_prepare(cpu);
1261                 break;
1262
1263         case CPU_STARTING:
1264                 if (x86_pmu.attr_rdpmc)
1265                         set_in_cr4(X86_CR4_PCE);
1266                 if (x86_pmu.cpu_starting)
1267                         x86_pmu.cpu_starting(cpu);
1268                 break;
1269
1270         case CPU_ONLINE:
1271                 kfree(cpuc->kfree_on_online);
1272                 break;
1273
1274         case CPU_DYING:
1275                 if (x86_pmu.cpu_dying)
1276                         x86_pmu.cpu_dying(cpu);
1277                 break;
1278
1279         case CPU_UP_CANCELED:
1280         case CPU_DEAD:
1281                 if (x86_pmu.cpu_dead)
1282                         x86_pmu.cpu_dead(cpu);
1283                 break;
1284
1285         default:
1286                 break;
1287         }
1288
1289         return ret;
1290 }
1291
1292 static void __init pmu_check_apic(void)
1293 {
1294         if (cpu_has_apic)
1295                 return;
1296
1297         x86_pmu.apic = 0;
1298         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1299         pr_info("no hardware sampling interrupt available.\n");
1300 }
1301
1302 static struct attribute_group x86_pmu_format_group = {
1303         .name = "format",
1304         .attrs = NULL,
1305 };
1306
1307 static int __init init_hw_perf_events(void)
1308 {
1309         struct x86_pmu_quirk *quirk;
1310         struct event_constraint *c;
1311         int err;
1312
1313         pr_info("Performance Events: ");
1314
1315         switch (boot_cpu_data.x86_vendor) {
1316         case X86_VENDOR_INTEL:
1317                 err = intel_pmu_init();
1318                 break;
1319         case X86_VENDOR_AMD:
1320                 err = amd_pmu_init();
1321                 break;
1322         default:
1323                 return 0;
1324         }
1325         if (err != 0) {
1326                 pr_cont("no PMU driver, software events only.\n");
1327                 return 0;
1328         }
1329
1330         pmu_check_apic();
1331
1332         /* sanity check that the hardware exists or is emulated */
1333         if (!check_hw_exists())
1334                 return 0;
1335
1336         pr_cont("%s PMU driver.\n", x86_pmu.name);
1337
1338         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1339                 quirk->func();
1340
1341         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1342                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1343                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1344                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1345         }
1346         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1347
1348         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1349                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1350                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1351                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1352         }
1353
1354         x86_pmu.intel_ctrl |=
1355                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1356
1357         perf_events_lapic_init();
1358         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1359
1360         unconstrained = (struct event_constraint)
1361                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1362                                    0, x86_pmu.num_counters, 0);
1363
1364         if (x86_pmu.event_constraints) {
1365                 /*
1366                  * event on fixed counter2 (REF_CYCLES) only works on this
1367                  * counter, so do not extend mask to generic counters
1368                  */
1369                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1370                         if (c->cmask != X86_RAW_EVENT_MASK
1371                             || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
1372                                 continue;
1373                         }
1374
1375                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1376                         c->weight += x86_pmu.num_counters;
1377                 }
1378         }
1379
1380         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1381         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1382
1383         pr_info("... version:                %d\n",     x86_pmu.version);
1384         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1385         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1386         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1387         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1388         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1389         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1390
1391         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1392         perf_cpu_notifier(x86_pmu_notifier);
1393
1394         return 0;
1395 }
1396 early_initcall(init_hw_perf_events);
1397
1398 static inline void x86_pmu_read(struct perf_event *event)
1399 {
1400         x86_perf_event_update(event);
1401 }
1402
1403 /*
1404  * Start group events scheduling transaction
1405  * Set the flag to make pmu::enable() not perform the
1406  * schedulability test, it will be performed at commit time
1407  */
1408 static void x86_pmu_start_txn(struct pmu *pmu)
1409 {
1410         perf_pmu_disable(pmu);
1411         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1412         __this_cpu_write(cpu_hw_events.n_txn, 0);
1413 }
1414
1415 /*
1416  * Stop group events scheduling transaction
1417  * Clear the flag and pmu::enable() will perform the
1418  * schedulability test.
1419  */
1420 static void x86_pmu_cancel_txn(struct pmu *pmu)
1421 {
1422         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1423         /*
1424          * Truncate the collected events.
1425          */
1426         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1427         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1428         perf_pmu_enable(pmu);
1429 }
1430
1431 /*
1432  * Commit group events scheduling transaction
1433  * Perform the group schedulability test as a whole
1434  * Return 0 if success
1435  */
1436 static int x86_pmu_commit_txn(struct pmu *pmu)
1437 {
1438         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1439         int assign[X86_PMC_IDX_MAX];
1440         int n, ret;
1441
1442         n = cpuc->n_events;
1443
1444         if (!x86_pmu_initialized())
1445                 return -EAGAIN;
1446
1447         ret = x86_pmu.schedule_events(cpuc, n, assign);
1448         if (ret)
1449                 return ret;
1450
1451         /*
1452          * copy new assignment, now we know it is possible
1453          * will be used by hw_perf_enable()
1454          */
1455         memcpy(cpuc->assign, assign, n*sizeof(int));
1456
1457         cpuc->group_flag &= ~PERF_EVENT_TXN;
1458         perf_pmu_enable(pmu);
1459         return 0;
1460 }
1461 /*
1462  * a fake_cpuc is used to validate event groups. Due to
1463  * the extra reg logic, we need to also allocate a fake
1464  * per_core and per_cpu structure. Otherwise, group events
1465  * using extra reg may conflict without the kernel being
1466  * able to catch this when the last event gets added to
1467  * the group.
1468  */
1469 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1470 {
1471         kfree(cpuc->shared_regs);
1472         kfree(cpuc);
1473 }
1474
1475 static struct cpu_hw_events *allocate_fake_cpuc(void)
1476 {
1477         struct cpu_hw_events *cpuc;
1478         int cpu = raw_smp_processor_id();
1479
1480         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1481         if (!cpuc)
1482                 return ERR_PTR(-ENOMEM);
1483
1484         /* only needed, if we have extra_regs */
1485         if (x86_pmu.extra_regs) {
1486                 cpuc->shared_regs = allocate_shared_regs(cpu);
1487                 if (!cpuc->shared_regs)
1488                         goto error;
1489         }
1490         cpuc->is_fake = 1;
1491         return cpuc;
1492 error:
1493         free_fake_cpuc(cpuc);
1494         return ERR_PTR(-ENOMEM);
1495 }
1496
1497 /*
1498  * validate that we can schedule this event
1499  */
1500 static int validate_event(struct perf_event *event)
1501 {
1502         struct cpu_hw_events *fake_cpuc;
1503         struct event_constraint *c;
1504         int ret = 0;
1505
1506         fake_cpuc = allocate_fake_cpuc();
1507         if (IS_ERR(fake_cpuc))
1508                 return PTR_ERR(fake_cpuc);
1509
1510         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1511
1512         if (!c || !c->weight)
1513                 ret = -EINVAL;
1514
1515         if (x86_pmu.put_event_constraints)
1516                 x86_pmu.put_event_constraints(fake_cpuc, event);
1517
1518         free_fake_cpuc(fake_cpuc);
1519
1520         return ret;
1521 }
1522
1523 /*
1524  * validate a single event group
1525  *
1526  * validation include:
1527  *      - check events are compatible which each other
1528  *      - events do not compete for the same counter
1529  *      - number of events <= number of counters
1530  *
1531  * validation ensures the group can be loaded onto the
1532  * PMU if it was the only group available.
1533  */
1534 static int validate_group(struct perf_event *event)
1535 {
1536         struct perf_event *leader = event->group_leader;
1537         struct cpu_hw_events *fake_cpuc;
1538         int ret = -EINVAL, n;
1539
1540         fake_cpuc = allocate_fake_cpuc();
1541         if (IS_ERR(fake_cpuc))
1542                 return PTR_ERR(fake_cpuc);
1543         /*
1544          * the event is not yet connected with its
1545          * siblings therefore we must first collect
1546          * existing siblings, then add the new event
1547          * before we can simulate the scheduling
1548          */
1549         n = collect_events(fake_cpuc, leader, true);
1550         if (n < 0)
1551                 goto out;
1552
1553         fake_cpuc->n_events = n;
1554         n = collect_events(fake_cpuc, event, false);
1555         if (n < 0)
1556                 goto out;
1557
1558         fake_cpuc->n_events = n;
1559
1560         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1561
1562 out:
1563         free_fake_cpuc(fake_cpuc);
1564         return ret;
1565 }
1566
1567 static int x86_pmu_event_init(struct perf_event *event)
1568 {
1569         struct pmu *tmp;
1570         int err;
1571
1572         switch (event->attr.type) {
1573         case PERF_TYPE_RAW:
1574         case PERF_TYPE_HARDWARE:
1575         case PERF_TYPE_HW_CACHE:
1576                 break;
1577
1578         default:
1579                 return -ENOENT;
1580         }
1581
1582         err = __x86_pmu_event_init(event);
1583         if (!err) {
1584                 /*
1585                  * we temporarily connect event to its pmu
1586                  * such that validate_group() can classify
1587                  * it as an x86 event using is_x86_event()
1588                  */
1589                 tmp = event->pmu;
1590                 event->pmu = &pmu;
1591
1592                 if (event->group_leader != event)
1593                         err = validate_group(event);
1594                 else
1595                         err = validate_event(event);
1596
1597                 event->pmu = tmp;
1598         }
1599         if (err) {
1600                 if (event->destroy)
1601                         event->destroy(event);
1602         }
1603
1604         return err;
1605 }
1606
1607 static int x86_pmu_event_idx(struct perf_event *event)
1608 {
1609         int idx = event->hw.idx;
1610
1611         if (!x86_pmu.attr_rdpmc)
1612                 return 0;
1613
1614         if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) {
1615                 idx -= X86_PMC_IDX_FIXED;
1616                 idx |= 1 << 30;
1617         }
1618
1619         return idx + 1;
1620 }
1621
1622 static ssize_t get_attr_rdpmc(struct device *cdev,
1623                               struct device_attribute *attr,
1624                               char *buf)
1625 {
1626         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1627 }
1628
1629 static void change_rdpmc(void *info)
1630 {
1631         bool enable = !!(unsigned long)info;
1632
1633         if (enable)
1634                 set_in_cr4(X86_CR4_PCE);
1635         else
1636                 clear_in_cr4(X86_CR4_PCE);
1637 }
1638
1639 static ssize_t set_attr_rdpmc(struct device *cdev,
1640                               struct device_attribute *attr,
1641                               const char *buf, size_t count)
1642 {
1643         unsigned long val = simple_strtoul(buf, NULL, 0);
1644
1645         if (!!val != !!x86_pmu.attr_rdpmc) {
1646                 x86_pmu.attr_rdpmc = !!val;
1647                 smp_call_function(change_rdpmc, (void *)val, 1);
1648         }
1649
1650         return count;
1651 }
1652
1653 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1654
1655 static struct attribute *x86_pmu_attrs[] = {
1656         &dev_attr_rdpmc.attr,
1657         NULL,
1658 };
1659
1660 static struct attribute_group x86_pmu_attr_group = {
1661         .attrs = x86_pmu_attrs,
1662 };
1663
1664 static const struct attribute_group *x86_pmu_attr_groups[] = {
1665         &x86_pmu_attr_group,
1666         &x86_pmu_format_group,
1667         NULL,
1668 };
1669
1670 static void x86_pmu_flush_branch_stack(void)
1671 {
1672         if (x86_pmu.flush_branch_stack)
1673                 x86_pmu.flush_branch_stack();
1674 }
1675
1676 static struct pmu pmu = {
1677         .pmu_enable             = x86_pmu_enable,
1678         .pmu_disable            = x86_pmu_disable,
1679
1680         .attr_groups    = x86_pmu_attr_groups,
1681
1682         .event_init     = x86_pmu_event_init,
1683
1684         .add                    = x86_pmu_add,
1685         .del                    = x86_pmu_del,
1686         .start                  = x86_pmu_start,
1687         .stop                   = x86_pmu_stop,
1688         .read                   = x86_pmu_read,
1689
1690         .start_txn      = x86_pmu_start_txn,
1691         .cancel_txn     = x86_pmu_cancel_txn,
1692         .commit_txn     = x86_pmu_commit_txn,
1693
1694         .event_idx      = x86_pmu_event_idx,
1695         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1696 };
1697
1698 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1699 {
1700         userpg->cap_usr_time = 0;
1701         userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;
1702         userpg->pmc_width = x86_pmu.cntval_bits;
1703
1704         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1705                 return;
1706
1707         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1708                 return;
1709
1710         userpg->cap_usr_time = 1;
1711         userpg->time_mult = this_cpu_read(cyc2ns);
1712         userpg->time_shift = CYC2NS_SCALE_FACTOR;
1713         userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
1714 }
1715
1716 /*
1717  * callchain support
1718  */
1719
1720 static int backtrace_stack(void *data, char *name)
1721 {
1722         return 0;
1723 }
1724
1725 static void backtrace_address(void *data, unsigned long addr, int reliable)
1726 {
1727         struct perf_callchain_entry *entry = data;
1728
1729         perf_callchain_store(entry, addr);
1730 }
1731
1732 static const struct stacktrace_ops backtrace_ops = {
1733         .stack                  = backtrace_stack,
1734         .address                = backtrace_address,
1735         .walk_stack             = print_context_stack_bp,
1736 };
1737
1738 void
1739 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1740 {
1741         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1742                 /* TODO: We don't support guest os callchain now */
1743                 return;
1744         }
1745
1746         perf_callchain_store(entry, regs->ip);
1747
1748         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1749 }
1750
1751 static inline int
1752 valid_user_frame(const void __user *fp, unsigned long size)
1753 {
1754         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1755 }
1756
1757 #ifdef CONFIG_COMPAT
1758
1759 #include <asm/compat.h>
1760
1761 static inline int
1762 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1763 {
1764         /* 32-bit process in 64-bit kernel. */
1765         struct stack_frame_ia32 frame;
1766         const void __user *fp;
1767
1768         if (!test_thread_flag(TIF_IA32))
1769                 return 0;
1770
1771         fp = compat_ptr(regs->bp);
1772         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1773                 unsigned long bytes;
1774                 frame.next_frame     = 0;
1775                 frame.return_address = 0;
1776
1777                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1778                 if (bytes != sizeof(frame))
1779                         break;
1780
1781                 if (!valid_user_frame(fp, sizeof(frame)))
1782                         break;
1783
1784                 perf_callchain_store(entry, frame.return_address);
1785                 fp = compat_ptr(frame.next_frame);
1786         }
1787         return 1;
1788 }
1789 #else
1790 static inline int
1791 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1792 {
1793     return 0;
1794 }
1795 #endif
1796
1797 void
1798 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1799 {
1800         struct stack_frame frame;
1801         const void __user *fp;
1802
1803         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1804                 /* TODO: We don't support guest os callchain now */
1805                 return;
1806         }
1807
1808         fp = (void __user *)regs->bp;
1809
1810         perf_callchain_store(entry, regs->ip);
1811
1812         if (!current->mm)
1813                 return;
1814
1815         if (perf_callchain_user32(regs, entry))
1816                 return;
1817
1818         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1819                 unsigned long bytes;
1820                 frame.next_frame             = NULL;
1821                 frame.return_address = 0;
1822
1823                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1824                 if (bytes != sizeof(frame))
1825                         break;
1826
1827                 if (!valid_user_frame(fp, sizeof(frame)))
1828                         break;
1829
1830                 perf_callchain_store(entry, frame.return_address);
1831                 fp = frame.next_frame;
1832         }
1833 }
1834
1835 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1836 {
1837         unsigned long ip;
1838
1839         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1840                 ip = perf_guest_cbs->get_guest_ip();
1841         else
1842                 ip = instruction_pointer(regs);
1843
1844         return ip;
1845 }
1846
1847 unsigned long perf_misc_flags(struct pt_regs *regs)
1848 {
1849         int misc = 0;
1850
1851         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1852                 if (perf_guest_cbs->is_user_mode())
1853                         misc |= PERF_RECORD_MISC_GUEST_USER;
1854                 else
1855                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1856         } else {
1857                 if (user_mode(regs))
1858                         misc |= PERF_RECORD_MISC_USER;
1859                 else
1860                         misc |= PERF_RECORD_MISC_KERNEL;
1861         }
1862
1863         if (regs->flags & PERF_EFLAGS_EXACT)
1864                 misc |= PERF_RECORD_MISC_EXACT_IP;
1865
1866         return misc;
1867 }
1868
1869 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
1870 {
1871         cap->version            = x86_pmu.version;
1872         cap->num_counters_gp    = x86_pmu.num_counters;
1873         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
1874         cap->bit_width_gp       = x86_pmu.cntval_bits;
1875         cap->bit_width_fixed    = x86_pmu.cntval_bits;
1876         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
1877         cap->events_mask_len    = x86_pmu.events_mask_len;
1878 }
1879 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);