2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_chrdev_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_chrdev_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
71 * 0: always panic on uncorrected errors, log corrected errors
72 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
73 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
74 * 3: never panic or SIGBUS, log all errors (for testing only)
76 static int tolerant __read_mostly = 1;
77 static int banks __read_mostly;
78 static int rip_msr __read_mostly;
79 static int mce_bootlog __read_mostly = -1;
80 static int monarch_timeout __read_mostly = -1;
81 static int mce_panic_timeout __read_mostly;
82 static int mce_dont_log_ce __read_mostly;
83 int mce_cmci_disabled __read_mostly;
84 int mce_ignore_ce __read_mostly;
85 int mce_ser __read_mostly;
87 struct mce_bank *mce_banks __read_mostly;
89 /* User mode helper program triggered by machine check event */
90 static unsigned long mce_need_notify;
91 static char mce_helper[128];
92 static char *mce_helper_argv[2] = { mce_helper, NULL };
94 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
96 static DEFINE_PER_CPU(struct mce, mces_seen);
97 static int cpu_missing;
99 /* MCA banks polled by the period polling timer for corrected events */
100 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
101 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
104 static DEFINE_PER_CPU(struct work_struct, mce_work);
107 * CPU/chipset specific EDAC code can register a notifier call here to print
108 * MCE errors in a human-readable form.
110 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
122 m->socketid = cpu_data(m->extcpu).phys_proc_id;
123 m->apicid = cpu_data(m->extcpu).initial_apicid;
124 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127 DEFINE_PER_CPU(struct mce, injectm);
128 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
131 * Lockless MCE logging infrastructure.
132 * This avoids deadlocks on printk locks without having to break locks. Also
133 * separate MCEs from kernel messages to avoid bogus bug reports.
136 static struct mce_log mcelog = {
137 .signature = MCE_LOG_SIGNATURE,
139 .recordlen = sizeof(struct mce),
142 void mce_log(struct mce *mce)
144 unsigned next, entry;
147 /* Emit the trace record: */
148 trace_mce_record(mce);
150 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
151 if (ret == NOTIFY_STOP)
157 entry = rcu_dereference_check_mce(mcelog.next);
161 * When the buffer fills up discard new entries.
162 * Assume that the earlier errors are the more
165 if (entry >= MCE_LOG_LEN) {
166 set_bit(MCE_OVERFLOW,
167 (unsigned long *)&mcelog.flags);
170 /* Old left over entry. Skip: */
171 if (mcelog.entry[entry].finished) {
179 if (cmpxchg(&mcelog.next, entry, next) == entry)
182 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
184 mcelog.entry[entry].finished = 1;
188 set_bit(0, &mce_need_notify);
191 static void drain_mcelog_buffer(void)
193 unsigned int next, i, prev = 0;
195 next = ACCESS_ONCE(mcelog.next);
200 /* drain what was logged during boot */
201 for (i = prev; i < next; i++) {
202 unsigned long start = jiffies;
203 unsigned retries = 1;
205 m = &mcelog.entry[i];
207 while (!m->finished) {
208 if (time_after_eq(jiffies, start + 2*retries))
213 if (!m->finished && retries >= 4) {
214 pr_err("skipping error being logged currently!\n");
219 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
222 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
224 next = cmpxchg(&mcelog.next, prev, 0);
225 } while (next != prev);
229 void mce_register_decode_chain(struct notifier_block *nb)
231 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
232 drain_mcelog_buffer();
234 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
236 void mce_unregister_decode_chain(struct notifier_block *nb)
238 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
240 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
242 static void print_mce(struct mce *m)
246 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
247 m->extcpu, m->mcgstatus, m->bank, m->status);
250 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
251 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
254 if (m->cs == __KERNEL_CS)
255 print_symbol("{%s}", m->ip);
259 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
261 pr_cont("ADDR %llx ", m->addr);
263 pr_cont("MISC %llx ", m->misc);
267 * Note this output is parsed by external tools and old fields
268 * should not be changed.
270 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
271 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
272 cpu_data(m->extcpu).microcode);
275 * Print out human-readable details about the MCE error,
276 * (if the CPU has an implementation for that)
278 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
279 if (ret == NOTIFY_STOP)
282 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
285 #define PANIC_TIMEOUT 5 /* 5 seconds */
287 static atomic_t mce_paniced;
289 static int fake_panic;
290 static atomic_t mce_fake_paniced;
292 /* Panic in progress. Enable interrupts and wait for final IPI */
293 static void wait_for_panic(void)
295 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
299 while (timeout-- > 0)
301 if (panic_timeout == 0)
302 panic_timeout = mce_panic_timeout;
303 panic("Panicing machine check CPU died");
306 static void mce_panic(char *msg, struct mce *final, char *exp)
312 * Make sure only one CPU runs in machine check panic
314 if (atomic_inc_return(&mce_paniced) > 1)
321 /* Don't log too much for fake panic */
322 if (atomic_inc_return(&mce_fake_paniced) > 1)
325 /* First print corrected ones that are still unlogged */
326 for (i = 0; i < MCE_LOG_LEN; i++) {
327 struct mce *m = &mcelog.entry[i];
328 if (!(m->status & MCI_STATUS_VAL))
330 if (!(m->status & MCI_STATUS_UC)) {
333 apei_err = apei_write_mce(m);
336 /* Now print uncorrected but with the final one last */
337 for (i = 0; i < MCE_LOG_LEN; i++) {
338 struct mce *m = &mcelog.entry[i];
339 if (!(m->status & MCI_STATUS_VAL))
341 if (!(m->status & MCI_STATUS_UC))
343 if (!final || memcmp(m, final, sizeof(struct mce))) {
346 apei_err = apei_write_mce(m);
352 apei_err = apei_write_mce(final);
355 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
357 pr_emerg(HW_ERR "Machine check: %s\n", exp);
359 if (panic_timeout == 0)
360 panic_timeout = mce_panic_timeout;
363 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
366 /* Support code for software error injection */
368 static int msr_to_offset(u32 msr)
370 unsigned bank = __this_cpu_read(injectm.bank);
373 return offsetof(struct mce, ip);
374 if (msr == MSR_IA32_MCx_STATUS(bank))
375 return offsetof(struct mce, status);
376 if (msr == MSR_IA32_MCx_ADDR(bank))
377 return offsetof(struct mce, addr);
378 if (msr == MSR_IA32_MCx_MISC(bank))
379 return offsetof(struct mce, misc);
380 if (msr == MSR_IA32_MCG_STATUS)
381 return offsetof(struct mce, mcgstatus);
385 /* MSR access wrappers used for error injection */
386 static u64 mce_rdmsrl(u32 msr)
390 if (__this_cpu_read(injectm.finished)) {
391 int offset = msr_to_offset(msr);
395 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
398 if (rdmsrl_safe(msr, &v)) {
399 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
401 * Return zero in case the access faulted. This should
402 * not happen normally but can happen if the CPU does
403 * something weird, or if the code is buggy.
411 static void mce_wrmsrl(u32 msr, u64 v)
413 if (__this_cpu_read(injectm.finished)) {
414 int offset = msr_to_offset(msr);
417 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
424 * Collect all global (w.r.t. this processor) status about this machine
425 * check into our "mce" struct so that we can use it later to assess
426 * the severity of the problem as we read per-bank specific details.
428 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
432 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
435 * Get the address of the instruction at the time of
436 * the machine check error.
438 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
443 * When in VM86 mode make the cs look like ring 3
444 * always. This is a lie, but it's better than passing
445 * the additional vm86 bit around everywhere.
447 if (v8086_mode(regs))
450 /* Use accurate RIP reporting if available. */
452 m->ip = mce_rdmsrl(rip_msr);
457 * Simple lockless ring to communicate PFNs from the exception handler with the
458 * process context work function. This is vastly simplified because there's
459 * only a single reader and a single writer.
461 #define MCE_RING_SIZE 16 /* we use one entry less */
464 unsigned short start;
466 unsigned long ring[MCE_RING_SIZE];
468 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
470 /* Runs with CPU affinity in workqueue */
471 static int mce_ring_empty(void)
473 struct mce_ring *r = &__get_cpu_var(mce_ring);
475 return r->start == r->end;
478 static int mce_ring_get(unsigned long *pfn)
485 r = &__get_cpu_var(mce_ring);
486 if (r->start == r->end)
488 *pfn = r->ring[r->start];
489 r->start = (r->start + 1) % MCE_RING_SIZE;
496 /* Always runs in MCE context with preempt off */
497 static int mce_ring_add(unsigned long pfn)
499 struct mce_ring *r = &__get_cpu_var(mce_ring);
502 next = (r->end + 1) % MCE_RING_SIZE;
503 if (next == r->start)
505 r->ring[r->end] = pfn;
511 int mce_available(struct cpuinfo_x86 *c)
515 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
518 static void mce_schedule_work(void)
520 if (!mce_ring_empty()) {
521 struct work_struct *work = &__get_cpu_var(mce_work);
522 if (!work_pending(work))
527 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
529 static void mce_irq_work_cb(struct irq_work *entry)
535 static void mce_report_event(struct pt_regs *regs)
537 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
540 * Triggering the work queue here is just an insurance
541 * policy in case the syscall exit notify handler
542 * doesn't run soon enough or ends up running on the
543 * wrong CPU (can happen when audit sleeps)
549 irq_work_queue(&__get_cpu_var(mce_irq_work));
553 * Read ADDR and MISC registers.
555 static void mce_read_aux(struct mce *m, int i)
557 if (m->status & MCI_STATUS_MISCV)
558 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
559 if (m->status & MCI_STATUS_ADDRV) {
560 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
563 * Mask the reported address by the reported granularity.
565 if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
566 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
573 DEFINE_PER_CPU(unsigned, mce_poll_count);
576 * Poll for corrected events or events that happened before reset.
577 * Those are just logged through /dev/mcelog.
579 * This is executed in standard interrupt context.
581 * Note: spec recommends to panic for fatal unsignalled
582 * errors here. However this would be quite problematic --
583 * we would need to reimplement the Monarch handling and
584 * it would mess up the exclusion between exception handler
585 * and poll hander -- * so we skip this for now.
586 * These cases should not happen anyways, or only when the CPU
587 * is already totally * confused. In this case it's likely it will
588 * not fully execute the machine check handler either.
590 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
595 this_cpu_inc(mce_poll_count);
597 mce_gather_info(&m, NULL);
599 for (i = 0; i < banks; i++) {
600 if (!mce_banks[i].ctl || !test_bit(i, *b))
609 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
610 if (!(m.status & MCI_STATUS_VAL))
614 * Uncorrected or signalled events are handled by the exception
615 * handler when it is enabled, so don't process those here.
617 * TBD do the same check for MCI_STATUS_EN here?
619 if (!(flags & MCP_UC) &&
620 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
625 if (!(flags & MCP_TIMESTAMP))
628 * Don't get the IP here because it's unlikely to
629 * have anything to do with the actual error location.
631 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
635 * Clear state for this bank.
637 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
641 * Don't clear MCG_STATUS here because it's only defined for
647 EXPORT_SYMBOL_GPL(machine_check_poll);
650 * Do a quick check if any of the events requires a panic.
651 * This decides if we keep the events around or clear them.
653 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp)
657 for (i = 0; i < banks; i++) {
658 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
659 if (m->status & MCI_STATUS_VAL)
660 __set_bit(i, validp);
661 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
668 * Variable to establish order between CPUs while scanning.
669 * Each CPU spins initially until executing is equal its number.
671 static atomic_t mce_executing;
674 * Defines order of CPUs on entry. First CPU becomes Monarch.
676 static atomic_t mce_callin;
679 * Check if a timeout waiting for other CPUs happened.
681 static int mce_timed_out(u64 *t)
684 * The others already did panic for some reason.
685 * Bail out like in a timeout.
686 * rmb() to tell the compiler that system_state
687 * might have been modified by someone else.
690 if (atomic_read(&mce_paniced))
692 if (!monarch_timeout)
694 if ((s64)*t < SPINUNIT) {
695 /* CHECKME: Make panic default for 1 too? */
697 mce_panic("Timeout synchronizing machine check over CPUs",
704 touch_nmi_watchdog();
709 * The Monarch's reign. The Monarch is the CPU who entered
710 * the machine check handler first. It waits for the others to
711 * raise the exception too and then grades them. When any
712 * error is fatal panic. Only then let the others continue.
714 * The other CPUs entering the MCE handler will be controlled by the
715 * Monarch. They are called Subjects.
717 * This way we prevent any potential data corruption in a unrecoverable case
718 * and also makes sure always all CPU's errors are examined.
720 * Also this detects the case of a machine check event coming from outer
721 * space (not detected by any CPUs) In this case some external agent wants
722 * us to shut down, so panic too.
724 * The other CPUs might still decide to panic if the handler happens
725 * in a unrecoverable place, but in this case the system is in a semi-stable
726 * state and won't corrupt anything by itself. It's ok to let the others
727 * continue for a bit first.
729 * All the spin loops have timeouts; when a timeout happens a CPU
730 * typically elects itself to be Monarch.
732 static void mce_reign(void)
735 struct mce *m = NULL;
736 int global_worst = 0;
741 * This CPU is the Monarch and the other CPUs have run
742 * through their handlers.
743 * Grade the severity of the errors of all the CPUs.
745 for_each_possible_cpu(cpu) {
746 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
748 if (severity > global_worst) {
750 global_worst = severity;
751 m = &per_cpu(mces_seen, cpu);
756 * Cannot recover? Panic here then.
757 * This dumps all the mces in the log buffer and stops the
760 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
761 mce_panic("Fatal Machine check", m, msg);
764 * For UC somewhere we let the CPU who detects it handle it.
765 * Also must let continue the others, otherwise the handling
766 * CPU could deadlock on a lock.
770 * No machine check event found. Must be some external
771 * source or one CPU is hung. Panic.
773 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
774 mce_panic("Machine check from unknown source", NULL, NULL);
777 * Now clear all the mces_seen so that they don't reappear on
780 for_each_possible_cpu(cpu)
781 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
784 static atomic_t global_nwo;
787 * Start of Monarch synchronization. This waits until all CPUs have
788 * entered the exception handler and then determines if any of them
789 * saw a fatal event that requires panic. Then it executes them
790 * in the entry order.
791 * TBD double check parallel CPU hotunplug
793 static int mce_start(int *no_way_out)
796 int cpus = num_online_cpus();
797 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
802 atomic_add(*no_way_out, &global_nwo);
804 * global_nwo should be updated before mce_callin
807 order = atomic_inc_return(&mce_callin);
812 while (atomic_read(&mce_callin) != cpus) {
813 if (mce_timed_out(&timeout)) {
814 atomic_set(&global_nwo, 0);
821 * mce_callin should be read before global_nwo
827 * Monarch: Starts executing now, the others wait.
829 atomic_set(&mce_executing, 1);
832 * Subject: Now start the scanning loop one by one in
833 * the original callin order.
834 * This way when there are any shared banks it will be
835 * only seen by one CPU before cleared, avoiding duplicates.
837 while (atomic_read(&mce_executing) < order) {
838 if (mce_timed_out(&timeout)) {
839 atomic_set(&global_nwo, 0);
847 * Cache the global no_way_out state.
849 *no_way_out = atomic_read(&global_nwo);
855 * Synchronize between CPUs after main scanning loop.
856 * This invokes the bulk of the Monarch processing.
858 static int mce_end(int order)
861 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
869 * Allow others to run.
871 atomic_inc(&mce_executing);
874 /* CHECKME: Can this race with a parallel hotplug? */
875 int cpus = num_online_cpus();
878 * Monarch: Wait for everyone to go through their scanning
881 while (atomic_read(&mce_executing) <= cpus) {
882 if (mce_timed_out(&timeout))
892 * Subject: Wait for Monarch to finish.
894 while (atomic_read(&mce_executing) != 0) {
895 if (mce_timed_out(&timeout))
901 * Don't reset anything. That's done by the Monarch.
907 * Reset all global state.
910 atomic_set(&global_nwo, 0);
911 atomic_set(&mce_callin, 0);
915 * Let others run again.
917 atomic_set(&mce_executing, 0);
922 * Check if the address reported by the CPU is in a format we can parse.
923 * It would be possible to add code for most other cases, but all would
924 * be somewhat complicated (e.g. segment offset would require an instruction
925 * parser). So only support physical addresses up to page granuality for now.
927 static int mce_usable_address(struct mce *m)
929 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
931 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
933 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
938 static void mce_clear_state(unsigned long *toclear)
942 for (i = 0; i < banks; i++) {
943 if (test_bit(i, toclear))
944 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
949 * Need to save faulting physical address associated with a process
950 * in the machine check handler some place where we can grab it back
951 * later in mce_notify_process()
953 #define MCE_INFO_MAX 16
957 struct task_struct *t;
960 } mce_info[MCE_INFO_MAX];
962 static void mce_save_info(__u64 addr, int c)
966 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
967 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
975 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
978 static struct mce_info *mce_find_info(void)
982 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
983 if (atomic_read(&mi->inuse) && mi->t == current)
988 static void mce_clear_info(struct mce_info *mi)
990 atomic_set(&mi->inuse, 0);
994 * The actual machine check handler. This only handles real
995 * exceptions when something got corrupted coming in through int 18.
997 * This is executed in NMI context not subject to normal locking rules. This
998 * implies that most kernel services cannot be safely used. Don't even
999 * think about putting a printk in there!
1001 * On Intel systems this is entered on all CPUs in parallel through
1002 * MCE broadcast. However some CPUs might be broken beyond repair,
1003 * so be always careful when synchronizing with others.
1005 void do_machine_check(struct pt_regs *regs, long error_code)
1007 struct mce m, *final;
1012 * Establish sequential order between the CPUs entering the machine
1017 * If no_way_out gets set, there is no safe way to recover from this
1018 * MCE. If tolerant is cranked up, we'll try anyway.
1022 * If kill_it gets set, there might be a way to recover from this
1026 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1027 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1028 char *msg = "Unknown";
1030 atomic_inc(&mce_entry);
1032 this_cpu_inc(mce_exception_count);
1037 mce_gather_info(&m, regs);
1039 final = &__get_cpu_var(mces_seen);
1042 memset(valid_banks, 0, sizeof(valid_banks));
1043 no_way_out = mce_no_way_out(&m, &msg, valid_banks);
1048 * When no restart IP might need to kill or panic.
1049 * Assume the worst for now, but if we find the
1050 * severity is MCE_AR_SEVERITY we have other options.
1052 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1056 * Go through all the banks in exclusion of the other CPUs.
1057 * This way we don't report duplicated events on shared banks
1058 * because the first one to see it will clear it.
1060 order = mce_start(&no_way_out);
1061 for (i = 0; i < banks; i++) {
1062 __clear_bit(i, toclear);
1063 if (!test_bit(i, valid_banks))
1065 if (!mce_banks[i].ctl)
1072 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1073 if ((m.status & MCI_STATUS_VAL) == 0)
1077 * Non uncorrected or non signaled errors are handled by
1078 * machine_check_poll. Leave them alone, unless this panics.
1080 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1085 * Set taint even when machine check was not enabled.
1087 add_taint(TAINT_MACHINE_CHECK);
1089 severity = mce_severity(&m, tolerant, NULL);
1092 * When machine check was for corrected handler don't touch,
1093 * unless we're panicing.
1095 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1097 __set_bit(i, toclear);
1098 if (severity == MCE_NO_SEVERITY) {
1100 * Machine check event was not enabled. Clear, but
1106 mce_read_aux(&m, i);
1109 * Action optional error. Queue address for later processing.
1110 * When the ring overflows we just ignore the AO error.
1111 * RED-PEN add some logging mechanism when
1112 * usable_address or mce_add_ring fails.
1113 * RED-PEN don't ignore overflow for tolerant == 0
1115 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1116 mce_ring_add(m.addr >> PAGE_SHIFT);
1120 if (severity > worst) {
1126 /* mce_clear_state will clear *final, save locally for use later */
1130 mce_clear_state(toclear);
1133 * Do most of the synchronization with other CPUs.
1134 * When there's any problem use only local no_way_out state.
1136 if (mce_end(order) < 0)
1137 no_way_out = worst >= MCE_PANIC_SEVERITY;
1140 * At insane "tolerant" levels we take no action. Otherwise
1141 * we only die if we have no other choice. For less serious
1142 * issues we try to recover, or limit damage to the current
1147 mce_panic("Fatal machine check on current CPU", &m, msg);
1148 if (worst == MCE_AR_SEVERITY) {
1149 /* schedule action before return to userland */
1150 mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV);
1151 set_thread_flag(TIF_MCE_NOTIFY);
1152 } else if (kill_it) {
1153 force_sig(SIGBUS, current);
1158 mce_report_event(regs);
1159 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1161 atomic_dec(&mce_entry);
1164 EXPORT_SYMBOL_GPL(do_machine_check);
1166 #ifndef CONFIG_MEMORY_FAILURE
1167 int memory_failure(unsigned long pfn, int vector, int flags)
1169 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1170 BUG_ON(flags & MF_ACTION_REQUIRED);
1171 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1172 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1180 * Called in process context that interrupted by MCE and marked with
1181 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1182 * This code is allowed to sleep.
1183 * Attempt possible recovery such as calling the high level VM handler to
1184 * process any corrupted pages, and kill/signal current process if required.
1185 * Action required errors are handled here.
1187 void mce_notify_process(void)
1190 struct mce_info *mi = mce_find_info();
1191 int flags = MF_ACTION_REQUIRED;
1194 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1195 pfn = mi->paddr >> PAGE_SHIFT;
1197 clear_thread_flag(TIF_MCE_NOTIFY);
1199 pr_err("Uncorrected hardware memory error in user-access at %llx",
1202 * We must call memory_failure() here even if the current process is
1203 * doomed. We still need to mark the page as poisoned and alert any
1204 * other users of the page.
1206 if (!mi->restartable)
1207 flags |= MF_MUST_KILL;
1208 if (memory_failure(pfn, MCE_VECTOR, flags) < 0) {
1209 pr_err("Memory error not recovered");
1210 force_sig(SIGBUS, current);
1216 * Action optional processing happens here (picking up
1217 * from the list of faulting pages that do_machine_check()
1218 * placed into the "ring").
1220 static void mce_process_work(struct work_struct *dummy)
1224 while (mce_ring_get(&pfn))
1225 memory_failure(pfn, MCE_VECTOR, 0);
1228 #ifdef CONFIG_X86_MCE_INTEL
1230 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1231 * @cpu: The CPU on which the event occurred.
1232 * @status: Event status information
1234 * This function should be called by the thermal interrupt after the
1235 * event has been processed and the decision was made to log the event
1238 * The status parameter will be saved to the 'status' field of 'struct mce'
1239 * and historically has been the register value of the
1240 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1242 void mce_log_therm_throt_event(__u64 status)
1247 m.bank = MCE_THERMAL_BANK;
1251 #endif /* CONFIG_X86_MCE_INTEL */
1254 * Periodic polling timer for "silent" machine check errors. If the
1255 * poller finds an MCE, poll 2x faster. When the poller finds no more
1256 * errors, poll 2x slower (up to check_interval seconds).
1258 static unsigned long check_interval = 5 * 60; /* 5 minutes */
1260 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1261 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1263 static void mce_timer_fn(unsigned long data)
1265 struct timer_list *t = &__get_cpu_var(mce_timer);
1268 WARN_ON(smp_processor_id() != data);
1270 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1271 machine_check_poll(MCP_TIMESTAMP,
1272 &__get_cpu_var(mce_poll_banks));
1276 * Alert userspace if needed. If we logged an MCE, reduce the
1277 * polling interval, otherwise increase the polling interval.
1279 iv = __this_cpu_read(mce_next_interval);
1280 if (mce_notify_irq())
1281 iv = max(iv / 2, (unsigned long) HZ/100);
1283 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1284 __this_cpu_write(mce_next_interval, iv);
1286 t->expires = jiffies + iv;
1287 add_timer_on(t, smp_processor_id());
1290 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1291 static void mce_timer_delete_all(void)
1295 for_each_online_cpu(cpu)
1296 del_timer_sync(&per_cpu(mce_timer, cpu));
1299 static void mce_do_trigger(struct work_struct *work)
1301 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1304 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1307 * Notify the user(s) about new machine check events.
1308 * Can be called from interrupt context, but not from machine check/NMI
1311 int mce_notify_irq(void)
1313 /* Not more than two messages every minute */
1314 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1316 if (test_and_clear_bit(0, &mce_need_notify)) {
1317 /* wake processes polling /dev/mcelog */
1318 wake_up_interruptible(&mce_chrdev_wait);
1321 * There is no risk of missing notifications because
1322 * work_pending is always cleared before the function is
1325 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1326 schedule_work(&mce_trigger_work);
1328 if (__ratelimit(&ratelimit))
1329 pr_info(HW_ERR "Machine check events logged\n");
1335 EXPORT_SYMBOL_GPL(mce_notify_irq);
1337 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1341 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1344 for (i = 0; i < banks; i++) {
1345 struct mce_bank *b = &mce_banks[i];
1354 * Initialize Machine Checks for a CPU.
1356 static int __cpuinit __mcheck_cpu_cap_init(void)
1361 rdmsrl(MSR_IA32_MCG_CAP, cap);
1363 b = cap & MCG_BANKCNT_MASK;
1365 pr_info("CPU supports %d MCE banks\n", b);
1367 if (b > MAX_NR_BANKS) {
1368 pr_warn("Using only %u machine check banks out of %u\n",
1373 /* Don't support asymmetric configurations today */
1374 WARN_ON(banks != 0 && b != banks);
1377 int err = __mcheck_cpu_mce_banks_init();
1383 /* Use accurate RIP reporting if available. */
1384 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1385 rip_msr = MSR_IA32_MCG_EIP;
1387 if (cap & MCG_SER_P)
1393 static void __mcheck_cpu_init_generic(void)
1395 mce_banks_t all_banks;
1400 * Log the machine checks left over from the previous reset.
1402 bitmap_fill(all_banks, MAX_NR_BANKS);
1403 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1405 set_in_cr4(X86_CR4_MCE);
1407 rdmsrl(MSR_IA32_MCG_CAP, cap);
1408 if (cap & MCG_CTL_P)
1409 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1411 for (i = 0; i < banks; i++) {
1412 struct mce_bank *b = &mce_banks[i];
1416 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1417 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1421 /* Add per CPU specific workarounds here */
1422 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1424 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1425 pr_info("unknown CPU type - not enabling MCE support\n");
1429 /* This should be disabled by the BIOS, but isn't always */
1430 if (c->x86_vendor == X86_VENDOR_AMD) {
1431 if (c->x86 == 15 && banks > 4) {
1433 * disable GART TBL walk error reporting, which
1434 * trips off incorrectly with the IOMMU & 3ware
1437 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1439 if (c->x86 <= 17 && mce_bootlog < 0) {
1441 * Lots of broken BIOS around that don't clear them
1442 * by default and leave crap in there. Don't log:
1447 * Various K7s with broken bank 0 around. Always disable
1450 if (c->x86 == 6 && banks > 0)
1451 mce_banks[0].ctl = 0;
1454 * Turn off MC4_MISC thresholding banks on those models since
1455 * they're not supported there.
1457 if (c->x86 == 0x15 &&
1458 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1463 0x00000413, /* MC4_MISC0 */
1464 0xc0000408, /* MC4_MISC1 */
1467 rdmsrl(MSR_K7_HWCR, hwcr);
1469 /* McStatusWrEn has to be set */
1470 need_toggle = !(hwcr & BIT(18));
1473 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1475 for (i = 0; i < ARRAY_SIZE(msrs); i++) {
1476 rdmsrl(msrs[i], val);
1479 if (val & BIT_64(62)) {
1481 wrmsrl(msrs[i], val);
1485 /* restore old settings */
1487 wrmsrl(MSR_K7_HWCR, hwcr);
1491 if (c->x86_vendor == X86_VENDOR_INTEL) {
1493 * SDM documents that on family 6 bank 0 should not be written
1494 * because it aliases to another special BIOS controlled
1496 * But it's not aliased anymore on model 0x1a+
1497 * Don't ignore bank 0 completely because there could be a
1498 * valid event later, merely don't write CTL0.
1501 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1502 mce_banks[0].init = 0;
1505 * All newer Intel systems support MCE broadcasting. Enable
1506 * synchronization with a one second timeout.
1508 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1509 monarch_timeout < 0)
1510 monarch_timeout = USEC_PER_SEC;
1513 * There are also broken BIOSes on some Pentium M and
1516 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1519 if (monarch_timeout < 0)
1520 monarch_timeout = 0;
1521 if (mce_bootlog != 0)
1522 mce_panic_timeout = 30;
1527 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1532 switch (c->x86_vendor) {
1533 case X86_VENDOR_INTEL:
1534 intel_p5_mcheck_init(c);
1537 case X86_VENDOR_CENTAUR:
1538 winchip_mcheck_init(c);
1546 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1548 switch (c->x86_vendor) {
1549 case X86_VENDOR_INTEL:
1550 mce_intel_feature_init(c);
1552 case X86_VENDOR_AMD:
1553 mce_amd_feature_init(c);
1560 static void __mcheck_cpu_init_timer(void)
1562 struct timer_list *t = &__get_cpu_var(mce_timer);
1563 unsigned long iv = check_interval * HZ;
1565 setup_timer(t, mce_timer_fn, smp_processor_id());
1570 __this_cpu_write(mce_next_interval, iv);
1573 t->expires = round_jiffies(jiffies + iv);
1574 add_timer_on(t, smp_processor_id());
1577 /* Handle unconfigured int18 (should never happen) */
1578 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1580 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1581 smp_processor_id());
1584 /* Call the installed machine check handler for this CPU setup. */
1585 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1586 unexpected_machine_check;
1589 * Called for each booted CPU to set up machine checks.
1590 * Must be called with preempt off:
1592 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1597 if (__mcheck_cpu_ancient_init(c))
1600 if (!mce_available(c))
1603 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1608 machine_check_vector = do_machine_check;
1610 __mcheck_cpu_init_generic();
1611 __mcheck_cpu_init_vendor(c);
1612 __mcheck_cpu_init_timer();
1613 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1614 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1618 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1621 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1622 static int mce_chrdev_open_count; /* #times opened */
1623 static int mce_chrdev_open_exclu; /* already open exclusive? */
1625 static int mce_chrdev_open(struct inode *inode, struct file *file)
1627 spin_lock(&mce_chrdev_state_lock);
1629 if (mce_chrdev_open_exclu ||
1630 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1631 spin_unlock(&mce_chrdev_state_lock);
1636 if (file->f_flags & O_EXCL)
1637 mce_chrdev_open_exclu = 1;
1638 mce_chrdev_open_count++;
1640 spin_unlock(&mce_chrdev_state_lock);
1642 return nonseekable_open(inode, file);
1645 static int mce_chrdev_release(struct inode *inode, struct file *file)
1647 spin_lock(&mce_chrdev_state_lock);
1649 mce_chrdev_open_count--;
1650 mce_chrdev_open_exclu = 0;
1652 spin_unlock(&mce_chrdev_state_lock);
1657 static void collect_tscs(void *data)
1659 unsigned long *cpu_tsc = (unsigned long *)data;
1661 rdtscll(cpu_tsc[smp_processor_id()]);
1664 static int mce_apei_read_done;
1666 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1667 static int __mce_read_apei(char __user **ubuf, size_t usize)
1673 if (usize < sizeof(struct mce))
1676 rc = apei_read_mce(&m, &record_id);
1677 /* Error or no more MCE record */
1679 mce_apei_read_done = 1;
1681 * When ERST is disabled, mce_chrdev_read() should return
1682 * "no record" instead of "no device."
1689 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1692 * In fact, we should have cleared the record after that has
1693 * been flushed to the disk or sent to network in
1694 * /sbin/mcelog, but we have no interface to support that now,
1695 * so just clear it to avoid duplication.
1697 rc = apei_clear_mce(record_id);
1699 mce_apei_read_done = 1;
1702 *ubuf += sizeof(struct mce);
1707 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1708 size_t usize, loff_t *off)
1710 char __user *buf = ubuf;
1711 unsigned long *cpu_tsc;
1712 unsigned prev, next;
1715 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1719 mutex_lock(&mce_chrdev_read_mutex);
1721 if (!mce_apei_read_done) {
1722 err = __mce_read_apei(&buf, usize);
1723 if (err || buf != ubuf)
1727 next = rcu_dereference_check_mce(mcelog.next);
1729 /* Only supports full reads right now */
1731 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1737 for (i = prev; i < next; i++) {
1738 unsigned long start = jiffies;
1739 struct mce *m = &mcelog.entry[i];
1741 while (!m->finished) {
1742 if (time_after_eq(jiffies, start + 2)) {
1743 memset(m, 0, sizeof(*m));
1749 err |= copy_to_user(buf, m, sizeof(*m));
1755 memset(mcelog.entry + prev, 0,
1756 (next - prev) * sizeof(struct mce));
1758 next = cmpxchg(&mcelog.next, prev, 0);
1759 } while (next != prev);
1761 synchronize_sched();
1764 * Collect entries that were still getting written before the
1767 on_each_cpu(collect_tscs, cpu_tsc, 1);
1769 for (i = next; i < MCE_LOG_LEN; i++) {
1770 struct mce *m = &mcelog.entry[i];
1772 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1773 err |= copy_to_user(buf, m, sizeof(*m));
1776 memset(m, 0, sizeof(*m));
1784 mutex_unlock(&mce_chrdev_read_mutex);
1787 return err ? err : buf - ubuf;
1790 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1792 poll_wait(file, &mce_chrdev_wait, wait);
1793 if (rcu_access_index(mcelog.next))
1794 return POLLIN | POLLRDNORM;
1795 if (!mce_apei_read_done && apei_check_mce())
1796 return POLLIN | POLLRDNORM;
1800 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1803 int __user *p = (int __user *)arg;
1805 if (!capable(CAP_SYS_ADMIN))
1809 case MCE_GET_RECORD_LEN:
1810 return put_user(sizeof(struct mce), p);
1811 case MCE_GET_LOG_LEN:
1812 return put_user(MCE_LOG_LEN, p);
1813 case MCE_GETCLEAR_FLAGS: {
1817 flags = mcelog.flags;
1818 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1820 return put_user(flags, p);
1827 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1828 size_t usize, loff_t *off);
1830 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1831 const char __user *ubuf,
1832 size_t usize, loff_t *off))
1836 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1838 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1839 size_t usize, loff_t *off)
1842 return mce_write(filp, ubuf, usize, off);
1847 static const struct file_operations mce_chrdev_ops = {
1848 .open = mce_chrdev_open,
1849 .release = mce_chrdev_release,
1850 .read = mce_chrdev_read,
1851 .write = mce_chrdev_write,
1852 .poll = mce_chrdev_poll,
1853 .unlocked_ioctl = mce_chrdev_ioctl,
1854 .llseek = no_llseek,
1857 static struct miscdevice mce_chrdev_device = {
1864 * mce=off Disables machine check
1865 * mce=no_cmci Disables CMCI
1866 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1867 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1868 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1869 * monarchtimeout is how long to wait for other CPUs on machine
1870 * check, or 0 to not wait
1871 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1872 * mce=nobootlog Don't log MCEs from before booting.
1874 static int __init mcheck_enable(char *str)
1882 if (!strcmp(str, "off"))
1884 else if (!strcmp(str, "no_cmci"))
1885 mce_cmci_disabled = 1;
1886 else if (!strcmp(str, "dont_log_ce"))
1887 mce_dont_log_ce = 1;
1888 else if (!strcmp(str, "ignore_ce"))
1890 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1891 mce_bootlog = (str[0] == 'b');
1892 else if (isdigit(str[0])) {
1893 get_option(&str, &tolerant);
1896 get_option(&str, &monarch_timeout);
1899 pr_info("mce argument %s ignored. Please use /sys\n", str);
1904 __setup("mce", mcheck_enable);
1906 int __init mcheck_init(void)
1908 mcheck_intel_therm_init();
1914 * mce_syscore: PM support
1918 * Disable machine checks on suspend and shutdown. We can't really handle
1921 static int mce_disable_error_reporting(void)
1925 for (i = 0; i < banks; i++) {
1926 struct mce_bank *b = &mce_banks[i];
1929 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1934 static int mce_syscore_suspend(void)
1936 return mce_disable_error_reporting();
1939 static void mce_syscore_shutdown(void)
1941 mce_disable_error_reporting();
1945 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1946 * Only one CPU is active at this time, the others get re-added later using
1949 static void mce_syscore_resume(void)
1951 __mcheck_cpu_init_generic();
1952 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1955 static struct syscore_ops mce_syscore_ops = {
1956 .suspend = mce_syscore_suspend,
1957 .shutdown = mce_syscore_shutdown,
1958 .resume = mce_syscore_resume,
1962 * mce_device: Sysfs support
1965 static void mce_cpu_restart(void *data)
1967 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1969 __mcheck_cpu_init_generic();
1970 __mcheck_cpu_init_timer();
1973 /* Reinit MCEs after user configuration changes */
1974 static void mce_restart(void)
1976 mce_timer_delete_all();
1977 on_each_cpu(mce_cpu_restart, NULL, 1);
1980 /* Toggle features for corrected errors */
1981 static void mce_disable_cmci(void *data)
1983 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1988 static void mce_enable_ce(void *all)
1990 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1995 __mcheck_cpu_init_timer();
1998 static struct bus_type mce_subsys = {
1999 .name = "machinecheck",
2000 .dev_name = "machinecheck",
2003 DEFINE_PER_CPU(struct device *, mce_device);
2006 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
2008 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2010 return container_of(attr, struct mce_bank, attr);
2013 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2016 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2019 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2020 const char *buf, size_t size)
2024 if (strict_strtoull(buf, 0, &new) < 0)
2027 attr_to_bank(attr)->ctl = new;
2034 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2036 strcpy(buf, mce_helper);
2038 return strlen(mce_helper) + 1;
2041 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2042 const char *buf, size_t siz)
2046 strncpy(mce_helper, buf, sizeof(mce_helper));
2047 mce_helper[sizeof(mce_helper)-1] = 0;
2048 p = strchr(mce_helper, '\n');
2053 return strlen(mce_helper) + !!p;
2056 static ssize_t set_ignore_ce(struct device *s,
2057 struct device_attribute *attr,
2058 const char *buf, size_t size)
2062 if (strict_strtoull(buf, 0, &new) < 0)
2065 if (mce_ignore_ce ^ !!new) {
2067 /* disable ce features */
2068 mce_timer_delete_all();
2069 on_each_cpu(mce_disable_cmci, NULL, 1);
2072 /* enable ce features */
2074 on_each_cpu(mce_enable_ce, (void *)1, 1);
2080 static ssize_t set_cmci_disabled(struct device *s,
2081 struct device_attribute *attr,
2082 const char *buf, size_t size)
2086 if (strict_strtoull(buf, 0, &new) < 0)
2089 if (mce_cmci_disabled ^ !!new) {
2092 on_each_cpu(mce_disable_cmci, NULL, 1);
2093 mce_cmci_disabled = 1;
2096 mce_cmci_disabled = 0;
2097 on_each_cpu(mce_enable_ce, NULL, 1);
2103 static ssize_t store_int_with_restart(struct device *s,
2104 struct device_attribute *attr,
2105 const char *buf, size_t size)
2107 ssize_t ret = device_store_int(s, attr, buf, size);
2112 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2113 static DEVICE_INT_ATTR(tolerant, 0644, tolerant);
2114 static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
2115 static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
2117 static struct dev_ext_attribute dev_attr_check_interval = {
2118 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2122 static struct dev_ext_attribute dev_attr_ignore_ce = {
2123 __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce),
2127 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2128 __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled),
2132 static struct device_attribute *mce_device_attrs[] = {
2133 &dev_attr_tolerant.attr,
2134 &dev_attr_check_interval.attr,
2136 &dev_attr_monarch_timeout.attr,
2137 &dev_attr_dont_log_ce.attr,
2138 &dev_attr_ignore_ce.attr,
2139 &dev_attr_cmci_disabled.attr,
2143 static cpumask_var_t mce_device_initialized;
2145 static void mce_device_release(struct device *dev)
2150 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2151 static __cpuinit int mce_device_create(unsigned int cpu)
2157 if (!mce_available(&boot_cpu_data))
2160 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2164 dev->bus = &mce_subsys;
2165 dev->release = &mce_device_release;
2167 err = device_register(dev);
2171 for (i = 0; mce_device_attrs[i]; i++) {
2172 err = device_create_file(dev, mce_device_attrs[i]);
2176 for (j = 0; j < banks; j++) {
2177 err = device_create_file(dev, &mce_banks[j].attr);
2181 cpumask_set_cpu(cpu, mce_device_initialized);
2182 per_cpu(mce_device, cpu) = dev;
2187 device_remove_file(dev, &mce_banks[j].attr);
2190 device_remove_file(dev, mce_device_attrs[i]);
2192 device_unregister(dev);
2197 static __cpuinit void mce_device_remove(unsigned int cpu)
2199 struct device *dev = per_cpu(mce_device, cpu);
2202 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2205 for (i = 0; mce_device_attrs[i]; i++)
2206 device_remove_file(dev, mce_device_attrs[i]);
2208 for (i = 0; i < banks; i++)
2209 device_remove_file(dev, &mce_banks[i].attr);
2211 device_unregister(dev);
2212 cpumask_clear_cpu(cpu, mce_device_initialized);
2213 per_cpu(mce_device, cpu) = NULL;
2216 /* Make sure there are no machine checks on offlined CPUs. */
2217 static void __cpuinit mce_disable_cpu(void *h)
2219 unsigned long action = *(unsigned long *)h;
2222 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2225 if (!(action & CPU_TASKS_FROZEN))
2227 for (i = 0; i < banks; i++) {
2228 struct mce_bank *b = &mce_banks[i];
2231 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2235 static void __cpuinit mce_reenable_cpu(void *h)
2237 unsigned long action = *(unsigned long *)h;
2240 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2243 if (!(action & CPU_TASKS_FROZEN))
2245 for (i = 0; i < banks; i++) {
2246 struct mce_bank *b = &mce_banks[i];
2249 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2253 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2254 static int __cpuinit
2255 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2257 unsigned int cpu = (unsigned long)hcpu;
2258 struct timer_list *t = &per_cpu(mce_timer, cpu);
2262 case CPU_ONLINE_FROZEN:
2263 mce_device_create(cpu);
2264 if (threshold_cpu_callback)
2265 threshold_cpu_callback(action, cpu);
2268 case CPU_DEAD_FROZEN:
2269 if (threshold_cpu_callback)
2270 threshold_cpu_callback(action, cpu);
2271 mce_device_remove(cpu);
2273 case CPU_DOWN_PREPARE:
2274 case CPU_DOWN_PREPARE_FROZEN:
2276 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2278 case CPU_DOWN_FAILED:
2279 case CPU_DOWN_FAILED_FROZEN:
2280 if (!mce_ignore_ce && check_interval) {
2281 t->expires = round_jiffies(jiffies +
2282 per_cpu(mce_next_interval, cpu));
2283 add_timer_on(t, cpu);
2285 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2288 /* intentionally ignoring frozen here */
2289 cmci_rediscover(cpu);
2295 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2296 .notifier_call = mce_cpu_callback,
2299 static __init void mce_init_banks(void)
2303 for (i = 0; i < banks; i++) {
2304 struct mce_bank *b = &mce_banks[i];
2305 struct device_attribute *a = &b->attr;
2307 sysfs_attr_init(&a->attr);
2308 a->attr.name = b->attrname;
2309 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2311 a->attr.mode = 0644;
2312 a->show = show_bank;
2313 a->store = set_bank;
2317 static __init int mcheck_init_device(void)
2322 if (!mce_available(&boot_cpu_data))
2325 zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL);
2329 err = subsys_system_register(&mce_subsys, NULL);
2333 for_each_online_cpu(i) {
2334 err = mce_device_create(i);
2339 register_syscore_ops(&mce_syscore_ops);
2340 register_hotcpu_notifier(&mce_cpu_notifier);
2342 /* register character device /dev/mcelog */
2343 misc_register(&mce_chrdev_device);
2347 device_initcall_sync(mcheck_init_device);
2350 * Old style boot options parsing. Only for compatibility.
2352 static int __init mcheck_disable(char *str)
2357 __setup("nomce", mcheck_disable);
2359 #ifdef CONFIG_DEBUG_FS
2360 struct dentry *mce_get_debugfs_dir(void)
2362 static struct dentry *dmce;
2365 dmce = debugfs_create_dir("mce", NULL);
2370 static void mce_reset(void)
2373 atomic_set(&mce_fake_paniced, 0);
2374 atomic_set(&mce_executing, 0);
2375 atomic_set(&mce_callin, 0);
2376 atomic_set(&global_nwo, 0);
2379 static int fake_panic_get(void *data, u64 *val)
2385 static int fake_panic_set(void *data, u64 val)
2392 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2393 fake_panic_set, "%llu\n");
2395 static int __init mcheck_debugfs_init(void)
2397 struct dentry *dmce, *ffake_panic;
2399 dmce = mce_get_debugfs_dir();
2402 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2409 late_initcall(mcheck_debugfs_init);