1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 u64 ctl; /* subevents to enable */
72 bool init; /* initialise bank? */
74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
77 /* One object for each MCE bank, shared by all CPUs */
79 struct device_attribute attr; /* device attribute */
80 char attrname[ATTR_LEN]; /* attribute name */
81 u8 bank; /* bank number */
83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
85 struct mce_vendor_flags mce_flags __read_mostly;
87 struct mca_config mca_cfg __read_mostly = {
91 * 0: always panic on uncorrected errors, log corrected errors
92 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
93 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
94 * 3: never panic or SIGBUS, log all errors (for testing only)
100 static DEFINE_PER_CPU(struct mce, mces_seen);
101 static unsigned long mce_need_notify;
102 static int cpu_missing;
105 * MCA banks polled by the period polling timer for corrected events.
106 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 * MCA banks controlled through firmware first for corrected errors.
114 * This is a global list of banks for which we won't enable CMCI and we
115 * won't poll. Firmware controls these banks and is responsible for
116 * reporting corrected errors through GHES. Uncorrected/recoverable
117 * errors are still notified through a machine check.
119 mce_banks_t mce_banks_ce_disabled;
121 static struct work_struct mce_work;
122 static struct irq_work mce_irq_work;
124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
127 * CPU/chipset specific EDAC code can register a notifier call here to print
128 * MCE errors in a human-readable form.
130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
132 /* Do initial initialization of a struct mce */
133 noinstr void mce_setup(struct mce *m)
135 memset(m, 0, sizeof(struct mce));
136 m->cpu = m->extcpu = smp_processor_id();
137 /* need the internal __ version to avoid deadlocks */
138 m->time = __ktime_get_real_seconds();
139 m->cpuvendor = boot_cpu_data.x86_vendor;
140 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 m->apicid = cpu_data(m->extcpu).initial_apicid;
143 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
145 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
146 m->ppin = __rdmsr(MSR_PPIN);
147 else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
148 m->ppin = __rdmsr(MSR_AMD_PPIN);
150 m->microcode = boot_cpu_data.microcode;
153 DEFINE_PER_CPU(struct mce, injectm);
154 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
156 void mce_log(struct mce *m)
158 if (!mce_gen_pool_add(m))
159 irq_work_queue(&mce_irq_work);
161 EXPORT_SYMBOL_GPL(mce_log);
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
166 nb->priority > MCE_PRIO_HIGHEST))
169 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
171 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
173 void mce_unregister_decode_chain(struct notifier_block *nb)
175 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
177 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
179 static inline u32 ctl_reg(int bank)
181 return MSR_IA32_MCx_CTL(bank);
184 static inline u32 status_reg(int bank)
186 return MSR_IA32_MCx_STATUS(bank);
189 static inline u32 addr_reg(int bank)
191 return MSR_IA32_MCx_ADDR(bank);
194 static inline u32 misc_reg(int bank)
196 return MSR_IA32_MCx_MISC(bank);
199 static inline u32 smca_ctl_reg(int bank)
201 return MSR_AMD64_SMCA_MCx_CTL(bank);
204 static inline u32 smca_status_reg(int bank)
206 return MSR_AMD64_SMCA_MCx_STATUS(bank);
209 static inline u32 smca_addr_reg(int bank)
211 return MSR_AMD64_SMCA_MCx_ADDR(bank);
214 static inline u32 smca_misc_reg(int bank)
216 return MSR_AMD64_SMCA_MCx_MISC(bank);
219 struct mca_msr_regs msr_ops = {
221 .status = status_reg,
226 static void __print_mce(struct mce *m)
228 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
230 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
231 m->mcgstatus, m->bank, m->status);
234 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
235 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
238 if (m->cs == __KERNEL_CS)
239 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
243 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
245 pr_cont("ADDR %llx ", m->addr);
247 pr_cont("MISC %llx ", m->misc);
249 pr_cont("PPIN %llx ", m->ppin);
251 if (mce_flags.smca) {
253 pr_cont("SYND %llx ", m->synd);
255 pr_cont("IPID %llx ", m->ipid);
261 * Note this output is parsed by external tools and old fields
262 * should not be changed.
264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
269 static void print_mce(struct mce *m)
273 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
277 #define PANIC_TIMEOUT 5 /* 5 seconds */
279 static atomic_t mce_panicked;
281 static int fake_panic;
282 static atomic_t mce_fake_panicked;
284 /* Panic in progress. Enable interrupts and wait for final IPI */
285 static void wait_for_panic(void)
287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
291 while (timeout-- > 0)
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
295 panic("Panicing machine check CPU died");
298 static void mce_panic(const char *msg, struct mce *final, char *exp)
301 struct llist_node *pending;
302 struct mce_evt_llist *l;
306 * Make sure only one CPU runs in machine check panic
308 if (atomic_inc_return(&mce_panicked) > 1)
315 /* Don't log too much for fake panic */
316 if (atomic_inc_return(&mce_fake_panicked) > 1)
319 pending = mce_gen_pool_prepare_records();
320 /* First print corrected ones that are still unlogged */
321 llist_for_each_entry(l, pending, llnode) {
322 struct mce *m = &l->mce;
323 if (!(m->status & MCI_STATUS_UC)) {
326 apei_err = apei_write_mce(m);
329 /* Now print uncorrected but with the final one last */
330 llist_for_each_entry(l, pending, llnode) {
331 struct mce *m = &l->mce;
332 if (!(m->status & MCI_STATUS_UC))
334 if (!final || mce_cmp(m, final)) {
337 apei_err = apei_write_mce(m);
343 apei_err = apei_write_mce(final);
346 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
348 pr_emerg(HW_ERR "Machine check: %s\n", exp);
350 if (panic_timeout == 0)
351 panic_timeout = mca_cfg.panic_timeout;
354 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
357 /* Support code for software error injection */
359 static int msr_to_offset(u32 msr)
361 unsigned bank = __this_cpu_read(injectm.bank);
363 if (msr == mca_cfg.rip_msr)
364 return offsetof(struct mce, ip);
365 if (msr == msr_ops.status(bank))
366 return offsetof(struct mce, status);
367 if (msr == msr_ops.addr(bank))
368 return offsetof(struct mce, addr);
369 if (msr == msr_ops.misc(bank))
370 return offsetof(struct mce, misc);
371 if (msr == MSR_IA32_MCG_STATUS)
372 return offsetof(struct mce, mcgstatus);
376 __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
377 struct pt_regs *regs, int trapnr,
378 unsigned long error_code,
379 unsigned long fault_addr)
381 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
382 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
384 show_stack_regs(regs);
386 panic("MCA architectural violation!\n");
394 /* MSR access wrappers used for error injection */
395 static noinstr u64 mce_rdmsrl(u32 msr)
397 DECLARE_ARGS(val, low, high);
399 if (__this_cpu_read(injectm.finished)) {
403 instrumentation_begin();
405 offset = msr_to_offset(msr);
409 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
411 instrumentation_end();
417 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
418 * architectural violation and needs to be reported to hw vendor. Panic
419 * the box to not allow any further progress.
421 asm volatile("1: rdmsr\n"
423 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_fault)
424 : EAX_EDX_RET(val, low, high) : "c" (msr));
427 return EAX_EDX_VAL(val, low, high);
430 __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup,
431 struct pt_regs *regs, int trapnr,
432 unsigned long error_code,
433 unsigned long fault_addr)
435 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
436 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
437 regs->ip, (void *)regs->ip);
439 show_stack_regs(regs);
441 panic("MCA architectural violation!\n");
449 static noinstr void mce_wrmsrl(u32 msr, u64 v)
453 if (__this_cpu_read(injectm.finished)) {
456 instrumentation_begin();
458 offset = msr_to_offset(msr);
460 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
462 instrumentation_end();
468 high = (u32)(v >> 32);
470 /* See comment in mce_rdmsrl() */
471 asm volatile("1: wrmsr\n"
473 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_fault)
474 : : "c" (msr), "a"(low), "d" (high) : "memory");
478 * Collect all global (w.r.t. this processor) status about this machine
479 * check into our "mce" struct so that we can use it later to assess
480 * the severity of the problem as we read per-bank specific details.
482 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
486 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
489 * Get the address of the instruction at the time of
490 * the machine check error.
492 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
497 * When in VM86 mode make the cs look like ring 3
498 * always. This is a lie, but it's better than passing
499 * the additional vm86 bit around everywhere.
501 if (v8086_mode(regs))
504 /* Use accurate RIP reporting if available. */
506 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
510 int mce_available(struct cpuinfo_x86 *c)
512 if (mca_cfg.disabled)
514 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
517 static void mce_schedule_work(void)
519 if (!mce_gen_pool_empty())
520 schedule_work(&mce_work);
523 static void mce_irq_work_cb(struct irq_work *entry)
529 * Check if the address reported by the CPU is in a format we can parse.
530 * It would be possible to add code for most other cases, but all would
531 * be somewhat complicated (e.g. segment offset would require an instruction
532 * parser). So only support physical addresses up to page granularity for now.
534 int mce_usable_address(struct mce *m)
536 if (!(m->status & MCI_STATUS_ADDRV))
539 /* Checks after this one are Intel/Zhaoxin-specific: */
540 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
541 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
544 if (!(m->status & MCI_STATUS_MISCV))
547 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
550 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
555 EXPORT_SYMBOL_GPL(mce_usable_address);
557 bool mce_is_memory_error(struct mce *m)
559 switch (m->cpuvendor) {
561 case X86_VENDOR_HYGON:
562 return amd_mce_is_memory_error(m);
564 case X86_VENDOR_INTEL:
565 case X86_VENDOR_ZHAOXIN:
567 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
569 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
570 * indicating a memory error. Bit 8 is used for indicating a
571 * cache hierarchy error. The combination of bit 2 and bit 3
572 * is used for indicating a `generic' cache hierarchy error
573 * But we can't just blindly check the above bits, because if
574 * bit 11 is set, then it is a bus/interconnect error - and
575 * either way the above bits just gives more detail on what
576 * bus/interconnect error happened. Note that bit 12 can be
577 * ignored, as it's the "filter" bit.
579 return (m->status & 0xef80) == BIT(7) ||
580 (m->status & 0xef00) == BIT(8) ||
581 (m->status & 0xeffc) == 0xc;
587 EXPORT_SYMBOL_GPL(mce_is_memory_error);
589 static bool whole_page(struct mce *m)
591 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
594 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
597 bool mce_is_correctable(struct mce *m)
599 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
602 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
605 if (m->status & MCI_STATUS_UC)
610 EXPORT_SYMBOL_GPL(mce_is_correctable);
612 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
615 struct mce *m = (struct mce *)data;
620 /* Emit the trace record: */
623 set_bit(0, &mce_need_notify);
630 static struct notifier_block early_nb = {
631 .notifier_call = mce_early_notifier,
632 .priority = MCE_PRIO_EARLY,
635 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
638 struct mce *mce = (struct mce *)data;
641 if (!mce || !mce_usable_address(mce))
644 if (mce->severity != MCE_AO_SEVERITY &&
645 mce->severity != MCE_DEFERRED_SEVERITY)
648 pfn = mce->addr >> PAGE_SHIFT;
649 if (!memory_failure(pfn, 0)) {
650 set_mce_nospec(pfn, whole_page(mce));
651 mce->kflags |= MCE_HANDLED_UC;
657 static struct notifier_block mce_uc_nb = {
658 .notifier_call = uc_decode_notifier,
659 .priority = MCE_PRIO_UC,
662 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
665 struct mce *m = (struct mce *)data;
670 if (mca_cfg.print_all || !m->kflags)
676 static struct notifier_block mce_default_nb = {
677 .notifier_call = mce_default_notifier,
678 /* lowest prio, we want it to run last. */
679 .priority = MCE_PRIO_LOWEST,
683 * Read ADDR and MISC registers.
685 static void mce_read_aux(struct mce *m, int i)
687 if (m->status & MCI_STATUS_MISCV)
688 m->misc = mce_rdmsrl(msr_ops.misc(i));
690 if (m->status & MCI_STATUS_ADDRV) {
691 m->addr = mce_rdmsrl(msr_ops.addr(i));
694 * Mask the reported address by the reported granularity.
696 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
697 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
703 * Extract [55:<lsb>] where lsb is the least significant
704 * *valid* bit of the address bits.
706 if (mce_flags.smca) {
707 u8 lsb = (m->addr >> 56) & 0x3f;
709 m->addr &= GENMASK_ULL(55, lsb);
713 if (mce_flags.smca) {
714 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
716 if (m->status & MCI_STATUS_SYNDV)
717 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
721 DEFINE_PER_CPU(unsigned, mce_poll_count);
724 * Poll for corrected events or events that happened before reset.
725 * Those are just logged through /dev/mcelog.
727 * This is executed in standard interrupt context.
729 * Note: spec recommends to panic for fatal unsignalled
730 * errors here. However this would be quite problematic --
731 * we would need to reimplement the Monarch handling and
732 * it would mess up the exclusion between exception handler
733 * and poll handler -- * so we skip this for now.
734 * These cases should not happen anyways, or only when the CPU
735 * is already totally * confused. In this case it's likely it will
736 * not fully execute the machine check handler either.
738 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
740 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
741 bool error_seen = false;
745 this_cpu_inc(mce_poll_count);
747 mce_gather_info(&m, NULL);
749 if (flags & MCP_TIMESTAMP)
752 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
753 if (!mce_banks[i].ctl || !test_bit(i, *b))
761 m.status = mce_rdmsrl(msr_ops.status(i));
763 /* If this entry is not valid, ignore it */
764 if (!(m.status & MCI_STATUS_VAL))
768 * If we are logging everything (at CPU online) or this
769 * is a corrected error, then we must log it.
771 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
775 * Newer Intel systems that support software error
776 * recovery need to make additional checks. Other
777 * CPUs should skip over uncorrected errors, but log
781 if (m.status & MCI_STATUS_UC)
786 /* Log "not enabled" (speculative) errors */
787 if (!(m.status & MCI_STATUS_EN))
791 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
792 * UC == 1 && PCC == 0 && S == 0
794 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
798 * Skip anything else. Presumption is that our read of this
799 * bank is racing with a machine check. Leave the log alone
800 * for do_machine_check() to deal with it.
807 if (flags & MCP_DONTLOG)
811 m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false);
813 * Don't get the IP here because it's unlikely to
814 * have anything to do with the actual error location.
817 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
820 if (flags & MCP_QUEUE_LOG)
821 mce_gen_pool_add(&m);
827 * Clear state for this bank.
829 mce_wrmsrl(msr_ops.status(i), 0);
833 * Don't clear MCG_STATUS here because it's only defined for
841 EXPORT_SYMBOL_GPL(machine_check_poll);
844 * Do a quick check if any of the events requires a panic.
845 * This decides if we keep the events around or clear them.
847 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
848 struct pt_regs *regs)
853 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
854 m->status = mce_rdmsrl(msr_ops.status(i));
855 if (!(m->status & MCI_STATUS_VAL))
858 __set_bit(i, validp);
859 if (quirk_no_way_out)
860 quirk_no_way_out(i, m, regs);
863 if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
873 * Variable to establish order between CPUs while scanning.
874 * Each CPU spins initially until executing is equal its number.
876 static atomic_t mce_executing;
879 * Defines order of CPUs on entry. First CPU becomes Monarch.
881 static atomic_t mce_callin;
884 * Track which CPUs entered the MCA broadcast synchronization and which not in
885 * order to print holdouts.
887 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
890 * Check if a timeout waiting for other CPUs happened.
892 static int mce_timed_out(u64 *t, const char *msg)
895 * The others already did panic for some reason.
896 * Bail out like in a timeout.
897 * rmb() to tell the compiler that system_state
898 * might have been modified by someone else.
901 if (atomic_read(&mce_panicked))
903 if (!mca_cfg.monarch_timeout)
905 if ((s64)*t < SPINUNIT) {
906 if (mca_cfg.tolerant <= 1) {
907 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
908 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
909 cpumask_pr_args(&mce_missing_cpus));
910 mce_panic(msg, NULL, NULL);
917 touch_nmi_watchdog();
922 * The Monarch's reign. The Monarch is the CPU who entered
923 * the machine check handler first. It waits for the others to
924 * raise the exception too and then grades them. When any
925 * error is fatal panic. Only then let the others continue.
927 * The other CPUs entering the MCE handler will be controlled by the
928 * Monarch. They are called Subjects.
930 * This way we prevent any potential data corruption in a unrecoverable case
931 * and also makes sure always all CPU's errors are examined.
933 * Also this detects the case of a machine check event coming from outer
934 * space (not detected by any CPUs) In this case some external agent wants
935 * us to shut down, so panic too.
937 * The other CPUs might still decide to panic if the handler happens
938 * in a unrecoverable place, but in this case the system is in a semi-stable
939 * state and won't corrupt anything by itself. It's ok to let the others
940 * continue for a bit first.
942 * All the spin loops have timeouts; when a timeout happens a CPU
943 * typically elects itself to be Monarch.
945 static void mce_reign(void)
948 struct mce *m = NULL;
949 int global_worst = 0;
953 * This CPU is the Monarch and the other CPUs have run
954 * through their handlers.
955 * Grade the severity of the errors of all the CPUs.
957 for_each_possible_cpu(cpu) {
958 struct mce *mtmp = &per_cpu(mces_seen, cpu);
960 if (mtmp->severity > global_worst) {
961 global_worst = mtmp->severity;
962 m = &per_cpu(mces_seen, cpu);
967 * Cannot recover? Panic here then.
968 * This dumps all the mces in the log buffer and stops the
971 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
972 /* call mce_severity() to get "msg" for panic */
973 mce_severity(m, NULL, mca_cfg.tolerant, &msg, true);
974 mce_panic("Fatal machine check", m, msg);
978 * For UC somewhere we let the CPU who detects it handle it.
979 * Also must let continue the others, otherwise the handling
980 * CPU could deadlock on a lock.
984 * No machine check event found. Must be some external
985 * source or one CPU is hung. Panic.
987 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
988 mce_panic("Fatal machine check from unknown source", NULL, NULL);
991 * Now clear all the mces_seen so that they don't reappear on
994 for_each_possible_cpu(cpu)
995 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
998 static atomic_t global_nwo;
1001 * Start of Monarch synchronization. This waits until all CPUs have
1002 * entered the exception handler and then determines if any of them
1003 * saw a fatal event that requires panic. Then it executes them
1004 * in the entry order.
1005 * TBD double check parallel CPU hotunplug
1007 static int mce_start(int *no_way_out)
1010 int cpus = num_online_cpus();
1011 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1016 atomic_add(*no_way_out, &global_nwo);
1018 * Rely on the implied barrier below, such that global_nwo
1019 * is updated before mce_callin.
1021 order = atomic_inc_return(&mce_callin);
1022 cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1025 * Wait for everyone.
1027 while (atomic_read(&mce_callin) != cpus) {
1028 if (mce_timed_out(&timeout,
1029 "Timeout: Not all CPUs entered broadcast exception handler")) {
1030 atomic_set(&global_nwo, 0);
1037 * mce_callin should be read before global_nwo
1043 * Monarch: Starts executing now, the others wait.
1045 atomic_set(&mce_executing, 1);
1048 * Subject: Now start the scanning loop one by one in
1049 * the original callin order.
1050 * This way when there are any shared banks it will be
1051 * only seen by one CPU before cleared, avoiding duplicates.
1053 while (atomic_read(&mce_executing) < order) {
1054 if (mce_timed_out(&timeout,
1055 "Timeout: Subject CPUs unable to finish machine check processing")) {
1056 atomic_set(&global_nwo, 0);
1064 * Cache the global no_way_out state.
1066 *no_way_out = atomic_read(&global_nwo);
1072 * Synchronize between CPUs after main scanning loop.
1073 * This invokes the bulk of the Monarch processing.
1075 static int mce_end(int order)
1078 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1086 * Allow others to run.
1088 atomic_inc(&mce_executing);
1091 /* CHECKME: Can this race with a parallel hotplug? */
1092 int cpus = num_online_cpus();
1095 * Monarch: Wait for everyone to go through their scanning
1098 while (atomic_read(&mce_executing) <= cpus) {
1099 if (mce_timed_out(&timeout,
1100 "Timeout: Monarch CPU unable to finish machine check processing"))
1110 * Subject: Wait for Monarch to finish.
1112 while (atomic_read(&mce_executing) != 0) {
1113 if (mce_timed_out(&timeout,
1114 "Timeout: Monarch CPU did not finish machine check processing"))
1120 * Don't reset anything. That's done by the Monarch.
1126 * Reset all global state.
1129 atomic_set(&global_nwo, 0);
1130 atomic_set(&mce_callin, 0);
1131 cpumask_setall(&mce_missing_cpus);
1135 * Let others run again.
1137 atomic_set(&mce_executing, 0);
1141 static void mce_clear_state(unsigned long *toclear)
1145 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1146 if (test_bit(i, toclear))
1147 mce_wrmsrl(msr_ops.status(i), 0);
1152 * Cases where we avoid rendezvous handler timeout:
1153 * 1) If this CPU is offline.
1155 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1156 * skip those CPUs which remain looping in the 1st kernel - see
1157 * crash_nmi_callback().
1159 * Note: there still is a small window between kexec-ing and the new,
1160 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1161 * might not get handled properly.
1163 static noinstr bool mce_check_crashing_cpu(void)
1165 unsigned int cpu = smp_processor_id();
1167 if (arch_cpu_is_offline(cpu) ||
1168 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1171 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1173 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1174 if (mcgstatus & MCG_STATUS_LMCES)
1178 if (mcgstatus & MCG_STATUS_RIPV) {
1179 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1186 static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1187 unsigned long *toclear, unsigned long *valid_banks,
1188 int no_way_out, int *worst)
1190 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1191 struct mca_config *cfg = &mca_cfg;
1194 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1195 __clear_bit(i, toclear);
1196 if (!test_bit(i, valid_banks))
1199 if (!mce_banks[i].ctl)
1206 m->status = mce_rdmsrl(msr_ops.status(i));
1207 if (!(m->status & MCI_STATUS_VAL))
1211 * Corrected or non-signaled errors are handled by
1212 * machine_check_poll(). Leave them alone, unless this panics.
1214 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1218 /* Set taint even when machine check was not enabled. */
1219 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1221 severity = mce_severity(m, regs, cfg->tolerant, NULL, true);
1224 * When machine check was for corrected/deferred handler don't
1225 * touch, unless we're panicking.
1227 if ((severity == MCE_KEEP_SEVERITY ||
1228 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1231 __set_bit(i, toclear);
1233 /* Machine check event was not enabled. Clear, but ignore. */
1234 if (severity == MCE_NO_SEVERITY)
1239 /* assuming valid severity level != 0 */
1240 m->severity = severity;
1244 if (severity > *worst) {
1250 /* mce_clear_state will clear *final, save locally for use later */
1254 static void kill_me_now(struct callback_head *ch)
1259 static void kill_me_maybe(struct callback_head *cb)
1261 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1262 int flags = MF_ACTION_REQUIRED;
1265 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1268 flags |= MF_MUST_KILL;
1270 ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags);
1271 if (!ret && !(p->mce_kflags & MCE_IN_KERNEL_COPYIN)) {
1272 set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page);
1278 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1279 * to the current process with the proper error info, so no need to
1280 * send SIGBUS here again.
1282 if (ret == -EHWPOISON)
1285 if (p->mce_vaddr != (void __user *)-1l) {
1286 force_sig_mceerr(BUS_MCEERR_AR, p->mce_vaddr, PAGE_SHIFT);
1288 pr_err("Memory error not recovered");
1293 static void queue_task_work(struct mce *m, int kill_current_task)
1295 current->mce_addr = m->addr;
1296 current->mce_kflags = m->kflags;
1297 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1298 current->mce_whole_page = whole_page(m);
1300 if (kill_current_task)
1301 current->mce_kill_me.func = kill_me_now;
1303 current->mce_kill_me.func = kill_me_maybe;
1305 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1309 * The actual machine check handler. This only handles real
1310 * exceptions when something got corrupted coming in through int 18.
1312 * This is executed in NMI context not subject to normal locking rules. This
1313 * implies that most kernel services cannot be safely used. Don't even
1314 * think about putting a printk in there!
1316 * On Intel systems this is entered on all CPUs in parallel through
1317 * MCE broadcast. However some CPUs might be broken beyond repair,
1318 * so be always careful when synchronizing with others.
1320 * Tracing and kprobes are disabled: if we interrupted a kernel context
1321 * with IF=1, we need to minimize stack usage. There are also recursion
1322 * issues: if the machine check was due to a failure of the memory
1323 * backing the user stack, tracing that reads the user stack will cause
1324 * potentially infinite recursion.
1326 noinstr void do_machine_check(struct pt_regs *regs)
1328 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1329 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1330 struct mca_config *cfg = &mca_cfg;
1331 struct mce m, *final;
1336 * Establish sequential order between the CPUs entering the machine
1342 * If no_way_out gets set, there is no safe way to recover from this
1343 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1348 * If kill_current_task is not set, there might be a way to recover from this
1351 int kill_current_task = 0;
1354 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1359 this_cpu_inc(mce_exception_count);
1361 mce_gather_info(&m, regs);
1364 final = this_cpu_ptr(&mces_seen);
1367 memset(valid_banks, 0, sizeof(valid_banks));
1368 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1373 * When no restart IP might need to kill or panic.
1374 * Assume the worst for now, but if we find the
1375 * severity is MCE_AR_SEVERITY we have other options.
1377 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1378 kill_current_task = (cfg->tolerant == 3) ? 0 : 1;
1380 * Check if this MCE is signaled to only this logical processor,
1381 * on Intel, Zhaoxin only.
1383 if (m.cpuvendor == X86_VENDOR_INTEL ||
1384 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1385 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1388 * Local machine check may already know that we have to panic.
1389 * Broadcast machine check begins rendezvous in mce_start()
1390 * Go through all banks in exclusion of the other CPUs. This way we
1391 * don't report duplicated events on shared banks because the first one
1392 * to see it will clear it.
1395 if (no_way_out && cfg->tolerant < 3)
1396 mce_panic("Fatal local machine check", &m, msg);
1398 order = mce_start(&no_way_out);
1401 __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1404 mce_clear_state(toclear);
1407 * Do most of the synchronization with other CPUs.
1408 * When there's any problem use only local no_way_out state.
1411 if (mce_end(order) < 0) {
1413 no_way_out = worst >= MCE_PANIC_SEVERITY;
1415 if (no_way_out && cfg->tolerant < 3)
1416 mce_panic("Fatal machine check on current CPU", &m, msg);
1420 * If there was a fatal machine check we should have
1421 * already called mce_panic earlier in this function.
1422 * Since we re-read the banks, we might have found
1423 * something new. Check again to see if we found a
1424 * fatal error. We call "mce_severity()" again to
1425 * make sure we have the right "msg".
1427 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1428 mce_severity(&m, regs, cfg->tolerant, &msg, true);
1429 mce_panic("Local fatal machine check!", &m, msg);
1433 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1436 /* Fault was in user mode and we need to take some action */
1437 if ((m.cs & 3) == 3) {
1438 /* If this triggers there is no way to recover. Die hard. */
1439 BUG_ON(!on_thread_stack() || !user_mode(regs));
1441 queue_task_work(&m, kill_current_task);
1445 * Handle an MCE which has happened in kernel space but from
1446 * which the kernel can recover: ex_has_fault_handler() has
1447 * already verified that the rIP at which the error happened is
1448 * a rIP from which the kernel can recover (by jumping to
1449 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1450 * corresponding exception handler which would do that is the
1453 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1454 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1455 mce_panic("Failed kernel mode recovery", &m, msg);
1458 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1459 queue_task_work(&m, kill_current_task);
1462 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1464 EXPORT_SYMBOL_GPL(do_machine_check);
1466 #ifndef CONFIG_MEMORY_FAILURE
1467 int memory_failure(unsigned long pfn, int flags)
1469 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1470 BUG_ON(flags & MF_ACTION_REQUIRED);
1471 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1472 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1480 * Periodic polling timer for "silent" machine check errors. If the
1481 * poller finds an MCE, poll 2x faster. When the poller finds no more
1482 * errors, poll 2x slower (up to check_interval seconds).
1484 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1486 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1487 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1489 static unsigned long mce_adjust_timer_default(unsigned long interval)
1494 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1496 static void __start_timer(struct timer_list *t, unsigned long interval)
1498 unsigned long when = jiffies + interval;
1499 unsigned long flags;
1501 local_irq_save(flags);
1503 if (!timer_pending(t) || time_before(when, t->expires))
1504 mod_timer(t, round_jiffies(when));
1506 local_irq_restore(flags);
1509 static void mce_timer_fn(struct timer_list *t)
1511 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1514 WARN_ON(cpu_t != t);
1516 iv = __this_cpu_read(mce_next_interval);
1518 if (mce_available(this_cpu_ptr(&cpu_info))) {
1519 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1521 if (mce_intel_cmci_poll()) {
1522 iv = mce_adjust_timer(iv);
1528 * Alert userspace if needed. If we logged an MCE, reduce the polling
1529 * interval, otherwise increase the polling interval.
1531 if (mce_notify_irq())
1532 iv = max(iv / 2, (unsigned long) HZ/100);
1534 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1537 __this_cpu_write(mce_next_interval, iv);
1538 __start_timer(t, iv);
1542 * Ensure that the timer is firing in @interval from now.
1544 void mce_timer_kick(unsigned long interval)
1546 struct timer_list *t = this_cpu_ptr(&mce_timer);
1547 unsigned long iv = __this_cpu_read(mce_next_interval);
1549 __start_timer(t, interval);
1552 __this_cpu_write(mce_next_interval, interval);
1555 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1556 static void mce_timer_delete_all(void)
1560 for_each_online_cpu(cpu)
1561 del_timer_sync(&per_cpu(mce_timer, cpu));
1565 * Notify the user(s) about new machine check events.
1566 * Can be called from interrupt context, but not from machine check/NMI
1569 int mce_notify_irq(void)
1571 /* Not more than two messages every minute */
1572 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1574 if (test_and_clear_bit(0, &mce_need_notify)) {
1577 if (__ratelimit(&ratelimit))
1578 pr_info(HW_ERR "Machine check events logged\n");
1584 EXPORT_SYMBOL_GPL(mce_notify_irq);
1586 static void __mcheck_cpu_mce_banks_init(void)
1588 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1589 u8 n_banks = this_cpu_read(mce_num_banks);
1592 for (i = 0; i < n_banks; i++) {
1593 struct mce_bank *b = &mce_banks[i];
1596 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1597 * the required vendor quirks before
1598 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1606 * Initialize Machine Checks for a CPU.
1608 static void __mcheck_cpu_cap_init(void)
1613 rdmsrl(MSR_IA32_MCG_CAP, cap);
1615 b = cap & MCG_BANKCNT_MASK;
1617 if (b > MAX_NR_BANKS) {
1618 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1619 smp_processor_id(), MAX_NR_BANKS, b);
1623 this_cpu_write(mce_num_banks, b);
1625 __mcheck_cpu_mce_banks_init();
1627 /* Use accurate RIP reporting if available. */
1628 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1629 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1631 if (cap & MCG_SER_P)
1635 static void __mcheck_cpu_init_generic(void)
1637 enum mcp_flags m_fl = 0;
1638 mce_banks_t all_banks;
1641 if (!mca_cfg.bootlog)
1645 * Log the machine checks left over from the previous reset. Log them
1646 * only, do not start processing them. That will happen in mcheck_late_init()
1647 * when all consumers have been registered on the notifier chain.
1649 bitmap_fill(all_banks, MAX_NR_BANKS);
1650 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1652 cr4_set_bits(X86_CR4_MCE);
1654 rdmsrl(MSR_IA32_MCG_CAP, cap);
1655 if (cap & MCG_CTL_P)
1656 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1659 static void __mcheck_cpu_init_clear_banks(void)
1661 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1664 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1665 struct mce_bank *b = &mce_banks[i];
1669 wrmsrl(msr_ops.ctl(i), b->ctl);
1670 wrmsrl(msr_ops.status(i), 0);
1675 * Do a final check to see if there are any unused/RAZ banks.
1677 * This must be done after the banks have been initialized and any quirks have
1680 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1681 * Otherwise, a user who disables a bank will not be able to re-enable it
1682 * without a system reboot.
1684 static void __mcheck_cpu_check_banks(void)
1686 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1690 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1691 struct mce_bank *b = &mce_banks[i];
1696 rdmsrl(msr_ops.ctl(i), msrval);
1702 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1703 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1704 * Vol 3B Table 15-20). But this confuses both the code that determines
1705 * whether the machine check occurred in kernel or user mode, and also
1706 * the severity assessment code. Pretend that EIPV was set, and take the
1707 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1709 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1713 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1715 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1716 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1717 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1719 (MCI_STATUS_UC|MCI_STATUS_EN|
1720 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1721 MCI_STATUS_AR|MCACOD_INSTR))
1724 m->mcgstatus |= MCG_STATUS_EIPV;
1729 /* Add per CPU specific workarounds here */
1730 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1732 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1733 struct mca_config *cfg = &mca_cfg;
1735 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1736 pr_info("unknown CPU type - not enabling MCE support\n");
1740 /* This should be disabled by the BIOS, but isn't always */
1741 if (c->x86_vendor == X86_VENDOR_AMD) {
1742 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1744 * disable GART TBL walk error reporting, which
1745 * trips off incorrectly with the IOMMU & 3ware
1748 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1750 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1752 * Lots of broken BIOS around that don't clear them
1753 * by default and leave crap in there. Don't log:
1758 * Various K7s with broken bank 0 around. Always disable
1761 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1762 mce_banks[0].ctl = 0;
1765 * overflow_recov is supported for F15h Models 00h-0fh
1766 * even though we don't have a CPUID bit for it.
1768 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1769 mce_flags.overflow_recov = 1;
1773 if (c->x86_vendor == X86_VENDOR_INTEL) {
1775 * SDM documents that on family 6 bank 0 should not be written
1776 * because it aliases to another special BIOS controlled
1778 * But it's not aliased anymore on model 0x1a+
1779 * Don't ignore bank 0 completely because there could be a
1780 * valid event later, merely don't write CTL0.
1783 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1784 mce_banks[0].init = false;
1787 * All newer Intel systems support MCE broadcasting. Enable
1788 * synchronization with a one second timeout.
1790 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1791 cfg->monarch_timeout < 0)
1792 cfg->monarch_timeout = USEC_PER_SEC;
1795 * There are also broken BIOSes on some Pentium M and
1798 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1801 if (c->x86 == 6 && c->x86_model == 45)
1802 quirk_no_way_out = quirk_sandybridge_ifu;
1805 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1807 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1808 * synchronization with a one second timeout.
1810 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1811 if (cfg->monarch_timeout < 0)
1812 cfg->monarch_timeout = USEC_PER_SEC;
1816 if (cfg->monarch_timeout < 0)
1817 cfg->monarch_timeout = 0;
1818 if (cfg->bootlog != 0)
1819 cfg->panic_timeout = 30;
1824 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1829 switch (c->x86_vendor) {
1830 case X86_VENDOR_INTEL:
1831 intel_p5_mcheck_init(c);
1833 case X86_VENDOR_CENTAUR:
1834 winchip_mcheck_init(c);
1844 * Init basic CPU features needed for early decoding of MCEs.
1846 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1848 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1849 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1850 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1851 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1852 mce_flags.amd_threshold = 1;
1854 if (mce_flags.smca) {
1855 msr_ops.ctl = smca_ctl_reg;
1856 msr_ops.status = smca_status_reg;
1857 msr_ops.addr = smca_addr_reg;
1858 msr_ops.misc = smca_misc_reg;
1863 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1865 struct mca_config *cfg = &mca_cfg;
1868 * All newer Centaur CPUs support MCE broadcasting. Enable
1869 * synchronization with a one second timeout.
1871 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1873 if (cfg->monarch_timeout < 0)
1874 cfg->monarch_timeout = USEC_PER_SEC;
1878 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1880 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1883 * These CPUs have MCA bank 8 which reports only one error type called
1884 * SVAD (System View Address Decoder). The reporting of that error is
1885 * controlled by IA32_MC8.CTL.0.
1887 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1888 * virtual machines start and result in a system panic. Always disable
1889 * bank 8 SVAD error by default.
1891 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1892 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1893 if (this_cpu_read(mce_num_banks) > 8)
1894 mce_banks[8].ctl = 0;
1899 mce_adjust_timer = cmci_intel_adjust_timer;
1902 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1907 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1909 switch (c->x86_vendor) {
1910 case X86_VENDOR_INTEL:
1911 mce_intel_feature_init(c);
1912 mce_adjust_timer = cmci_intel_adjust_timer;
1915 case X86_VENDOR_AMD: {
1916 mce_amd_feature_init(c);
1920 case X86_VENDOR_HYGON:
1921 mce_hygon_feature_init(c);
1924 case X86_VENDOR_CENTAUR:
1925 mce_centaur_feature_init(c);
1928 case X86_VENDOR_ZHAOXIN:
1929 mce_zhaoxin_feature_init(c);
1937 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1939 switch (c->x86_vendor) {
1940 case X86_VENDOR_INTEL:
1941 mce_intel_feature_clear(c);
1944 case X86_VENDOR_ZHAOXIN:
1945 mce_zhaoxin_feature_clear(c);
1953 static void mce_start_timer(struct timer_list *t)
1955 unsigned long iv = check_interval * HZ;
1957 if (mca_cfg.ignore_ce || !iv)
1960 this_cpu_write(mce_next_interval, iv);
1961 __start_timer(t, iv);
1964 static void __mcheck_cpu_setup_timer(void)
1966 struct timer_list *t = this_cpu_ptr(&mce_timer);
1968 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1971 static void __mcheck_cpu_init_timer(void)
1973 struct timer_list *t = this_cpu_ptr(&mce_timer);
1975 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1979 bool filter_mce(struct mce *m)
1981 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1982 return amd_filter_mce(m);
1983 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1984 return intel_filter_mce(m);
1989 /* Handle unconfigured int18 (should never happen) */
1990 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1992 instrumentation_begin();
1993 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1994 smp_processor_id());
1995 instrumentation_end();
1998 /* Call the installed machine check handler for this CPU setup. */
1999 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
2001 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2003 irqentry_state_t irq_state;
2005 WARN_ON_ONCE(user_mode(regs));
2008 * Only required when from kernel mode. See
2009 * mce_check_crashing_cpu() for details.
2011 if (machine_check_vector == do_machine_check &&
2012 mce_check_crashing_cpu())
2015 irq_state = irqentry_nmi_enter(regs);
2017 * The call targets are marked noinstr, but objtool can't figure
2018 * that out because it's an indirect call. Annotate it.
2020 instrumentation_begin();
2022 machine_check_vector(regs);
2024 instrumentation_end();
2025 irqentry_nmi_exit(regs, irq_state);
2028 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2030 irqentry_enter_from_user_mode(regs);
2031 instrumentation_begin();
2033 machine_check_vector(regs);
2035 instrumentation_end();
2036 irqentry_exit_to_user_mode(regs);
2039 #ifdef CONFIG_X86_64
2040 /* MCE hit kernel mode */
2041 DEFINE_IDTENTRY_MCE(exc_machine_check)
2045 dr7 = local_db_save();
2046 exc_machine_check_kernel(regs);
2047 local_db_restore(dr7);
2050 /* The user mode variant. */
2051 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2055 dr7 = local_db_save();
2056 exc_machine_check_user(regs);
2057 local_db_restore(dr7);
2060 /* 32bit unified entry point */
2061 DEFINE_IDTENTRY_RAW(exc_machine_check)
2065 dr7 = local_db_save();
2066 if (user_mode(regs))
2067 exc_machine_check_user(regs);
2069 exc_machine_check_kernel(regs);
2070 local_db_restore(dr7);
2075 * Called for each booted CPU to set up machine checks.
2076 * Must be called with preempt off:
2078 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2080 if (mca_cfg.disabled)
2083 if (__mcheck_cpu_ancient_init(c))
2086 if (!mce_available(c))
2089 __mcheck_cpu_cap_init();
2091 if (__mcheck_cpu_apply_quirks(c) < 0) {
2092 mca_cfg.disabled = 1;
2096 if (mce_gen_pool_init()) {
2097 mca_cfg.disabled = 1;
2098 pr_emerg("Couldn't allocate MCE records pool!\n");
2102 machine_check_vector = do_machine_check;
2104 __mcheck_cpu_init_early(c);
2105 __mcheck_cpu_init_generic();
2106 __mcheck_cpu_init_vendor(c);
2107 __mcheck_cpu_init_clear_banks();
2108 __mcheck_cpu_check_banks();
2109 __mcheck_cpu_setup_timer();
2113 * Called for each booted CPU to clear some machine checks opt-ins
2115 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2117 if (mca_cfg.disabled)
2120 if (!mce_available(c))
2124 * Possibly to clear general settings generic to x86
2125 * __mcheck_cpu_clear_generic(c);
2127 __mcheck_cpu_clear_vendor(c);
2131 static void __mce_disable_bank(void *arg)
2133 int bank = *((int *)arg);
2134 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2135 cmci_disable_bank(bank);
2138 void mce_disable_bank(int bank)
2140 if (bank >= this_cpu_read(mce_num_banks)) {
2142 "Ignoring request to disable invalid MCA bank %d.\n",
2146 set_bit(bank, mce_banks_ce_disabled);
2147 on_each_cpu(__mce_disable_bank, &bank, 1);
2151 * mce=off Disables machine check
2152 * mce=no_cmci Disables CMCI
2153 * mce=no_lmce Disables LMCE
2154 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2155 * mce=print_all Print all machine check logs to console
2156 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2157 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2158 * monarchtimeout is how long to wait for other CPUs on machine
2159 * check, or 0 to not wait
2160 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2162 * mce=nobootlog Don't log MCEs from before booting.
2163 * mce=bios_cmci_threshold Don't program the CMCI threshold
2164 * mce=recovery force enable copy_mc_fragile()
2166 static int __init mcheck_enable(char *str)
2168 struct mca_config *cfg = &mca_cfg;
2176 if (!strcmp(str, "off"))
2178 else if (!strcmp(str, "no_cmci"))
2179 cfg->cmci_disabled = true;
2180 else if (!strcmp(str, "no_lmce"))
2181 cfg->lmce_disabled = 1;
2182 else if (!strcmp(str, "dont_log_ce"))
2183 cfg->dont_log_ce = true;
2184 else if (!strcmp(str, "print_all"))
2185 cfg->print_all = true;
2186 else if (!strcmp(str, "ignore_ce"))
2187 cfg->ignore_ce = true;
2188 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2189 cfg->bootlog = (str[0] == 'b');
2190 else if (!strcmp(str, "bios_cmci_threshold"))
2191 cfg->bios_cmci_threshold = 1;
2192 else if (!strcmp(str, "recovery"))
2194 else if (isdigit(str[0])) {
2195 if (get_option(&str, &cfg->tolerant) == 2)
2196 get_option(&str, &(cfg->monarch_timeout));
2198 pr_info("mce argument %s ignored. Please use /sys\n", str);
2203 __setup("mce", mcheck_enable);
2205 int __init mcheck_init(void)
2207 mce_register_decode_chain(&early_nb);
2208 mce_register_decode_chain(&mce_uc_nb);
2209 mce_register_decode_chain(&mce_default_nb);
2210 mcheck_vendor_init_severity();
2212 INIT_WORK(&mce_work, mce_gen_pool_process);
2213 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2219 * mce_syscore: PM support
2223 * Disable machine checks on suspend and shutdown. We can't really handle
2226 static void mce_disable_error_reporting(void)
2228 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2231 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2232 struct mce_bank *b = &mce_banks[i];
2235 wrmsrl(msr_ops.ctl(i), 0);
2240 static void vendor_disable_error_reporting(void)
2243 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2244 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2245 * is bad, since it will inhibit reporting for all shared resources on
2246 * the socket like the last level cache (LLC), the integrated memory
2247 * controller (iMC), etc.
2249 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2250 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2251 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2252 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2255 mce_disable_error_reporting();
2258 static int mce_syscore_suspend(void)
2260 vendor_disable_error_reporting();
2264 static void mce_syscore_shutdown(void)
2266 vendor_disable_error_reporting();
2270 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2271 * Only one CPU is active at this time, the others get re-added later using
2274 static void mce_syscore_resume(void)
2276 __mcheck_cpu_init_generic();
2277 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2278 __mcheck_cpu_init_clear_banks();
2281 static struct syscore_ops mce_syscore_ops = {
2282 .suspend = mce_syscore_suspend,
2283 .shutdown = mce_syscore_shutdown,
2284 .resume = mce_syscore_resume,
2288 * mce_device: Sysfs support
2291 static void mce_cpu_restart(void *data)
2293 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2295 __mcheck_cpu_init_generic();
2296 __mcheck_cpu_init_clear_banks();
2297 __mcheck_cpu_init_timer();
2300 /* Reinit MCEs after user configuration changes */
2301 static void mce_restart(void)
2303 mce_timer_delete_all();
2304 on_each_cpu(mce_cpu_restart, NULL, 1);
2307 /* Toggle features for corrected errors */
2308 static void mce_disable_cmci(void *data)
2310 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2315 static void mce_enable_ce(void *all)
2317 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2322 __mcheck_cpu_init_timer();
2325 static struct bus_type mce_subsys = {
2326 .name = "machinecheck",
2327 .dev_name = "machinecheck",
2330 DEFINE_PER_CPU(struct device *, mce_device);
2332 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2334 return container_of(attr, struct mce_bank_dev, attr);
2337 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2340 u8 bank = attr_to_bank(attr)->bank;
2343 if (bank >= per_cpu(mce_num_banks, s->id))
2346 b = &per_cpu(mce_banks_array, s->id)[bank];
2351 return sprintf(buf, "%llx\n", b->ctl);
2354 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2355 const char *buf, size_t size)
2357 u8 bank = attr_to_bank(attr)->bank;
2361 if (kstrtou64(buf, 0, &new) < 0)
2364 if (bank >= per_cpu(mce_num_banks, s->id))
2367 b = &per_cpu(mce_banks_array, s->id)[bank];
2378 static ssize_t set_ignore_ce(struct device *s,
2379 struct device_attribute *attr,
2380 const char *buf, size_t size)
2384 if (kstrtou64(buf, 0, &new) < 0)
2387 mutex_lock(&mce_sysfs_mutex);
2388 if (mca_cfg.ignore_ce ^ !!new) {
2390 /* disable ce features */
2391 mce_timer_delete_all();
2392 on_each_cpu(mce_disable_cmci, NULL, 1);
2393 mca_cfg.ignore_ce = true;
2395 /* enable ce features */
2396 mca_cfg.ignore_ce = false;
2397 on_each_cpu(mce_enable_ce, (void *)1, 1);
2400 mutex_unlock(&mce_sysfs_mutex);
2405 static ssize_t set_cmci_disabled(struct device *s,
2406 struct device_attribute *attr,
2407 const char *buf, size_t size)
2411 if (kstrtou64(buf, 0, &new) < 0)
2414 mutex_lock(&mce_sysfs_mutex);
2415 if (mca_cfg.cmci_disabled ^ !!new) {
2418 on_each_cpu(mce_disable_cmci, NULL, 1);
2419 mca_cfg.cmci_disabled = true;
2422 mca_cfg.cmci_disabled = false;
2423 on_each_cpu(mce_enable_ce, NULL, 1);
2426 mutex_unlock(&mce_sysfs_mutex);
2431 static ssize_t store_int_with_restart(struct device *s,
2432 struct device_attribute *attr,
2433 const char *buf, size_t size)
2435 unsigned long old_check_interval = check_interval;
2436 ssize_t ret = device_store_ulong(s, attr, buf, size);
2438 if (check_interval == old_check_interval)
2441 mutex_lock(&mce_sysfs_mutex);
2443 mutex_unlock(&mce_sysfs_mutex);
2448 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2449 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2450 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2451 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2453 static struct dev_ext_attribute dev_attr_check_interval = {
2454 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2458 static struct dev_ext_attribute dev_attr_ignore_ce = {
2459 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2463 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2464 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2465 &mca_cfg.cmci_disabled
2468 static struct device_attribute *mce_device_attrs[] = {
2469 &dev_attr_tolerant.attr,
2470 &dev_attr_check_interval.attr,
2471 #ifdef CONFIG_X86_MCELOG_LEGACY
2474 &dev_attr_monarch_timeout.attr,
2475 &dev_attr_dont_log_ce.attr,
2476 &dev_attr_print_all.attr,
2477 &dev_attr_ignore_ce.attr,
2478 &dev_attr_cmci_disabled.attr,
2482 static cpumask_var_t mce_device_initialized;
2484 static void mce_device_release(struct device *dev)
2489 /* Per CPU device init. All of the CPUs still share the same bank device: */
2490 static int mce_device_create(unsigned int cpu)
2496 if (!mce_available(&boot_cpu_data))
2499 dev = per_cpu(mce_device, cpu);
2503 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2507 dev->bus = &mce_subsys;
2508 dev->release = &mce_device_release;
2510 err = device_register(dev);
2516 for (i = 0; mce_device_attrs[i]; i++) {
2517 err = device_create_file(dev, mce_device_attrs[i]);
2521 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2522 err = device_create_file(dev, &mce_bank_devs[j].attr);
2526 cpumask_set_cpu(cpu, mce_device_initialized);
2527 per_cpu(mce_device, cpu) = dev;
2532 device_remove_file(dev, &mce_bank_devs[j].attr);
2535 device_remove_file(dev, mce_device_attrs[i]);
2537 device_unregister(dev);
2542 static void mce_device_remove(unsigned int cpu)
2544 struct device *dev = per_cpu(mce_device, cpu);
2547 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2550 for (i = 0; mce_device_attrs[i]; i++)
2551 device_remove_file(dev, mce_device_attrs[i]);
2553 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2554 device_remove_file(dev, &mce_bank_devs[i].attr);
2556 device_unregister(dev);
2557 cpumask_clear_cpu(cpu, mce_device_initialized);
2558 per_cpu(mce_device, cpu) = NULL;
2561 /* Make sure there are no machine checks on offlined CPUs. */
2562 static void mce_disable_cpu(void)
2564 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2567 if (!cpuhp_tasks_frozen)
2570 vendor_disable_error_reporting();
2573 static void mce_reenable_cpu(void)
2575 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2578 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2581 if (!cpuhp_tasks_frozen)
2583 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2584 struct mce_bank *b = &mce_banks[i];
2587 wrmsrl(msr_ops.ctl(i), b->ctl);
2591 static int mce_cpu_dead(unsigned int cpu)
2593 mce_intel_hcpu_update(cpu);
2595 /* intentionally ignoring frozen here */
2596 if (!cpuhp_tasks_frozen)
2601 static int mce_cpu_online(unsigned int cpu)
2603 struct timer_list *t = this_cpu_ptr(&mce_timer);
2606 mce_device_create(cpu);
2608 ret = mce_threshold_create_device(cpu);
2610 mce_device_remove(cpu);
2618 static int mce_cpu_pre_down(unsigned int cpu)
2620 struct timer_list *t = this_cpu_ptr(&mce_timer);
2624 mce_threshold_remove_device(cpu);
2625 mce_device_remove(cpu);
2629 static __init void mce_init_banks(void)
2633 for (i = 0; i < MAX_NR_BANKS; i++) {
2634 struct mce_bank_dev *b = &mce_bank_devs[i];
2635 struct device_attribute *a = &b->attr;
2639 sysfs_attr_init(&a->attr);
2640 a->attr.name = b->attrname;
2641 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2643 a->attr.mode = 0644;
2644 a->show = show_bank;
2645 a->store = set_bank;
2650 * When running on XEN, this initcall is ordered against the XEN mcelog
2653 * device_initcall(xen_late_init_mcelog);
2654 * device_initcall_sync(mcheck_init_device);
2656 static __init int mcheck_init_device(void)
2661 * Check if we have a spare virtual bit. This will only become
2662 * a problem if/when we move beyond 5-level page tables.
2664 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2666 if (!mce_available(&boot_cpu_data)) {
2671 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2678 err = subsys_system_register(&mce_subsys, NULL);
2682 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2688 * Invokes mce_cpu_online() on all CPUs which are online when
2689 * the state is installed.
2691 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2692 mce_cpu_online, mce_cpu_pre_down);
2694 goto err_out_online;
2696 register_syscore_ops(&mce_syscore_ops);
2701 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2704 free_cpumask_var(mce_device_initialized);
2707 pr_err("Unable to init MCE device (rc: %d)\n", err);
2711 device_initcall_sync(mcheck_init_device);
2714 * Old style boot options parsing. Only for compatibility.
2716 static int __init mcheck_disable(char *str)
2718 mca_cfg.disabled = 1;
2721 __setup("nomce", mcheck_disable);
2723 #ifdef CONFIG_DEBUG_FS
2724 struct dentry *mce_get_debugfs_dir(void)
2726 static struct dentry *dmce;
2729 dmce = debugfs_create_dir("mce", NULL);
2734 static void mce_reset(void)
2737 atomic_set(&mce_fake_panicked, 0);
2738 atomic_set(&mce_executing, 0);
2739 atomic_set(&mce_callin, 0);
2740 atomic_set(&global_nwo, 0);
2741 cpumask_setall(&mce_missing_cpus);
2744 static int fake_panic_get(void *data, u64 *val)
2750 static int fake_panic_set(void *data, u64 val)
2757 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2760 static void __init mcheck_debugfs_init(void)
2762 struct dentry *dmce;
2764 dmce = mce_get_debugfs_dir();
2765 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2769 static void __init mcheck_debugfs_init(void) { }
2772 static int __init mcheck_late_init(void)
2774 if (mca_cfg.recovery)
2775 enable_copy_mc_fragile();
2777 mcheck_debugfs_init();
2780 * Flush out everything that has been logged during early boot, now that
2781 * everything has been initialized (workqueues, decoders, ...).
2783 mce_schedule_work();
2787 late_initcall(mcheck_late_init);