1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
70 DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
73 /* One object for each MCE bank, shared by all CPUs */
75 struct device_attribute attr; /* device attribute */
76 char attrname[ATTR_LEN]; /* attribute name */
77 u8 bank; /* bank number */
79 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
81 struct mce_vendor_flags mce_flags __read_mostly;
83 struct mca_config mca_cfg __read_mostly = {
88 static DEFINE_PER_CPU(struct mce, mces_seen);
89 static unsigned long mce_need_notify;
92 * MCA banks polled by the period polling timer for corrected events.
93 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
95 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
96 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
100 * MCA banks controlled through firmware first for corrected errors.
101 * This is a global list of banks for which we won't enable CMCI and we
102 * won't poll. Firmware controls these banks and is responsible for
103 * reporting corrected errors through GHES. Uncorrected/recoverable
104 * errors are still notified through a machine check.
106 mce_banks_t mce_banks_ce_disabled;
108 static struct work_struct mce_work;
109 static struct irq_work mce_irq_work;
112 * CPU/chipset specific EDAC code can register a notifier call here to print
113 * MCE errors in a human-readable form.
115 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
117 /* Do initial initialization of a struct mce */
118 void mce_setup(struct mce *m)
120 memset(m, 0, sizeof(struct mce));
121 m->cpu = m->extcpu = smp_processor_id();
122 /* need the internal __ version to avoid deadlocks */
123 m->time = __ktime_get_real_seconds();
124 m->cpuvendor = boot_cpu_data.x86_vendor;
125 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
129 m->ppin = cpu_data(m->extcpu).ppin;
130 m->microcode = boot_cpu_data.microcode;
133 DEFINE_PER_CPU(struct mce, injectm);
134 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
136 void mce_log(struct mce *m)
138 if (!mce_gen_pool_add(m))
139 irq_work_queue(&mce_irq_work);
141 EXPORT_SYMBOL_GPL(mce_log);
143 void mce_register_decode_chain(struct notifier_block *nb)
145 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
146 nb->priority > MCE_PRIO_HIGHEST))
149 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
151 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
153 void mce_unregister_decode_chain(struct notifier_block *nb)
155 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
157 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
159 static void __print_mce(struct mce *m)
161 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
163 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
164 m->mcgstatus, m->bank, m->status);
167 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
168 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
171 if (m->cs == __KERNEL_CS)
172 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
176 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
178 pr_cont("ADDR %llx ", m->addr);
180 pr_cont("MISC %llx ", m->misc);
182 pr_cont("PPIN %llx ", m->ppin);
184 if (mce_flags.smca) {
186 pr_cont("SYND %llx ", m->synd);
188 pr_cont("IPID %llx ", m->ipid);
194 * Note this output is parsed by external tools and old fields
195 * should not be changed.
197 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
198 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
202 static void print_mce(struct mce *m)
206 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
207 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
210 #define PANIC_TIMEOUT 5 /* 5 seconds */
212 static atomic_t mce_panicked;
214 static int fake_panic;
215 static atomic_t mce_fake_panicked;
217 /* Panic in progress. Enable interrupts and wait for final IPI */
218 static void wait_for_panic(void)
220 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
224 while (timeout-- > 0)
226 if (panic_timeout == 0)
227 panic_timeout = mca_cfg.panic_timeout;
228 panic("Panicing machine check CPU died");
231 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
233 struct llist_node *pending;
234 struct mce_evt_llist *l;
238 * Allow instrumentation around external facilities usage. Not that it
239 * matters a whole lot since the machine is going to panic anyway.
241 instrumentation_begin();
245 * Make sure only one CPU runs in machine check panic
247 if (atomic_inc_return(&mce_panicked) > 1)
254 /* Don't log too much for fake panic */
255 if (atomic_inc_return(&mce_fake_panicked) > 1)
258 pending = mce_gen_pool_prepare_records();
259 /* First print corrected ones that are still unlogged */
260 llist_for_each_entry(l, pending, llnode) {
261 struct mce *m = &l->mce;
262 if (!(m->status & MCI_STATUS_UC)) {
265 apei_err = apei_write_mce(m);
268 /* Now print uncorrected but with the final one last */
269 llist_for_each_entry(l, pending, llnode) {
270 struct mce *m = &l->mce;
271 if (!(m->status & MCI_STATUS_UC))
273 if (!final || mce_cmp(m, final)) {
276 apei_err = apei_write_mce(m);
282 apei_err = apei_write_mce(final);
285 pr_emerg(HW_ERR "Machine check: %s\n", exp);
287 if (panic_timeout == 0)
288 panic_timeout = mca_cfg.panic_timeout;
291 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
294 instrumentation_end();
297 /* Support code for software error injection */
299 static int msr_to_offset(u32 msr)
301 unsigned bank = __this_cpu_read(injectm.bank);
303 if (msr == mca_cfg.rip_msr)
304 return offsetof(struct mce, ip);
305 if (msr == mca_msr_reg(bank, MCA_STATUS))
306 return offsetof(struct mce, status);
307 if (msr == mca_msr_reg(bank, MCA_ADDR))
308 return offsetof(struct mce, addr);
309 if (msr == mca_msr_reg(bank, MCA_MISC))
310 return offsetof(struct mce, misc);
311 if (msr == MSR_IA32_MCG_STATUS)
312 return offsetof(struct mce, mcgstatus);
316 void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
319 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
320 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
321 regs->ip, (void *)regs->ip);
323 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
324 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
327 show_stack_regs(regs);
329 panic("MCA architectural violation!\n");
335 /* MSR access wrappers used for error injection */
336 noinstr u64 mce_rdmsrl(u32 msr)
338 DECLARE_ARGS(val, low, high);
340 if (__this_cpu_read(injectm.finished)) {
344 instrumentation_begin();
346 offset = msr_to_offset(msr);
350 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
352 instrumentation_end();
358 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
359 * architectural violation and needs to be reported to hw vendor. Panic
360 * the box to not allow any further progress.
362 asm volatile("1: rdmsr\n"
364 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE)
365 : EAX_EDX_RET(val, low, high) : "c" (msr));
368 return EAX_EDX_VAL(val, low, high);
371 static noinstr void mce_wrmsrl(u32 msr, u64 v)
375 if (__this_cpu_read(injectm.finished)) {
378 instrumentation_begin();
380 offset = msr_to_offset(msr);
382 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
384 instrumentation_end();
390 high = (u32)(v >> 32);
392 /* See comment in mce_rdmsrl() */
393 asm volatile("1: wrmsr\n"
395 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE)
396 : : "c" (msr), "a"(low), "d" (high) : "memory");
400 * Collect all global (w.r.t. this processor) status about this machine
401 * check into our "mce" struct so that we can use it later to assess
402 * the severity of the problem as we read per-bank specific details.
404 static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs)
407 * Enable instrumentation around mce_setup() which calls external
410 instrumentation_begin();
412 instrumentation_end();
414 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
417 * Get the address of the instruction at the time of
418 * the machine check error.
420 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
425 * When in VM86 mode make the cs look like ring 3
426 * always. This is a lie, but it's better than passing
427 * the additional vm86 bit around everywhere.
429 if (v8086_mode(regs))
432 /* Use accurate RIP reporting if available. */
434 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
438 int mce_available(struct cpuinfo_x86 *c)
440 if (mca_cfg.disabled)
442 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
445 static void mce_schedule_work(void)
447 if (!mce_gen_pool_empty())
448 schedule_work(&mce_work);
451 static void mce_irq_work_cb(struct irq_work *entry)
457 * Check if the address reported by the CPU is in a format we can parse.
458 * It would be possible to add code for most other cases, but all would
459 * be somewhat complicated (e.g. segment offset would require an instruction
460 * parser). So only support physical addresses up to page granularity for now.
462 int mce_usable_address(struct mce *m)
464 if (!(m->status & MCI_STATUS_ADDRV))
467 /* Checks after this one are Intel/Zhaoxin-specific: */
468 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
469 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
472 if (!(m->status & MCI_STATUS_MISCV))
475 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
478 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
483 EXPORT_SYMBOL_GPL(mce_usable_address);
485 bool mce_is_memory_error(struct mce *m)
487 switch (m->cpuvendor) {
489 case X86_VENDOR_HYGON:
490 return amd_mce_is_memory_error(m);
492 case X86_VENDOR_INTEL:
493 case X86_VENDOR_ZHAOXIN:
495 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
497 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
498 * indicating a memory error. Bit 8 is used for indicating a
499 * cache hierarchy error. The combination of bit 2 and bit 3
500 * is used for indicating a `generic' cache hierarchy error
501 * But we can't just blindly check the above bits, because if
502 * bit 11 is set, then it is a bus/interconnect error - and
503 * either way the above bits just gives more detail on what
504 * bus/interconnect error happened. Note that bit 12 can be
505 * ignored, as it's the "filter" bit.
507 return (m->status & 0xef80) == BIT(7) ||
508 (m->status & 0xef00) == BIT(8) ||
509 (m->status & 0xeffc) == 0xc;
515 EXPORT_SYMBOL_GPL(mce_is_memory_error);
517 static bool whole_page(struct mce *m)
519 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
522 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
525 bool mce_is_correctable(struct mce *m)
527 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
530 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
533 if (m->status & MCI_STATUS_UC)
538 EXPORT_SYMBOL_GPL(mce_is_correctable);
540 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
543 struct mce *m = (struct mce *)data;
548 /* Emit the trace record: */
551 set_bit(0, &mce_need_notify);
558 static struct notifier_block early_nb = {
559 .notifier_call = mce_early_notifier,
560 .priority = MCE_PRIO_EARLY,
563 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
566 struct mce *mce = (struct mce *)data;
569 if (!mce || !mce_usable_address(mce))
572 if (mce->severity != MCE_AO_SEVERITY &&
573 mce->severity != MCE_DEFERRED_SEVERITY)
576 pfn = (mce->addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
577 if (!memory_failure(pfn, 0)) {
579 mce->kflags |= MCE_HANDLED_UC;
585 static struct notifier_block mce_uc_nb = {
586 .notifier_call = uc_decode_notifier,
587 .priority = MCE_PRIO_UC,
590 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
593 struct mce *m = (struct mce *)data;
598 if (mca_cfg.print_all || !m->kflags)
604 static struct notifier_block mce_default_nb = {
605 .notifier_call = mce_default_notifier,
606 /* lowest prio, we want it to run last. */
607 .priority = MCE_PRIO_LOWEST,
611 * Read ADDR and MISC registers.
613 static noinstr void mce_read_aux(struct mce *m, int i)
615 if (m->status & MCI_STATUS_MISCV)
616 m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
618 if (m->status & MCI_STATUS_ADDRV) {
619 m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR));
622 * Mask the reported address by the reported granularity.
624 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
625 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
630 smca_extract_err_addr(m);
633 if (mce_flags.smca) {
634 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
636 if (m->status & MCI_STATUS_SYNDV)
637 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
641 DEFINE_PER_CPU(unsigned, mce_poll_count);
644 * Poll for corrected events or events that happened before reset.
645 * Those are just logged through /dev/mcelog.
647 * This is executed in standard interrupt context.
649 * Note: spec recommends to panic for fatal unsignalled
650 * errors here. However this would be quite problematic --
651 * we would need to reimplement the Monarch handling and
652 * it would mess up the exclusion between exception handler
653 * and poll handler -- * so we skip this for now.
654 * These cases should not happen anyways, or only when the CPU
655 * is already totally * confused. In this case it's likely it will
656 * not fully execute the machine check handler either.
658 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
660 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
661 bool error_seen = false;
665 this_cpu_inc(mce_poll_count);
667 mce_gather_info(&m, NULL);
669 if (flags & MCP_TIMESTAMP)
672 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
673 if (!mce_banks[i].ctl || !test_bit(i, *b))
681 m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
683 /* If this entry is not valid, ignore it */
684 if (!(m.status & MCI_STATUS_VAL))
688 * If we are logging everything (at CPU online) or this
689 * is a corrected error, then we must log it.
691 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
695 * Newer Intel systems that support software error
696 * recovery need to make additional checks. Other
697 * CPUs should skip over uncorrected errors, but log
701 if (m.status & MCI_STATUS_UC)
706 /* Log "not enabled" (speculative) errors */
707 if (!(m.status & MCI_STATUS_EN))
711 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
712 * UC == 1 && PCC == 0 && S == 0
714 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
718 * Skip anything else. Presumption is that our read of this
719 * bank is racing with a machine check. Leave the log alone
720 * for do_machine_check() to deal with it.
727 if (flags & MCP_DONTLOG)
731 m.severity = mce_severity(&m, NULL, NULL, false);
733 * Don't get the IP here because it's unlikely to
734 * have anything to do with the actual error location.
737 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
740 if (flags & MCP_QUEUE_LOG)
741 mce_gen_pool_add(&m);
747 * Clear state for this bank.
749 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
753 * Don't clear MCG_STATUS here because it's only defined for
761 EXPORT_SYMBOL_GPL(machine_check_poll);
764 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
765 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
766 * Vol 3B Table 15-20). But this confuses both the code that determines
767 * whether the machine check occurred in kernel or user mode, and also
768 * the severity assessment code. Pretend that EIPV was set, and take the
769 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
771 static __always_inline void
772 quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
776 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
778 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
779 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
780 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
782 (MCI_STATUS_UC|MCI_STATUS_EN|
783 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
784 MCI_STATUS_AR|MCACOD_INSTR))
787 m->mcgstatus |= MCG_STATUS_EIPV;
793 * Disable fast string copy and return from the MCE handler upon the first SRAR
794 * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake
796 * The fast string copy instructions ("REP; MOVS*") could consume an
797 * uncorrectable memory error in the cache line _right after_ the desired region
798 * to copy and raise an MCE with RIP pointing to the instruction _after_ the
800 * This mitigation addresses the issue completely with the caveat of performance
801 * degradation on the CPU affected. This is still better than the OS crashing on
802 * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a
803 * kernel context (e.g., copy_page).
805 * Returns true when fast string copy on CPU has been disabled.
807 static noinstr bool quirk_skylake_repmov(void)
809 u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
810 u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE);
814 * Apply the quirk only to local machine checks, i.e., no broadcast
817 if (!(mcgstatus & MCG_STATUS_LMCES) ||
818 !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
821 mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1));
823 /* Check for a software-recoverable data fetch error. */
825 (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN |
826 MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC |
827 MCI_STATUS_AR | MCI_STATUS_S)) ==
828 (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
829 MCI_STATUS_ADDRV | MCI_STATUS_MISCV |
830 MCI_STATUS_AR | MCI_STATUS_S)) {
831 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
832 mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
833 mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0);
835 instrumentation_begin();
836 pr_err_once("Erratum detected, disable fast string copy instructions.\n");
837 instrumentation_end();
846 * Do a quick check if any of the events requires a panic.
847 * This decides if we keep the events around or clear them.
849 static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
850 struct pt_regs *regs)
855 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
856 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
857 if (!(m->status & MCI_STATUS_VAL))
860 arch___set_bit(i, validp);
861 if (mce_flags.snb_ifu_quirk)
862 quirk_sandybridge_ifu(i, m, regs);
865 if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
875 * Variable to establish order between CPUs while scanning.
876 * Each CPU spins initially until executing is equal its number.
878 static atomic_t mce_executing;
881 * Defines order of CPUs on entry. First CPU becomes Monarch.
883 static atomic_t mce_callin;
886 * Track which CPUs entered the MCA broadcast synchronization and which not in
887 * order to print holdouts.
889 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
892 * Check if a timeout waiting for other CPUs happened.
894 static noinstr int mce_timed_out(u64 *t, const char *msg)
898 /* Enable instrumentation around calls to external facilities */
899 instrumentation_begin();
902 * The others already did panic for some reason.
903 * Bail out like in a timeout.
904 * rmb() to tell the compiler that system_state
905 * might have been modified by someone else.
908 if (atomic_read(&mce_panicked))
910 if (!mca_cfg.monarch_timeout)
912 if ((s64)*t < SPINUNIT) {
913 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
914 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
915 cpumask_pr_args(&mce_missing_cpus));
916 mce_panic(msg, NULL, NULL);
924 touch_nmi_watchdog();
926 instrumentation_end();
932 * The Monarch's reign. The Monarch is the CPU who entered
933 * the machine check handler first. It waits for the others to
934 * raise the exception too and then grades them. When any
935 * error is fatal panic. Only then let the others continue.
937 * The other CPUs entering the MCE handler will be controlled by the
938 * Monarch. They are called Subjects.
940 * This way we prevent any potential data corruption in a unrecoverable case
941 * and also makes sure always all CPU's errors are examined.
943 * Also this detects the case of a machine check event coming from outer
944 * space (not detected by any CPUs) In this case some external agent wants
945 * us to shut down, so panic too.
947 * The other CPUs might still decide to panic if the handler happens
948 * in a unrecoverable place, but in this case the system is in a semi-stable
949 * state and won't corrupt anything by itself. It's ok to let the others
950 * continue for a bit first.
952 * All the spin loops have timeouts; when a timeout happens a CPU
953 * typically elects itself to be Monarch.
955 static void mce_reign(void)
958 struct mce *m = NULL;
959 int global_worst = 0;
963 * This CPU is the Monarch and the other CPUs have run
964 * through their handlers.
965 * Grade the severity of the errors of all the CPUs.
967 for_each_possible_cpu(cpu) {
968 struct mce *mtmp = &per_cpu(mces_seen, cpu);
970 if (mtmp->severity > global_worst) {
971 global_worst = mtmp->severity;
972 m = &per_cpu(mces_seen, cpu);
977 * Cannot recover? Panic here then.
978 * This dumps all the mces in the log buffer and stops the
981 if (m && global_worst >= MCE_PANIC_SEVERITY) {
982 /* call mce_severity() to get "msg" for panic */
983 mce_severity(m, NULL, &msg, true);
984 mce_panic("Fatal machine check", m, msg);
988 * For UC somewhere we let the CPU who detects it handle it.
989 * Also must let continue the others, otherwise the handling
990 * CPU could deadlock on a lock.
994 * No machine check event found. Must be some external
995 * source or one CPU is hung. Panic.
997 if (global_worst <= MCE_KEEP_SEVERITY)
998 mce_panic("Fatal machine check from unknown source", NULL, NULL);
1001 * Now clear all the mces_seen so that they don't reappear on
1004 for_each_possible_cpu(cpu)
1005 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
1008 static atomic_t global_nwo;
1011 * Start of Monarch synchronization. This waits until all CPUs have
1012 * entered the exception handler and then determines if any of them
1013 * saw a fatal event that requires panic. Then it executes them
1014 * in the entry order.
1015 * TBD double check parallel CPU hotunplug
1017 static noinstr int mce_start(int *no_way_out)
1019 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1020 int order, ret = -1;
1025 raw_atomic_add(*no_way_out, &global_nwo);
1027 * Rely on the implied barrier below, such that global_nwo
1028 * is updated before mce_callin.
1030 order = raw_atomic_inc_return(&mce_callin);
1031 arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1033 /* Enable instrumentation around calls to external facilities */
1034 instrumentation_begin();
1037 * Wait for everyone.
1039 while (raw_atomic_read(&mce_callin) != num_online_cpus()) {
1040 if (mce_timed_out(&timeout,
1041 "Timeout: Not all CPUs entered broadcast exception handler")) {
1042 raw_atomic_set(&global_nwo, 0);
1049 * mce_callin should be read before global_nwo
1055 * Monarch: Starts executing now, the others wait.
1057 raw_atomic_set(&mce_executing, 1);
1060 * Subject: Now start the scanning loop one by one in
1061 * the original callin order.
1062 * This way when there are any shared banks it will be
1063 * only seen by one CPU before cleared, avoiding duplicates.
1065 while (raw_atomic_read(&mce_executing) < order) {
1066 if (mce_timed_out(&timeout,
1067 "Timeout: Subject CPUs unable to finish machine check processing")) {
1068 raw_atomic_set(&global_nwo, 0);
1076 * Cache the global no_way_out state.
1078 *no_way_out = raw_atomic_read(&global_nwo);
1083 instrumentation_end();
1089 * Synchronize between CPUs after main scanning loop.
1090 * This invokes the bulk of the Monarch processing.
1092 static noinstr int mce_end(int order)
1094 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1097 /* Allow instrumentation around external facilities. */
1098 instrumentation_begin();
1106 * Allow others to run.
1108 atomic_inc(&mce_executing);
1112 * Monarch: Wait for everyone to go through their scanning
1115 while (atomic_read(&mce_executing) <= num_online_cpus()) {
1116 if (mce_timed_out(&timeout,
1117 "Timeout: Monarch CPU unable to finish machine check processing"))
1127 * Subject: Wait for Monarch to finish.
1129 while (atomic_read(&mce_executing) != 0) {
1130 if (mce_timed_out(&timeout,
1131 "Timeout: Monarch CPU did not finish machine check processing"))
1137 * Don't reset anything. That's done by the Monarch.
1144 * Reset all global state.
1147 atomic_set(&global_nwo, 0);
1148 atomic_set(&mce_callin, 0);
1149 cpumask_setall(&mce_missing_cpus);
1153 * Let others run again.
1155 atomic_set(&mce_executing, 0);
1158 instrumentation_end();
1163 static __always_inline void mce_clear_state(unsigned long *toclear)
1167 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1168 if (arch_test_bit(i, toclear))
1169 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1174 * Cases where we avoid rendezvous handler timeout:
1175 * 1) If this CPU is offline.
1177 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1178 * skip those CPUs which remain looping in the 1st kernel - see
1179 * crash_nmi_callback().
1181 * Note: there still is a small window between kexec-ing and the new,
1182 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1183 * might not get handled properly.
1185 static noinstr bool mce_check_crashing_cpu(void)
1187 unsigned int cpu = smp_processor_id();
1189 if (arch_cpu_is_offline(cpu) ||
1190 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1193 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1195 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1196 if (mcgstatus & MCG_STATUS_LMCES)
1200 if (mcgstatus & MCG_STATUS_RIPV) {
1201 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1208 static __always_inline int
1209 __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1210 unsigned long *toclear, unsigned long *valid_banks, int no_way_out,
1213 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1214 struct mca_config *cfg = &mca_cfg;
1215 int severity, i, taint = 0;
1217 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1218 arch___clear_bit(i, toclear);
1219 if (!arch_test_bit(i, valid_banks))
1222 if (!mce_banks[i].ctl)
1229 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
1230 if (!(m->status & MCI_STATUS_VAL))
1234 * Corrected or non-signaled errors are handled by
1235 * machine_check_poll(). Leave them alone, unless this panics.
1237 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1241 /* Set taint even when machine check was not enabled. */
1244 severity = mce_severity(m, regs, NULL, true);
1247 * When machine check was for corrected/deferred handler don't
1248 * touch, unless we're panicking.
1250 if ((severity == MCE_KEEP_SEVERITY ||
1251 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1254 arch___set_bit(i, toclear);
1256 /* Machine check event was not enabled. Clear, but ignore. */
1257 if (severity == MCE_NO_SEVERITY)
1262 /* assuming valid severity level != 0 */
1263 m->severity = severity;
1266 * Enable instrumentation around the mce_log() call which is
1267 * done in #MC context, where instrumentation is disabled.
1269 instrumentation_begin();
1271 instrumentation_end();
1273 if (severity > *worst) {
1279 /* mce_clear_state will clear *final, save locally for use later */
1285 static void kill_me_now(struct callback_head *ch)
1287 struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
1293 static void kill_me_maybe(struct callback_head *cb)
1295 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1296 int flags = MF_ACTION_REQUIRED;
1301 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1304 flags |= MF_MUST_KILL;
1306 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1307 ret = memory_failure(pfn, flags);
1309 set_mce_nospec(pfn);
1315 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1316 * to the current process with the proper error info,
1317 * -EOPNOTSUPP means hwpoison_filter() filtered the error event,
1319 * In both cases, no further processing is required.
1321 if (ret == -EHWPOISON || ret == -EOPNOTSUPP)
1324 pr_err("Memory error not recovered");
1328 static void kill_me_never(struct callback_head *cb)
1330 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1334 pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr);
1335 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1336 if (!memory_failure(pfn, 0))
1337 set_mce_nospec(pfn);
1340 static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *))
1342 int count = ++current->mce_count;
1344 /* First call, save all the details */
1346 current->mce_addr = m->addr;
1347 current->mce_kflags = m->kflags;
1348 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1349 current->mce_whole_page = whole_page(m);
1350 current->mce_kill_me.func = func;
1353 /* Ten is likely overkill. Don't expect more than two faults before task_work() */
1355 mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
1357 /* Second or later call, make sure page address matches the one from first call */
1358 if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
1359 mce_panic("Consecutive machine checks to different user pages", m, msg);
1361 /* Do not call task_work_add() more than once */
1365 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1368 /* Handle unconfigured int18 (should never happen) */
1369 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1371 instrumentation_begin();
1372 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1373 smp_processor_id());
1374 instrumentation_end();
1378 * The actual machine check handler. This only handles real exceptions when
1379 * something got corrupted coming in through int 18.
1381 * This is executed in #MC context not subject to normal locking rules.
1382 * This implies that most kernel services cannot be safely used. Don't even
1383 * think about putting a printk in there!
1385 * On Intel systems this is entered on all CPUs in parallel through
1386 * MCE broadcast. However some CPUs might be broken beyond repair,
1387 * so be always careful when synchronizing with others.
1389 * Tracing and kprobes are disabled: if we interrupted a kernel context
1390 * with IF=1, we need to minimize stack usage. There are also recursion
1391 * issues: if the machine check was due to a failure of the memory
1392 * backing the user stack, tracing that reads the user stack will cause
1393 * potentially infinite recursion.
1395 * Currently, the #MC handler calls out to a number of external facilities
1396 * and, therefore, allows instrumentation around them. The optimal thing to
1397 * have would be to do the absolutely minimal work required in #MC context
1398 * and have instrumentation disabled only around that. Further processing can
1399 * then happen in process context where instrumentation is allowed. Achieving
1400 * that requires careful auditing and modifications. Until then, the code
1401 * allows instrumentation temporarily, where required. *
1403 noinstr void do_machine_check(struct pt_regs *regs)
1405 int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0;
1406 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 };
1407 DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 };
1408 struct mce m, *final;
1411 if (unlikely(mce_flags.p5))
1412 return pentium_machine_check(regs);
1413 else if (unlikely(mce_flags.winchip))
1414 return winchip_machine_check(regs);
1415 else if (unlikely(!mca_cfg.initialized))
1416 return unexpected_machine_check(regs);
1418 if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov())
1422 * Establish sequential order between the CPUs entering the machine
1428 * If no_way_out gets set, there is no safe way to recover from this
1434 * If kill_current_task is not set, there might be a way to recover from this
1437 kill_current_task = 0;
1440 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1445 this_cpu_inc(mce_exception_count);
1447 mce_gather_info(&m, regs);
1450 final = this_cpu_ptr(&mces_seen);
1453 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1458 * When no restart IP might need to kill or panic.
1459 * Assume the worst for now, but if we find the
1460 * severity is MCE_AR_SEVERITY we have other options.
1462 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1463 kill_current_task = 1;
1465 * Check if this MCE is signaled to only this logical processor,
1466 * on Intel, Zhaoxin only.
1468 if (m.cpuvendor == X86_VENDOR_INTEL ||
1469 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1470 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1473 * Local machine check may already know that we have to panic.
1474 * Broadcast machine check begins rendezvous in mce_start()
1475 * Go through all banks in exclusion of the other CPUs. This way we
1476 * don't report duplicated events on shared banks because the first one
1477 * to see it will clear it.
1481 mce_panic("Fatal local machine check", &m, msg);
1483 order = mce_start(&no_way_out);
1486 taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1489 mce_clear_state(toclear);
1492 * Do most of the synchronization with other CPUs.
1493 * When there's any problem use only local no_way_out state.
1496 if (mce_end(order) < 0) {
1498 no_way_out = worst >= MCE_PANIC_SEVERITY;
1501 mce_panic("Fatal machine check on current CPU", &m, msg);
1505 * If there was a fatal machine check we should have
1506 * already called mce_panic earlier in this function.
1507 * Since we re-read the banks, we might have found
1508 * something new. Check again to see if we found a
1509 * fatal error. We call "mce_severity()" again to
1510 * make sure we have the right "msg".
1512 if (worst >= MCE_PANIC_SEVERITY) {
1513 mce_severity(&m, regs, &msg, true);
1514 mce_panic("Local fatal machine check!", &m, msg);
1519 * Enable instrumentation around the external facilities like task_work_add()
1520 * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this
1521 * properly would need a lot more involved reorganization.
1523 instrumentation_begin();
1526 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1528 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1531 /* Fault was in user mode and we need to take some action */
1532 if ((m.cs & 3) == 3) {
1533 /* If this triggers there is no way to recover. Die hard. */
1534 BUG_ON(!on_thread_stack() || !user_mode(regs));
1536 if (!mce_usable_address(&m))
1537 queue_task_work(&m, msg, kill_me_now);
1539 queue_task_work(&m, msg, kill_me_maybe);
1543 * Handle an MCE which has happened in kernel space but from
1544 * which the kernel can recover: ex_has_fault_handler() has
1545 * already verified that the rIP at which the error happened is
1546 * a rIP from which the kernel can recover (by jumping to
1547 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1548 * corresponding exception handler which would do that is the
1551 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1552 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1553 mce_panic("Failed kernel mode recovery", &m, msg);
1556 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1557 queue_task_work(&m, msg, kill_me_never);
1561 instrumentation_end();
1564 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1566 EXPORT_SYMBOL_GPL(do_machine_check);
1568 #ifndef CONFIG_MEMORY_FAILURE
1569 int memory_failure(unsigned long pfn, int flags)
1571 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1572 BUG_ON(flags & MF_ACTION_REQUIRED);
1573 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1574 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1582 * Periodic polling timer for "silent" machine check errors. If the
1583 * poller finds an MCE, poll 2x faster. When the poller finds no more
1584 * errors, poll 2x slower (up to check_interval seconds).
1586 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1588 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1589 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1591 static unsigned long mce_adjust_timer_default(unsigned long interval)
1596 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1598 static void __start_timer(struct timer_list *t, unsigned long interval)
1600 unsigned long when = jiffies + interval;
1601 unsigned long flags;
1603 local_irq_save(flags);
1605 if (!timer_pending(t) || time_before(when, t->expires))
1606 mod_timer(t, round_jiffies(when));
1608 local_irq_restore(flags);
1611 static void mce_timer_fn(struct timer_list *t)
1613 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1616 WARN_ON(cpu_t != t);
1618 iv = __this_cpu_read(mce_next_interval);
1620 if (mce_available(this_cpu_ptr(&cpu_info))) {
1621 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1623 if (mce_intel_cmci_poll()) {
1624 iv = mce_adjust_timer(iv);
1630 * Alert userspace if needed. If we logged an MCE, reduce the polling
1631 * interval, otherwise increase the polling interval.
1633 if (mce_notify_irq())
1634 iv = max(iv / 2, (unsigned long) HZ/100);
1636 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1639 __this_cpu_write(mce_next_interval, iv);
1640 __start_timer(t, iv);
1644 * Ensure that the timer is firing in @interval from now.
1646 void mce_timer_kick(unsigned long interval)
1648 struct timer_list *t = this_cpu_ptr(&mce_timer);
1649 unsigned long iv = __this_cpu_read(mce_next_interval);
1651 __start_timer(t, interval);
1654 __this_cpu_write(mce_next_interval, interval);
1657 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1658 static void mce_timer_delete_all(void)
1662 for_each_online_cpu(cpu)
1663 del_timer_sync(&per_cpu(mce_timer, cpu));
1667 * Notify the user(s) about new machine check events.
1668 * Can be called from interrupt context, but not from machine check/NMI
1671 int mce_notify_irq(void)
1673 /* Not more than two messages every minute */
1674 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1676 if (test_and_clear_bit(0, &mce_need_notify)) {
1679 if (__ratelimit(&ratelimit))
1680 pr_info(HW_ERR "Machine check events logged\n");
1686 EXPORT_SYMBOL_GPL(mce_notify_irq);
1688 static void __mcheck_cpu_mce_banks_init(void)
1690 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1691 u8 n_banks = this_cpu_read(mce_num_banks);
1694 for (i = 0; i < n_banks; i++) {
1695 struct mce_bank *b = &mce_banks[i];
1698 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1699 * the required vendor quirks before
1700 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1708 * Initialize Machine Checks for a CPU.
1710 static void __mcheck_cpu_cap_init(void)
1715 rdmsrl(MSR_IA32_MCG_CAP, cap);
1717 b = cap & MCG_BANKCNT_MASK;
1719 if (b > MAX_NR_BANKS) {
1720 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1721 smp_processor_id(), MAX_NR_BANKS, b);
1725 this_cpu_write(mce_num_banks, b);
1727 __mcheck_cpu_mce_banks_init();
1729 /* Use accurate RIP reporting if available. */
1730 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1731 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1733 if (cap & MCG_SER_P)
1737 static void __mcheck_cpu_init_generic(void)
1739 enum mcp_flags m_fl = 0;
1740 mce_banks_t all_banks;
1743 if (!mca_cfg.bootlog)
1747 * Log the machine checks left over from the previous reset. Log them
1748 * only, do not start processing them. That will happen in mcheck_late_init()
1749 * when all consumers have been registered on the notifier chain.
1751 bitmap_fill(all_banks, MAX_NR_BANKS);
1752 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1754 cr4_set_bits(X86_CR4_MCE);
1756 rdmsrl(MSR_IA32_MCG_CAP, cap);
1757 if (cap & MCG_CTL_P)
1758 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1761 static void __mcheck_cpu_init_clear_banks(void)
1763 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1766 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1767 struct mce_bank *b = &mce_banks[i];
1771 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
1772 wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1777 * Do a final check to see if there are any unused/RAZ banks.
1779 * This must be done after the banks have been initialized and any quirks have
1782 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1783 * Otherwise, a user who disables a bank will not be able to re-enable it
1784 * without a system reboot.
1786 static void __mcheck_cpu_check_banks(void)
1788 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1792 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1793 struct mce_bank *b = &mce_banks[i];
1798 rdmsrl(mca_msr_reg(i, MCA_CTL), msrval);
1803 /* Add per CPU specific workarounds here */
1804 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1806 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1807 struct mca_config *cfg = &mca_cfg;
1809 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1810 pr_info("unknown CPU type - not enabling MCE support\n");
1814 /* This should be disabled by the BIOS, but isn't always */
1815 if (c->x86_vendor == X86_VENDOR_AMD) {
1816 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1818 * disable GART TBL walk error reporting, which
1819 * trips off incorrectly with the IOMMU & 3ware
1822 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1824 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1826 * Lots of broken BIOS around that don't clear them
1827 * by default and leave crap in there. Don't log:
1832 * Various K7s with broken bank 0 around. Always disable
1835 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1836 mce_banks[0].ctl = 0;
1839 * overflow_recov is supported for F15h Models 00h-0fh
1840 * even though we don't have a CPUID bit for it.
1842 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1843 mce_flags.overflow_recov = 1;
1847 if (c->x86_vendor == X86_VENDOR_INTEL) {
1849 * SDM documents that on family 6 bank 0 should not be written
1850 * because it aliases to another special BIOS controlled
1852 * But it's not aliased anymore on model 0x1a+
1853 * Don't ignore bank 0 completely because there could be a
1854 * valid event later, merely don't write CTL0.
1857 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1858 mce_banks[0].init = false;
1861 * All newer Intel systems support MCE broadcasting. Enable
1862 * synchronization with a one second timeout.
1864 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1865 cfg->monarch_timeout < 0)
1866 cfg->monarch_timeout = USEC_PER_SEC;
1869 * There are also broken BIOSes on some Pentium M and
1872 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1875 if (c->x86 == 6 && c->x86_model == 45)
1876 mce_flags.snb_ifu_quirk = 1;
1879 * Skylake, Cascacde Lake and Cooper Lake require a quirk on
1882 if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X)
1883 mce_flags.skx_repmov_quirk = 1;
1886 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1888 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1889 * synchronization with a one second timeout.
1891 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1892 if (cfg->monarch_timeout < 0)
1893 cfg->monarch_timeout = USEC_PER_SEC;
1897 if (cfg->monarch_timeout < 0)
1898 cfg->monarch_timeout = 0;
1899 if (cfg->bootlog != 0)
1900 cfg->panic_timeout = 30;
1905 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1910 switch (c->x86_vendor) {
1911 case X86_VENDOR_INTEL:
1912 intel_p5_mcheck_init(c);
1915 case X86_VENDOR_CENTAUR:
1916 winchip_mcheck_init(c);
1917 mce_flags.winchip = 1;
1927 * Init basic CPU features needed for early decoding of MCEs.
1929 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1931 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1932 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1933 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1934 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1935 mce_flags.amd_threshold = 1;
1939 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1941 struct mca_config *cfg = &mca_cfg;
1944 * All newer Centaur CPUs support MCE broadcasting. Enable
1945 * synchronization with a one second timeout.
1947 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1949 if (cfg->monarch_timeout < 0)
1950 cfg->monarch_timeout = USEC_PER_SEC;
1954 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1956 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1959 * These CPUs have MCA bank 8 which reports only one error type called
1960 * SVAD (System View Address Decoder). The reporting of that error is
1961 * controlled by IA32_MC8.CTL.0.
1963 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1964 * virtual machines start and result in a system panic. Always disable
1965 * bank 8 SVAD error by default.
1967 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1968 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1969 if (this_cpu_read(mce_num_banks) > 8)
1970 mce_banks[8].ctl = 0;
1975 mce_adjust_timer = cmci_intel_adjust_timer;
1978 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1983 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1985 switch (c->x86_vendor) {
1986 case X86_VENDOR_INTEL:
1987 mce_intel_feature_init(c);
1988 mce_adjust_timer = cmci_intel_adjust_timer;
1991 case X86_VENDOR_AMD: {
1992 mce_amd_feature_init(c);
1996 case X86_VENDOR_HYGON:
1997 mce_hygon_feature_init(c);
2000 case X86_VENDOR_CENTAUR:
2001 mce_centaur_feature_init(c);
2004 case X86_VENDOR_ZHAOXIN:
2005 mce_zhaoxin_feature_init(c);
2013 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
2015 switch (c->x86_vendor) {
2016 case X86_VENDOR_INTEL:
2017 mce_intel_feature_clear(c);
2020 case X86_VENDOR_ZHAOXIN:
2021 mce_zhaoxin_feature_clear(c);
2029 static void mce_start_timer(struct timer_list *t)
2031 unsigned long iv = check_interval * HZ;
2033 if (mca_cfg.ignore_ce || !iv)
2036 this_cpu_write(mce_next_interval, iv);
2037 __start_timer(t, iv);
2040 static void __mcheck_cpu_setup_timer(void)
2042 struct timer_list *t = this_cpu_ptr(&mce_timer);
2044 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2047 static void __mcheck_cpu_init_timer(void)
2049 struct timer_list *t = this_cpu_ptr(&mce_timer);
2051 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2055 bool filter_mce(struct mce *m)
2057 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2058 return amd_filter_mce(m);
2059 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2060 return intel_filter_mce(m);
2065 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2067 irqentry_state_t irq_state;
2069 WARN_ON_ONCE(user_mode(regs));
2072 * Only required when from kernel mode. See
2073 * mce_check_crashing_cpu() for details.
2075 if (mca_cfg.initialized && mce_check_crashing_cpu())
2078 irq_state = irqentry_nmi_enter(regs);
2080 do_machine_check(regs);
2082 irqentry_nmi_exit(regs, irq_state);
2085 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2087 irqentry_enter_from_user_mode(regs);
2089 do_machine_check(regs);
2091 irqentry_exit_to_user_mode(regs);
2094 #ifdef CONFIG_X86_64
2095 /* MCE hit kernel mode */
2096 DEFINE_IDTENTRY_MCE(exc_machine_check)
2100 dr7 = local_db_save();
2101 exc_machine_check_kernel(regs);
2102 local_db_restore(dr7);
2105 /* The user mode variant. */
2106 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2110 dr7 = local_db_save();
2111 exc_machine_check_user(regs);
2112 local_db_restore(dr7);
2115 /* 32bit unified entry point */
2116 DEFINE_IDTENTRY_RAW(exc_machine_check)
2120 dr7 = local_db_save();
2121 if (user_mode(regs))
2122 exc_machine_check_user(regs);
2124 exc_machine_check_kernel(regs);
2125 local_db_restore(dr7);
2130 * Called for each booted CPU to set up machine checks.
2131 * Must be called with preempt off:
2133 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2135 if (mca_cfg.disabled)
2138 if (__mcheck_cpu_ancient_init(c))
2141 if (!mce_available(c))
2144 __mcheck_cpu_cap_init();
2146 if (__mcheck_cpu_apply_quirks(c) < 0) {
2147 mca_cfg.disabled = 1;
2151 if (mce_gen_pool_init()) {
2152 mca_cfg.disabled = 1;
2153 pr_emerg("Couldn't allocate MCE records pool!\n");
2157 mca_cfg.initialized = 1;
2159 __mcheck_cpu_init_early(c);
2160 __mcheck_cpu_init_generic();
2161 __mcheck_cpu_init_vendor(c);
2162 __mcheck_cpu_init_clear_banks();
2163 __mcheck_cpu_check_banks();
2164 __mcheck_cpu_setup_timer();
2168 * Called for each booted CPU to clear some machine checks opt-ins
2170 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2172 if (mca_cfg.disabled)
2175 if (!mce_available(c))
2179 * Possibly to clear general settings generic to x86
2180 * __mcheck_cpu_clear_generic(c);
2182 __mcheck_cpu_clear_vendor(c);
2186 static void __mce_disable_bank(void *arg)
2188 int bank = *((int *)arg);
2189 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2190 cmci_disable_bank(bank);
2193 void mce_disable_bank(int bank)
2195 if (bank >= this_cpu_read(mce_num_banks)) {
2197 "Ignoring request to disable invalid MCA bank %d.\n",
2201 set_bit(bank, mce_banks_ce_disabled);
2202 on_each_cpu(__mce_disable_bank, &bank, 1);
2206 * mce=off Disables machine check
2207 * mce=no_cmci Disables CMCI
2208 * mce=no_lmce Disables LMCE
2209 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2210 * mce=print_all Print all machine check logs to console
2211 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2212 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2213 * monarchtimeout is how long to wait for other CPUs on machine
2214 * check, or 0 to not wait
2215 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2217 * mce=nobootlog Don't log MCEs from before booting.
2218 * mce=bios_cmci_threshold Don't program the CMCI threshold
2219 * mce=recovery force enable copy_mc_fragile()
2221 static int __init mcheck_enable(char *str)
2223 struct mca_config *cfg = &mca_cfg;
2231 if (!strcmp(str, "off"))
2233 else if (!strcmp(str, "no_cmci"))
2234 cfg->cmci_disabled = true;
2235 else if (!strcmp(str, "no_lmce"))
2236 cfg->lmce_disabled = 1;
2237 else if (!strcmp(str, "dont_log_ce"))
2238 cfg->dont_log_ce = true;
2239 else if (!strcmp(str, "print_all"))
2240 cfg->print_all = true;
2241 else if (!strcmp(str, "ignore_ce"))
2242 cfg->ignore_ce = true;
2243 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2244 cfg->bootlog = (str[0] == 'b');
2245 else if (!strcmp(str, "bios_cmci_threshold"))
2246 cfg->bios_cmci_threshold = 1;
2247 else if (!strcmp(str, "recovery"))
2249 else if (isdigit(str[0]))
2250 get_option(&str, &(cfg->monarch_timeout));
2252 pr_info("mce argument %s ignored. Please use /sys\n", str);
2257 __setup("mce", mcheck_enable);
2259 int __init mcheck_init(void)
2261 mce_register_decode_chain(&early_nb);
2262 mce_register_decode_chain(&mce_uc_nb);
2263 mce_register_decode_chain(&mce_default_nb);
2265 INIT_WORK(&mce_work, mce_gen_pool_process);
2266 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2272 * mce_syscore: PM support
2276 * Disable machine checks on suspend and shutdown. We can't really handle
2279 static void mce_disable_error_reporting(void)
2281 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2284 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2285 struct mce_bank *b = &mce_banks[i];
2288 wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
2293 static void vendor_disable_error_reporting(void)
2296 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2297 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2298 * is bad, since it will inhibit reporting for all shared resources on
2299 * the socket like the last level cache (LLC), the integrated memory
2300 * controller (iMC), etc.
2302 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2303 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2304 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2305 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2308 mce_disable_error_reporting();
2311 static int mce_syscore_suspend(void)
2313 vendor_disable_error_reporting();
2317 static void mce_syscore_shutdown(void)
2319 vendor_disable_error_reporting();
2323 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2324 * Only one CPU is active at this time, the others get re-added later using
2327 static void mce_syscore_resume(void)
2329 __mcheck_cpu_init_generic();
2330 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2331 __mcheck_cpu_init_clear_banks();
2334 static struct syscore_ops mce_syscore_ops = {
2335 .suspend = mce_syscore_suspend,
2336 .shutdown = mce_syscore_shutdown,
2337 .resume = mce_syscore_resume,
2341 * mce_device: Sysfs support
2344 static void mce_cpu_restart(void *data)
2346 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2348 __mcheck_cpu_init_generic();
2349 __mcheck_cpu_init_clear_banks();
2350 __mcheck_cpu_init_timer();
2353 /* Reinit MCEs after user configuration changes */
2354 static void mce_restart(void)
2356 mce_timer_delete_all();
2357 on_each_cpu(mce_cpu_restart, NULL, 1);
2358 mce_schedule_work();
2361 /* Toggle features for corrected errors */
2362 static void mce_disable_cmci(void *data)
2364 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2369 static void mce_enable_ce(void *all)
2371 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2376 __mcheck_cpu_init_timer();
2379 static struct bus_type mce_subsys = {
2380 .name = "machinecheck",
2381 .dev_name = "machinecheck",
2384 DEFINE_PER_CPU(struct device *, mce_device);
2386 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2388 return container_of(attr, struct mce_bank_dev, attr);
2391 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2394 u8 bank = attr_to_bank(attr)->bank;
2397 if (bank >= per_cpu(mce_num_banks, s->id))
2400 b = &per_cpu(mce_banks_array, s->id)[bank];
2405 return sprintf(buf, "%llx\n", b->ctl);
2408 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2409 const char *buf, size_t size)
2411 u8 bank = attr_to_bank(attr)->bank;
2415 if (kstrtou64(buf, 0, &new) < 0)
2418 if (bank >= per_cpu(mce_num_banks, s->id))
2421 b = &per_cpu(mce_banks_array, s->id)[bank];
2432 static ssize_t set_ignore_ce(struct device *s,
2433 struct device_attribute *attr,
2434 const char *buf, size_t size)
2438 if (kstrtou64(buf, 0, &new) < 0)
2441 mutex_lock(&mce_sysfs_mutex);
2442 if (mca_cfg.ignore_ce ^ !!new) {
2444 /* disable ce features */
2445 mce_timer_delete_all();
2446 on_each_cpu(mce_disable_cmci, NULL, 1);
2447 mca_cfg.ignore_ce = true;
2449 /* enable ce features */
2450 mca_cfg.ignore_ce = false;
2451 on_each_cpu(mce_enable_ce, (void *)1, 1);
2454 mutex_unlock(&mce_sysfs_mutex);
2459 static ssize_t set_cmci_disabled(struct device *s,
2460 struct device_attribute *attr,
2461 const char *buf, size_t size)
2465 if (kstrtou64(buf, 0, &new) < 0)
2468 mutex_lock(&mce_sysfs_mutex);
2469 if (mca_cfg.cmci_disabled ^ !!new) {
2472 on_each_cpu(mce_disable_cmci, NULL, 1);
2473 mca_cfg.cmci_disabled = true;
2476 mca_cfg.cmci_disabled = false;
2477 on_each_cpu(mce_enable_ce, NULL, 1);
2480 mutex_unlock(&mce_sysfs_mutex);
2485 static ssize_t store_int_with_restart(struct device *s,
2486 struct device_attribute *attr,
2487 const char *buf, size_t size)
2489 unsigned long old_check_interval = check_interval;
2490 ssize_t ret = device_store_ulong(s, attr, buf, size);
2492 if (check_interval == old_check_interval)
2495 mutex_lock(&mce_sysfs_mutex);
2497 mutex_unlock(&mce_sysfs_mutex);
2502 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2503 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2504 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2506 static struct dev_ext_attribute dev_attr_check_interval = {
2507 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2511 static struct dev_ext_attribute dev_attr_ignore_ce = {
2512 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2516 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2517 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2518 &mca_cfg.cmci_disabled
2521 static struct device_attribute *mce_device_attrs[] = {
2522 &dev_attr_check_interval.attr,
2523 #ifdef CONFIG_X86_MCELOG_LEGACY
2526 &dev_attr_monarch_timeout.attr,
2527 &dev_attr_dont_log_ce.attr,
2528 &dev_attr_print_all.attr,
2529 &dev_attr_ignore_ce.attr,
2530 &dev_attr_cmci_disabled.attr,
2534 static cpumask_var_t mce_device_initialized;
2536 static void mce_device_release(struct device *dev)
2541 /* Per CPU device init. All of the CPUs still share the same bank device: */
2542 static int mce_device_create(unsigned int cpu)
2548 if (!mce_available(&boot_cpu_data))
2551 dev = per_cpu(mce_device, cpu);
2555 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2559 dev->bus = &mce_subsys;
2560 dev->release = &mce_device_release;
2562 err = device_register(dev);
2568 for (i = 0; mce_device_attrs[i]; i++) {
2569 err = device_create_file(dev, mce_device_attrs[i]);
2573 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2574 err = device_create_file(dev, &mce_bank_devs[j].attr);
2578 cpumask_set_cpu(cpu, mce_device_initialized);
2579 per_cpu(mce_device, cpu) = dev;
2584 device_remove_file(dev, &mce_bank_devs[j].attr);
2587 device_remove_file(dev, mce_device_attrs[i]);
2589 device_unregister(dev);
2594 static void mce_device_remove(unsigned int cpu)
2596 struct device *dev = per_cpu(mce_device, cpu);
2599 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2602 for (i = 0; mce_device_attrs[i]; i++)
2603 device_remove_file(dev, mce_device_attrs[i]);
2605 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2606 device_remove_file(dev, &mce_bank_devs[i].attr);
2608 device_unregister(dev);
2609 cpumask_clear_cpu(cpu, mce_device_initialized);
2610 per_cpu(mce_device, cpu) = NULL;
2613 /* Make sure there are no machine checks on offlined CPUs. */
2614 static void mce_disable_cpu(void)
2616 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2619 if (!cpuhp_tasks_frozen)
2622 vendor_disable_error_reporting();
2625 static void mce_reenable_cpu(void)
2627 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2630 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2633 if (!cpuhp_tasks_frozen)
2635 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2636 struct mce_bank *b = &mce_banks[i];
2639 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
2643 static int mce_cpu_dead(unsigned int cpu)
2645 mce_intel_hcpu_update(cpu);
2647 /* intentionally ignoring frozen here */
2648 if (!cpuhp_tasks_frozen)
2653 static int mce_cpu_online(unsigned int cpu)
2655 struct timer_list *t = this_cpu_ptr(&mce_timer);
2658 mce_device_create(cpu);
2660 ret = mce_threshold_create_device(cpu);
2662 mce_device_remove(cpu);
2670 static int mce_cpu_pre_down(unsigned int cpu)
2672 struct timer_list *t = this_cpu_ptr(&mce_timer);
2676 mce_threshold_remove_device(cpu);
2677 mce_device_remove(cpu);
2681 static __init void mce_init_banks(void)
2685 for (i = 0; i < MAX_NR_BANKS; i++) {
2686 struct mce_bank_dev *b = &mce_bank_devs[i];
2687 struct device_attribute *a = &b->attr;
2691 sysfs_attr_init(&a->attr);
2692 a->attr.name = b->attrname;
2693 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2695 a->attr.mode = 0644;
2696 a->show = show_bank;
2697 a->store = set_bank;
2702 * When running on XEN, this initcall is ordered against the XEN mcelog
2705 * device_initcall(xen_late_init_mcelog);
2706 * device_initcall_sync(mcheck_init_device);
2708 static __init int mcheck_init_device(void)
2713 * Check if we have a spare virtual bit. This will only become
2714 * a problem if/when we move beyond 5-level page tables.
2716 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2718 if (!mce_available(&boot_cpu_data)) {
2723 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2730 err = subsys_system_register(&mce_subsys, NULL);
2734 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2740 * Invokes mce_cpu_online() on all CPUs which are online when
2741 * the state is installed.
2743 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2744 mce_cpu_online, mce_cpu_pre_down);
2746 goto err_out_online;
2748 register_syscore_ops(&mce_syscore_ops);
2753 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2756 free_cpumask_var(mce_device_initialized);
2759 pr_err("Unable to init MCE device (rc: %d)\n", err);
2763 device_initcall_sync(mcheck_init_device);
2766 * Old style boot options parsing. Only for compatibility.
2768 static int __init mcheck_disable(char *str)
2770 mca_cfg.disabled = 1;
2773 __setup("nomce", mcheck_disable);
2775 #ifdef CONFIG_DEBUG_FS
2776 struct dentry *mce_get_debugfs_dir(void)
2778 static struct dentry *dmce;
2781 dmce = debugfs_create_dir("mce", NULL);
2786 static void mce_reset(void)
2788 atomic_set(&mce_fake_panicked, 0);
2789 atomic_set(&mce_executing, 0);
2790 atomic_set(&mce_callin, 0);
2791 atomic_set(&global_nwo, 0);
2792 cpumask_setall(&mce_missing_cpus);
2795 static int fake_panic_get(void *data, u64 *val)
2801 static int fake_panic_set(void *data, u64 val)
2808 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2811 static void __init mcheck_debugfs_init(void)
2813 struct dentry *dmce;
2815 dmce = mce_get_debugfs_dir();
2816 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2820 static void __init mcheck_debugfs_init(void) { }
2823 static int __init mcheck_late_init(void)
2825 if (mca_cfg.recovery)
2826 enable_copy_mc_fragile();
2828 mcheck_debugfs_init();
2831 * Flush out everything that has been logged during early boot, now that
2832 * everything has been initialized (workqueues, decoders, ...).
2834 mce_schedule_work();
2838 late_initcall(mcheck_late_init);