1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 u64 ctl; /* subevents to enable */
72 bool init; /* initialise bank? */
74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
77 /* One object for each MCE bank, shared by all CPUs */
79 struct device_attribute attr; /* device attribute */
80 char attrname[ATTR_LEN]; /* attribute name */
81 u8 bank; /* bank number */
83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
85 struct mce_vendor_flags mce_flags __read_mostly;
87 struct mca_config mca_cfg __read_mostly = {
91 * 0: always panic on uncorrected errors, log corrected errors
92 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
93 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
94 * 3: never panic or SIGBUS, log all errors (for testing only)
100 static DEFINE_PER_CPU(struct mce, mces_seen);
101 static unsigned long mce_need_notify;
102 static int cpu_missing;
105 * MCA banks polled by the period polling timer for corrected events.
106 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 * MCA banks controlled through firmware first for corrected errors.
114 * This is a global list of banks for which we won't enable CMCI and we
115 * won't poll. Firmware controls these banks and is responsible for
116 * reporting corrected errors through GHES. Uncorrected/recoverable
117 * errors are still notified through a machine check.
119 mce_banks_t mce_banks_ce_disabled;
121 static struct work_struct mce_work;
122 static struct irq_work mce_irq_work;
124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
127 * CPU/chipset specific EDAC code can register a notifier call here to print
128 * MCE errors in a human-readable form.
130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
132 /* Do initial initialization of a struct mce */
133 noinstr void mce_setup(struct mce *m)
135 memset(m, 0, sizeof(struct mce));
136 m->cpu = m->extcpu = smp_processor_id();
137 /* need the internal __ version to avoid deadlocks */
138 m->time = __ktime_get_real_seconds();
139 m->cpuvendor = boot_cpu_data.x86_vendor;
140 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 m->apicid = cpu_data(m->extcpu).initial_apicid;
143 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
145 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
146 m->ppin = __rdmsr(MSR_PPIN);
147 else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
148 m->ppin = __rdmsr(MSR_AMD_PPIN);
150 m->microcode = boot_cpu_data.microcode;
153 DEFINE_PER_CPU(struct mce, injectm);
154 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
156 void mce_log(struct mce *m)
158 if (!mce_gen_pool_add(m))
159 irq_work_queue(&mce_irq_work);
161 EXPORT_SYMBOL_GPL(mce_log);
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
166 nb->priority > MCE_PRIO_HIGHEST))
169 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
171 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
173 void mce_unregister_decode_chain(struct notifier_block *nb)
175 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
177 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
179 static inline u32 ctl_reg(int bank)
181 return MSR_IA32_MCx_CTL(bank);
184 static inline u32 status_reg(int bank)
186 return MSR_IA32_MCx_STATUS(bank);
189 static inline u32 addr_reg(int bank)
191 return MSR_IA32_MCx_ADDR(bank);
194 static inline u32 misc_reg(int bank)
196 return MSR_IA32_MCx_MISC(bank);
199 static inline u32 smca_ctl_reg(int bank)
201 return MSR_AMD64_SMCA_MCx_CTL(bank);
204 static inline u32 smca_status_reg(int bank)
206 return MSR_AMD64_SMCA_MCx_STATUS(bank);
209 static inline u32 smca_addr_reg(int bank)
211 return MSR_AMD64_SMCA_MCx_ADDR(bank);
214 static inline u32 smca_misc_reg(int bank)
216 return MSR_AMD64_SMCA_MCx_MISC(bank);
219 struct mca_msr_regs msr_ops = {
221 .status = status_reg,
226 static void __print_mce(struct mce *m)
228 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
230 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
231 m->mcgstatus, m->bank, m->status);
234 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
235 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
238 if (m->cs == __KERNEL_CS)
239 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
243 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
245 pr_cont("ADDR %llx ", m->addr);
247 pr_cont("MISC %llx ", m->misc);
249 pr_cont("PPIN %llx ", m->ppin);
251 if (mce_flags.smca) {
253 pr_cont("SYND %llx ", m->synd);
255 pr_cont("IPID %llx ", m->ipid);
261 * Note this output is parsed by external tools and old fields
262 * should not be changed.
264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
269 static void print_mce(struct mce *m)
273 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
277 #define PANIC_TIMEOUT 5 /* 5 seconds */
279 static atomic_t mce_panicked;
281 static int fake_panic;
282 static atomic_t mce_fake_panicked;
284 /* Panic in progress. Enable interrupts and wait for final IPI */
285 static void wait_for_panic(void)
287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
291 while (timeout-- > 0)
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
295 panic("Panicing machine check CPU died");
298 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
300 struct llist_node *pending;
301 struct mce_evt_llist *l;
305 * Allow instrumentation around external facilities usage. Not that it
306 * matters a whole lot since the machine is going to panic anyway.
308 instrumentation_begin();
312 * Make sure only one CPU runs in machine check panic
314 if (atomic_inc_return(&mce_panicked) > 1)
321 /* Don't log too much for fake panic */
322 if (atomic_inc_return(&mce_fake_panicked) > 1)
325 pending = mce_gen_pool_prepare_records();
326 /* First print corrected ones that are still unlogged */
327 llist_for_each_entry(l, pending, llnode) {
328 struct mce *m = &l->mce;
329 if (!(m->status & MCI_STATUS_UC)) {
332 apei_err = apei_write_mce(m);
335 /* Now print uncorrected but with the final one last */
336 llist_for_each_entry(l, pending, llnode) {
337 struct mce *m = &l->mce;
338 if (!(m->status & MCI_STATUS_UC))
340 if (!final || mce_cmp(m, final)) {
343 apei_err = apei_write_mce(m);
349 apei_err = apei_write_mce(final);
352 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
354 pr_emerg(HW_ERR "Machine check: %s\n", exp);
356 if (panic_timeout == 0)
357 panic_timeout = mca_cfg.panic_timeout;
360 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
363 instrumentation_end();
366 /* Support code for software error injection */
368 static int msr_to_offset(u32 msr)
370 unsigned bank = __this_cpu_read(injectm.bank);
372 if (msr == mca_cfg.rip_msr)
373 return offsetof(struct mce, ip);
374 if (msr == msr_ops.status(bank))
375 return offsetof(struct mce, status);
376 if (msr == msr_ops.addr(bank))
377 return offsetof(struct mce, addr);
378 if (msr == msr_ops.misc(bank))
379 return offsetof(struct mce, misc);
380 if (msr == MSR_IA32_MCG_STATUS)
381 return offsetof(struct mce, mcgstatus);
385 void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
388 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
389 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
390 regs->ip, (void *)regs->ip);
392 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
393 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
396 show_stack_regs(regs);
398 panic("MCA architectural violation!\n");
404 /* MSR access wrappers used for error injection */
405 static noinstr u64 mce_rdmsrl(u32 msr)
407 DECLARE_ARGS(val, low, high);
409 if (__this_cpu_read(injectm.finished)) {
413 instrumentation_begin();
415 offset = msr_to_offset(msr);
419 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
421 instrumentation_end();
427 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
428 * architectural violation and needs to be reported to hw vendor. Panic
429 * the box to not allow any further progress.
431 asm volatile("1: rdmsr\n"
433 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE)
434 : EAX_EDX_RET(val, low, high) : "c" (msr));
437 return EAX_EDX_VAL(val, low, high);
440 static noinstr void mce_wrmsrl(u32 msr, u64 v)
444 if (__this_cpu_read(injectm.finished)) {
447 instrumentation_begin();
449 offset = msr_to_offset(msr);
451 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
453 instrumentation_end();
459 high = (u32)(v >> 32);
461 /* See comment in mce_rdmsrl() */
462 asm volatile("1: wrmsr\n"
464 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE)
465 : : "c" (msr), "a"(low), "d" (high) : "memory");
469 * Collect all global (w.r.t. this processor) status about this machine
470 * check into our "mce" struct so that we can use it later to assess
471 * the severity of the problem as we read per-bank specific details.
473 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
477 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
480 * Get the address of the instruction at the time of
481 * the machine check error.
483 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
488 * When in VM86 mode make the cs look like ring 3
489 * always. This is a lie, but it's better than passing
490 * the additional vm86 bit around everywhere.
492 if (v8086_mode(regs))
495 /* Use accurate RIP reporting if available. */
497 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
501 int mce_available(struct cpuinfo_x86 *c)
503 if (mca_cfg.disabled)
505 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
508 static void mce_schedule_work(void)
510 if (!mce_gen_pool_empty())
511 schedule_work(&mce_work);
514 static void mce_irq_work_cb(struct irq_work *entry)
520 * Check if the address reported by the CPU is in a format we can parse.
521 * It would be possible to add code for most other cases, but all would
522 * be somewhat complicated (e.g. segment offset would require an instruction
523 * parser). So only support physical addresses up to page granularity for now.
525 int mce_usable_address(struct mce *m)
527 if (!(m->status & MCI_STATUS_ADDRV))
530 /* Checks after this one are Intel/Zhaoxin-specific: */
531 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
532 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
535 if (!(m->status & MCI_STATUS_MISCV))
538 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
541 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
546 EXPORT_SYMBOL_GPL(mce_usable_address);
548 bool mce_is_memory_error(struct mce *m)
550 switch (m->cpuvendor) {
552 case X86_VENDOR_HYGON:
553 return amd_mce_is_memory_error(m);
555 case X86_VENDOR_INTEL:
556 case X86_VENDOR_ZHAOXIN:
558 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
560 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
561 * indicating a memory error. Bit 8 is used for indicating a
562 * cache hierarchy error. The combination of bit 2 and bit 3
563 * is used for indicating a `generic' cache hierarchy error
564 * But we can't just blindly check the above bits, because if
565 * bit 11 is set, then it is a bus/interconnect error - and
566 * either way the above bits just gives more detail on what
567 * bus/interconnect error happened. Note that bit 12 can be
568 * ignored, as it's the "filter" bit.
570 return (m->status & 0xef80) == BIT(7) ||
571 (m->status & 0xef00) == BIT(8) ||
572 (m->status & 0xeffc) == 0xc;
578 EXPORT_SYMBOL_GPL(mce_is_memory_error);
580 static bool whole_page(struct mce *m)
582 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
585 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
588 bool mce_is_correctable(struct mce *m)
590 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
593 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
596 if (m->status & MCI_STATUS_UC)
601 EXPORT_SYMBOL_GPL(mce_is_correctable);
603 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
606 struct mce *m = (struct mce *)data;
611 /* Emit the trace record: */
614 set_bit(0, &mce_need_notify);
621 static struct notifier_block early_nb = {
622 .notifier_call = mce_early_notifier,
623 .priority = MCE_PRIO_EARLY,
626 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
629 struct mce *mce = (struct mce *)data;
632 if (!mce || !mce_usable_address(mce))
635 if (mce->severity != MCE_AO_SEVERITY &&
636 mce->severity != MCE_DEFERRED_SEVERITY)
639 pfn = mce->addr >> PAGE_SHIFT;
640 if (!memory_failure(pfn, 0)) {
641 set_mce_nospec(pfn, whole_page(mce));
642 mce->kflags |= MCE_HANDLED_UC;
648 static struct notifier_block mce_uc_nb = {
649 .notifier_call = uc_decode_notifier,
650 .priority = MCE_PRIO_UC,
653 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
656 struct mce *m = (struct mce *)data;
661 if (mca_cfg.print_all || !m->kflags)
667 static struct notifier_block mce_default_nb = {
668 .notifier_call = mce_default_notifier,
669 /* lowest prio, we want it to run last. */
670 .priority = MCE_PRIO_LOWEST,
674 * Read ADDR and MISC registers.
676 static noinstr void mce_read_aux(struct mce *m, int i)
678 if (m->status & MCI_STATUS_MISCV)
679 m->misc = mce_rdmsrl(msr_ops.misc(i));
681 if (m->status & MCI_STATUS_ADDRV) {
682 m->addr = mce_rdmsrl(msr_ops.addr(i));
685 * Mask the reported address by the reported granularity.
687 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
688 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
694 * Extract [55:<lsb>] where lsb is the least significant
695 * *valid* bit of the address bits.
697 if (mce_flags.smca) {
698 u8 lsb = (m->addr >> 56) & 0x3f;
700 m->addr &= GENMASK_ULL(55, lsb);
704 if (mce_flags.smca) {
705 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
707 if (m->status & MCI_STATUS_SYNDV)
708 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
712 DEFINE_PER_CPU(unsigned, mce_poll_count);
715 * Poll for corrected events or events that happened before reset.
716 * Those are just logged through /dev/mcelog.
718 * This is executed in standard interrupt context.
720 * Note: spec recommends to panic for fatal unsignalled
721 * errors here. However this would be quite problematic --
722 * we would need to reimplement the Monarch handling and
723 * it would mess up the exclusion between exception handler
724 * and poll handler -- * so we skip this for now.
725 * These cases should not happen anyways, or only when the CPU
726 * is already totally * confused. In this case it's likely it will
727 * not fully execute the machine check handler either.
729 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
731 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
732 bool error_seen = false;
736 this_cpu_inc(mce_poll_count);
738 mce_gather_info(&m, NULL);
740 if (flags & MCP_TIMESTAMP)
743 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
744 if (!mce_banks[i].ctl || !test_bit(i, *b))
752 m.status = mce_rdmsrl(msr_ops.status(i));
754 /* If this entry is not valid, ignore it */
755 if (!(m.status & MCI_STATUS_VAL))
759 * If we are logging everything (at CPU online) or this
760 * is a corrected error, then we must log it.
762 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
766 * Newer Intel systems that support software error
767 * recovery need to make additional checks. Other
768 * CPUs should skip over uncorrected errors, but log
772 if (m.status & MCI_STATUS_UC)
777 /* Log "not enabled" (speculative) errors */
778 if (!(m.status & MCI_STATUS_EN))
782 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
783 * UC == 1 && PCC == 0 && S == 0
785 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
789 * Skip anything else. Presumption is that our read of this
790 * bank is racing with a machine check. Leave the log alone
791 * for do_machine_check() to deal with it.
798 if (flags & MCP_DONTLOG)
802 m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false);
804 * Don't get the IP here because it's unlikely to
805 * have anything to do with the actual error location.
808 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
811 if (flags & MCP_QUEUE_LOG)
812 mce_gen_pool_add(&m);
818 * Clear state for this bank.
820 mce_wrmsrl(msr_ops.status(i), 0);
824 * Don't clear MCG_STATUS here because it's only defined for
832 EXPORT_SYMBOL_GPL(machine_check_poll);
835 * Do a quick check if any of the events requires a panic.
836 * This decides if we keep the events around or clear them.
838 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
839 struct pt_regs *regs)
844 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
845 m->status = mce_rdmsrl(msr_ops.status(i));
846 if (!(m->status & MCI_STATUS_VAL))
849 __set_bit(i, validp);
850 if (quirk_no_way_out)
851 quirk_no_way_out(i, m, regs);
854 if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
864 * Variable to establish order between CPUs while scanning.
865 * Each CPU spins initially until executing is equal its number.
867 static atomic_t mce_executing;
870 * Defines order of CPUs on entry. First CPU becomes Monarch.
872 static atomic_t mce_callin;
875 * Track which CPUs entered the MCA broadcast synchronization and which not in
876 * order to print holdouts.
878 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
881 * Check if a timeout waiting for other CPUs happened.
883 static int mce_timed_out(u64 *t, const char *msg)
886 * The others already did panic for some reason.
887 * Bail out like in a timeout.
888 * rmb() to tell the compiler that system_state
889 * might have been modified by someone else.
892 if (atomic_read(&mce_panicked))
894 if (!mca_cfg.monarch_timeout)
896 if ((s64)*t < SPINUNIT) {
897 if (mca_cfg.tolerant <= 1) {
898 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
899 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
900 cpumask_pr_args(&mce_missing_cpus));
901 mce_panic(msg, NULL, NULL);
908 touch_nmi_watchdog();
913 * The Monarch's reign. The Monarch is the CPU who entered
914 * the machine check handler first. It waits for the others to
915 * raise the exception too and then grades them. When any
916 * error is fatal panic. Only then let the others continue.
918 * The other CPUs entering the MCE handler will be controlled by the
919 * Monarch. They are called Subjects.
921 * This way we prevent any potential data corruption in a unrecoverable case
922 * and also makes sure always all CPU's errors are examined.
924 * Also this detects the case of a machine check event coming from outer
925 * space (not detected by any CPUs) In this case some external agent wants
926 * us to shut down, so panic too.
928 * The other CPUs might still decide to panic if the handler happens
929 * in a unrecoverable place, but in this case the system is in a semi-stable
930 * state and won't corrupt anything by itself. It's ok to let the others
931 * continue for a bit first.
933 * All the spin loops have timeouts; when a timeout happens a CPU
934 * typically elects itself to be Monarch.
936 static void mce_reign(void)
939 struct mce *m = NULL;
940 int global_worst = 0;
944 * This CPU is the Monarch and the other CPUs have run
945 * through their handlers.
946 * Grade the severity of the errors of all the CPUs.
948 for_each_possible_cpu(cpu) {
949 struct mce *mtmp = &per_cpu(mces_seen, cpu);
951 if (mtmp->severity > global_worst) {
952 global_worst = mtmp->severity;
953 m = &per_cpu(mces_seen, cpu);
958 * Cannot recover? Panic here then.
959 * This dumps all the mces in the log buffer and stops the
962 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
963 /* call mce_severity() to get "msg" for panic */
964 mce_severity(m, NULL, mca_cfg.tolerant, &msg, true);
965 mce_panic("Fatal machine check", m, msg);
969 * For UC somewhere we let the CPU who detects it handle it.
970 * Also must let continue the others, otherwise the handling
971 * CPU could deadlock on a lock.
975 * No machine check event found. Must be some external
976 * source or one CPU is hung. Panic.
978 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
979 mce_panic("Fatal machine check from unknown source", NULL, NULL);
982 * Now clear all the mces_seen so that they don't reappear on
985 for_each_possible_cpu(cpu)
986 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
989 static atomic_t global_nwo;
992 * Start of Monarch synchronization. This waits until all CPUs have
993 * entered the exception handler and then determines if any of them
994 * saw a fatal event that requires panic. Then it executes them
995 * in the entry order.
996 * TBD double check parallel CPU hotunplug
998 static int mce_start(int *no_way_out)
1001 int cpus = num_online_cpus();
1002 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1007 atomic_add(*no_way_out, &global_nwo);
1009 * Rely on the implied barrier below, such that global_nwo
1010 * is updated before mce_callin.
1012 order = atomic_inc_return(&mce_callin);
1013 cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1016 * Wait for everyone.
1018 while (atomic_read(&mce_callin) != cpus) {
1019 if (mce_timed_out(&timeout,
1020 "Timeout: Not all CPUs entered broadcast exception handler")) {
1021 atomic_set(&global_nwo, 0);
1028 * mce_callin should be read before global_nwo
1034 * Monarch: Starts executing now, the others wait.
1036 atomic_set(&mce_executing, 1);
1039 * Subject: Now start the scanning loop one by one in
1040 * the original callin order.
1041 * This way when there are any shared banks it will be
1042 * only seen by one CPU before cleared, avoiding duplicates.
1044 while (atomic_read(&mce_executing) < order) {
1045 if (mce_timed_out(&timeout,
1046 "Timeout: Subject CPUs unable to finish machine check processing")) {
1047 atomic_set(&global_nwo, 0);
1055 * Cache the global no_way_out state.
1057 *no_way_out = atomic_read(&global_nwo);
1063 * Synchronize between CPUs after main scanning loop.
1064 * This invokes the bulk of the Monarch processing.
1066 static noinstr int mce_end(int order)
1068 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1071 /* Allow instrumentation around external facilities. */
1072 instrumentation_begin();
1080 * Allow others to run.
1082 atomic_inc(&mce_executing);
1085 /* CHECKME: Can this race with a parallel hotplug? */
1086 int cpus = num_online_cpus();
1089 * Monarch: Wait for everyone to go through their scanning
1092 while (atomic_read(&mce_executing) <= cpus) {
1093 if (mce_timed_out(&timeout,
1094 "Timeout: Monarch CPU unable to finish machine check processing"))
1104 * Subject: Wait for Monarch to finish.
1106 while (atomic_read(&mce_executing) != 0) {
1107 if (mce_timed_out(&timeout,
1108 "Timeout: Monarch CPU did not finish machine check processing"))
1114 * Don't reset anything. That's done by the Monarch.
1121 * Reset all global state.
1124 atomic_set(&global_nwo, 0);
1125 atomic_set(&mce_callin, 0);
1126 cpumask_setall(&mce_missing_cpus);
1130 * Let others run again.
1132 atomic_set(&mce_executing, 0);
1135 instrumentation_end();
1140 static void mce_clear_state(unsigned long *toclear)
1144 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1145 if (test_bit(i, toclear))
1146 mce_wrmsrl(msr_ops.status(i), 0);
1151 * Cases where we avoid rendezvous handler timeout:
1152 * 1) If this CPU is offline.
1154 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1155 * skip those CPUs which remain looping in the 1st kernel - see
1156 * crash_nmi_callback().
1158 * Note: there still is a small window between kexec-ing and the new,
1159 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1160 * might not get handled properly.
1162 static noinstr bool mce_check_crashing_cpu(void)
1164 unsigned int cpu = smp_processor_id();
1166 if (arch_cpu_is_offline(cpu) ||
1167 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1170 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1172 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1173 if (mcgstatus & MCG_STATUS_LMCES)
1177 if (mcgstatus & MCG_STATUS_RIPV) {
1178 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1185 static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1186 unsigned long *toclear, unsigned long *valid_banks,
1187 int no_way_out, int *worst)
1189 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1190 struct mca_config *cfg = &mca_cfg;
1193 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1194 __clear_bit(i, toclear);
1195 if (!test_bit(i, valid_banks))
1198 if (!mce_banks[i].ctl)
1205 m->status = mce_rdmsrl(msr_ops.status(i));
1206 if (!(m->status & MCI_STATUS_VAL))
1210 * Corrected or non-signaled errors are handled by
1211 * machine_check_poll(). Leave them alone, unless this panics.
1213 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1217 /* Set taint even when machine check was not enabled. */
1218 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1220 severity = mce_severity(m, regs, cfg->tolerant, NULL, true);
1223 * When machine check was for corrected/deferred handler don't
1224 * touch, unless we're panicking.
1226 if ((severity == MCE_KEEP_SEVERITY ||
1227 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1230 __set_bit(i, toclear);
1232 /* Machine check event was not enabled. Clear, but ignore. */
1233 if (severity == MCE_NO_SEVERITY)
1238 /* assuming valid severity level != 0 */
1239 m->severity = severity;
1243 if (severity > *worst) {
1249 /* mce_clear_state will clear *final, save locally for use later */
1253 static void kill_me_now(struct callback_head *ch)
1255 struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
1261 static void kill_me_maybe(struct callback_head *cb)
1263 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1264 int flags = MF_ACTION_REQUIRED;
1268 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1271 flags |= MF_MUST_KILL;
1273 ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags);
1274 if (!ret && !(p->mce_kflags & MCE_IN_KERNEL_COPYIN)) {
1275 set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page);
1281 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1282 * to the current process with the proper error info,
1283 * -EOPNOTSUPP means hwpoison_filter() filtered the error event,
1285 * In both cases, no further processing is required.
1287 if (ret == -EHWPOISON || ret == -EOPNOTSUPP)
1290 if (p->mce_vaddr != (void __user *)-1l) {
1291 force_sig_mceerr(BUS_MCEERR_AR, p->mce_vaddr, PAGE_SHIFT);
1293 pr_err("Memory error not recovered");
1298 static void queue_task_work(struct mce *m, char *msg, int kill_current_task)
1300 int count = ++current->mce_count;
1302 /* First call, save all the details */
1304 current->mce_addr = m->addr;
1305 current->mce_kflags = m->kflags;
1306 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1307 current->mce_whole_page = whole_page(m);
1309 if (kill_current_task)
1310 current->mce_kill_me.func = kill_me_now;
1312 current->mce_kill_me.func = kill_me_maybe;
1315 /* Ten is likely overkill. Don't expect more than two faults before task_work() */
1317 mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
1319 /* Second or later call, make sure page address matches the one from first call */
1320 if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
1321 mce_panic("Consecutive machine checks to different user pages", m, msg);
1323 /* Do not call task_work_add() more than once */
1327 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1331 * The actual machine check handler. This only handles real
1332 * exceptions when something got corrupted coming in through int 18.
1334 * This is executed in NMI context not subject to normal locking rules. This
1335 * implies that most kernel services cannot be safely used. Don't even
1336 * think about putting a printk in there!
1338 * On Intel systems this is entered on all CPUs in parallel through
1339 * MCE broadcast. However some CPUs might be broken beyond repair,
1340 * so be always careful when synchronizing with others.
1342 * Tracing and kprobes are disabled: if we interrupted a kernel context
1343 * with IF=1, we need to minimize stack usage. There are also recursion
1344 * issues: if the machine check was due to a failure of the memory
1345 * backing the user stack, tracing that reads the user stack will cause
1346 * potentially infinite recursion.
1348 noinstr void do_machine_check(struct pt_regs *regs)
1350 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1351 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1352 struct mca_config *cfg = &mca_cfg;
1353 struct mce m, *final;
1358 * Establish sequential order between the CPUs entering the machine
1364 * If no_way_out gets set, there is no safe way to recover from this
1365 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1370 * If kill_current_task is not set, there might be a way to recover from this
1373 int kill_current_task = 0;
1376 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1381 this_cpu_inc(mce_exception_count);
1383 mce_gather_info(&m, regs);
1386 final = this_cpu_ptr(&mces_seen);
1389 memset(valid_banks, 0, sizeof(valid_banks));
1390 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1395 * When no restart IP might need to kill or panic.
1396 * Assume the worst for now, but if we find the
1397 * severity is MCE_AR_SEVERITY we have other options.
1399 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1400 kill_current_task = (cfg->tolerant == 3) ? 0 : 1;
1402 * Check if this MCE is signaled to only this logical processor,
1403 * on Intel, Zhaoxin only.
1405 if (m.cpuvendor == X86_VENDOR_INTEL ||
1406 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1407 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1410 * Local machine check may already know that we have to panic.
1411 * Broadcast machine check begins rendezvous in mce_start()
1412 * Go through all banks in exclusion of the other CPUs. This way we
1413 * don't report duplicated events on shared banks because the first one
1414 * to see it will clear it.
1417 if (no_way_out && cfg->tolerant < 3)
1418 mce_panic("Fatal local machine check", &m, msg);
1420 order = mce_start(&no_way_out);
1423 __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1426 mce_clear_state(toclear);
1429 * Do most of the synchronization with other CPUs.
1430 * When there's any problem use only local no_way_out state.
1433 if (mce_end(order) < 0) {
1435 no_way_out = worst >= MCE_PANIC_SEVERITY;
1437 if (no_way_out && cfg->tolerant < 3)
1438 mce_panic("Fatal machine check on current CPU", &m, msg);
1442 * If there was a fatal machine check we should have
1443 * already called mce_panic earlier in this function.
1444 * Since we re-read the banks, we might have found
1445 * something new. Check again to see if we found a
1446 * fatal error. We call "mce_severity()" again to
1447 * make sure we have the right "msg".
1449 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1450 mce_severity(&m, regs, cfg->tolerant, &msg, true);
1451 mce_panic("Local fatal machine check!", &m, msg);
1455 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1459 * Enable instrumentation around the external facilities like
1460 * task_work_add() (via queue_task_work()), fixup_exception() etc.
1461 * For now, that is. Fixing this properly would need a lot more involved
1464 instrumentation_begin();
1466 /* Fault was in user mode and we need to take some action */
1467 if ((m.cs & 3) == 3) {
1468 /* If this triggers there is no way to recover. Die hard. */
1469 BUG_ON(!on_thread_stack() || !user_mode(regs));
1471 queue_task_work(&m, msg, kill_current_task);
1475 * Handle an MCE which has happened in kernel space but from
1476 * which the kernel can recover: ex_has_fault_handler() has
1477 * already verified that the rIP at which the error happened is
1478 * a rIP from which the kernel can recover (by jumping to
1479 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1480 * corresponding exception handler which would do that is the
1483 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1484 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1485 mce_panic("Failed kernel mode recovery", &m, msg);
1488 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1489 queue_task_work(&m, msg, kill_current_task);
1492 instrumentation_end();
1495 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1497 EXPORT_SYMBOL_GPL(do_machine_check);
1499 #ifndef CONFIG_MEMORY_FAILURE
1500 int memory_failure(unsigned long pfn, int flags)
1502 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1503 BUG_ON(flags & MF_ACTION_REQUIRED);
1504 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1505 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1513 * Periodic polling timer for "silent" machine check errors. If the
1514 * poller finds an MCE, poll 2x faster. When the poller finds no more
1515 * errors, poll 2x slower (up to check_interval seconds).
1517 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1519 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1520 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1522 static unsigned long mce_adjust_timer_default(unsigned long interval)
1527 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1529 static void __start_timer(struct timer_list *t, unsigned long interval)
1531 unsigned long when = jiffies + interval;
1532 unsigned long flags;
1534 local_irq_save(flags);
1536 if (!timer_pending(t) || time_before(when, t->expires))
1537 mod_timer(t, round_jiffies(when));
1539 local_irq_restore(flags);
1542 static void mce_timer_fn(struct timer_list *t)
1544 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1547 WARN_ON(cpu_t != t);
1549 iv = __this_cpu_read(mce_next_interval);
1551 if (mce_available(this_cpu_ptr(&cpu_info))) {
1552 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1554 if (mce_intel_cmci_poll()) {
1555 iv = mce_adjust_timer(iv);
1561 * Alert userspace if needed. If we logged an MCE, reduce the polling
1562 * interval, otherwise increase the polling interval.
1564 if (mce_notify_irq())
1565 iv = max(iv / 2, (unsigned long) HZ/100);
1567 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1570 __this_cpu_write(mce_next_interval, iv);
1571 __start_timer(t, iv);
1575 * Ensure that the timer is firing in @interval from now.
1577 void mce_timer_kick(unsigned long interval)
1579 struct timer_list *t = this_cpu_ptr(&mce_timer);
1580 unsigned long iv = __this_cpu_read(mce_next_interval);
1582 __start_timer(t, interval);
1585 __this_cpu_write(mce_next_interval, interval);
1588 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1589 static void mce_timer_delete_all(void)
1593 for_each_online_cpu(cpu)
1594 del_timer_sync(&per_cpu(mce_timer, cpu));
1598 * Notify the user(s) about new machine check events.
1599 * Can be called from interrupt context, but not from machine check/NMI
1602 int mce_notify_irq(void)
1604 /* Not more than two messages every minute */
1605 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1607 if (test_and_clear_bit(0, &mce_need_notify)) {
1610 if (__ratelimit(&ratelimit))
1611 pr_info(HW_ERR "Machine check events logged\n");
1617 EXPORT_SYMBOL_GPL(mce_notify_irq);
1619 static void __mcheck_cpu_mce_banks_init(void)
1621 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1622 u8 n_banks = this_cpu_read(mce_num_banks);
1625 for (i = 0; i < n_banks; i++) {
1626 struct mce_bank *b = &mce_banks[i];
1629 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1630 * the required vendor quirks before
1631 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1639 * Initialize Machine Checks for a CPU.
1641 static void __mcheck_cpu_cap_init(void)
1646 rdmsrl(MSR_IA32_MCG_CAP, cap);
1648 b = cap & MCG_BANKCNT_MASK;
1650 if (b > MAX_NR_BANKS) {
1651 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1652 smp_processor_id(), MAX_NR_BANKS, b);
1656 this_cpu_write(mce_num_banks, b);
1658 __mcheck_cpu_mce_banks_init();
1660 /* Use accurate RIP reporting if available. */
1661 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1662 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1664 if (cap & MCG_SER_P)
1668 static void __mcheck_cpu_init_generic(void)
1670 enum mcp_flags m_fl = 0;
1671 mce_banks_t all_banks;
1674 if (!mca_cfg.bootlog)
1678 * Log the machine checks left over from the previous reset. Log them
1679 * only, do not start processing them. That will happen in mcheck_late_init()
1680 * when all consumers have been registered on the notifier chain.
1682 bitmap_fill(all_banks, MAX_NR_BANKS);
1683 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1685 cr4_set_bits(X86_CR4_MCE);
1687 rdmsrl(MSR_IA32_MCG_CAP, cap);
1688 if (cap & MCG_CTL_P)
1689 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1692 static void __mcheck_cpu_init_clear_banks(void)
1694 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1697 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1698 struct mce_bank *b = &mce_banks[i];
1702 wrmsrl(msr_ops.ctl(i), b->ctl);
1703 wrmsrl(msr_ops.status(i), 0);
1708 * Do a final check to see if there are any unused/RAZ banks.
1710 * This must be done after the banks have been initialized and any quirks have
1713 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1714 * Otherwise, a user who disables a bank will not be able to re-enable it
1715 * without a system reboot.
1717 static void __mcheck_cpu_check_banks(void)
1719 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1723 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1724 struct mce_bank *b = &mce_banks[i];
1729 rdmsrl(msr_ops.ctl(i), msrval);
1735 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1736 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1737 * Vol 3B Table 15-20). But this confuses both the code that determines
1738 * whether the machine check occurred in kernel or user mode, and also
1739 * the severity assessment code. Pretend that EIPV was set, and take the
1740 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1742 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1746 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1748 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1749 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1750 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1752 (MCI_STATUS_UC|MCI_STATUS_EN|
1753 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1754 MCI_STATUS_AR|MCACOD_INSTR))
1757 m->mcgstatus |= MCG_STATUS_EIPV;
1762 /* Add per CPU specific workarounds here */
1763 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1765 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1766 struct mca_config *cfg = &mca_cfg;
1768 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1769 pr_info("unknown CPU type - not enabling MCE support\n");
1773 /* This should be disabled by the BIOS, but isn't always */
1774 if (c->x86_vendor == X86_VENDOR_AMD) {
1775 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1777 * disable GART TBL walk error reporting, which
1778 * trips off incorrectly with the IOMMU & 3ware
1781 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1783 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1785 * Lots of broken BIOS around that don't clear them
1786 * by default and leave crap in there. Don't log:
1791 * Various K7s with broken bank 0 around. Always disable
1794 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1795 mce_banks[0].ctl = 0;
1798 * overflow_recov is supported for F15h Models 00h-0fh
1799 * even though we don't have a CPUID bit for it.
1801 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1802 mce_flags.overflow_recov = 1;
1806 if (c->x86_vendor == X86_VENDOR_INTEL) {
1808 * SDM documents that on family 6 bank 0 should not be written
1809 * because it aliases to another special BIOS controlled
1811 * But it's not aliased anymore on model 0x1a+
1812 * Don't ignore bank 0 completely because there could be a
1813 * valid event later, merely don't write CTL0.
1816 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1817 mce_banks[0].init = false;
1820 * All newer Intel systems support MCE broadcasting. Enable
1821 * synchronization with a one second timeout.
1823 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1824 cfg->monarch_timeout < 0)
1825 cfg->monarch_timeout = USEC_PER_SEC;
1828 * There are also broken BIOSes on some Pentium M and
1831 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1834 if (c->x86 == 6 && c->x86_model == 45)
1835 quirk_no_way_out = quirk_sandybridge_ifu;
1838 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1840 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1841 * synchronization with a one second timeout.
1843 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1844 if (cfg->monarch_timeout < 0)
1845 cfg->monarch_timeout = USEC_PER_SEC;
1849 if (cfg->monarch_timeout < 0)
1850 cfg->monarch_timeout = 0;
1851 if (cfg->bootlog != 0)
1852 cfg->panic_timeout = 30;
1857 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1862 switch (c->x86_vendor) {
1863 case X86_VENDOR_INTEL:
1864 intel_p5_mcheck_init(c);
1866 case X86_VENDOR_CENTAUR:
1867 winchip_mcheck_init(c);
1877 * Init basic CPU features needed for early decoding of MCEs.
1879 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1881 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1882 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1883 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1884 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1885 mce_flags.amd_threshold = 1;
1887 if (mce_flags.smca) {
1888 msr_ops.ctl = smca_ctl_reg;
1889 msr_ops.status = smca_status_reg;
1890 msr_ops.addr = smca_addr_reg;
1891 msr_ops.misc = smca_misc_reg;
1896 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1898 struct mca_config *cfg = &mca_cfg;
1901 * All newer Centaur CPUs support MCE broadcasting. Enable
1902 * synchronization with a one second timeout.
1904 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1906 if (cfg->monarch_timeout < 0)
1907 cfg->monarch_timeout = USEC_PER_SEC;
1911 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1913 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1916 * These CPUs have MCA bank 8 which reports only one error type called
1917 * SVAD (System View Address Decoder). The reporting of that error is
1918 * controlled by IA32_MC8.CTL.0.
1920 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1921 * virtual machines start and result in a system panic. Always disable
1922 * bank 8 SVAD error by default.
1924 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1925 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1926 if (this_cpu_read(mce_num_banks) > 8)
1927 mce_banks[8].ctl = 0;
1932 mce_adjust_timer = cmci_intel_adjust_timer;
1935 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1940 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1942 switch (c->x86_vendor) {
1943 case X86_VENDOR_INTEL:
1944 mce_intel_feature_init(c);
1945 mce_adjust_timer = cmci_intel_adjust_timer;
1948 case X86_VENDOR_AMD: {
1949 mce_amd_feature_init(c);
1953 case X86_VENDOR_HYGON:
1954 mce_hygon_feature_init(c);
1957 case X86_VENDOR_CENTAUR:
1958 mce_centaur_feature_init(c);
1961 case X86_VENDOR_ZHAOXIN:
1962 mce_zhaoxin_feature_init(c);
1970 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1972 switch (c->x86_vendor) {
1973 case X86_VENDOR_INTEL:
1974 mce_intel_feature_clear(c);
1977 case X86_VENDOR_ZHAOXIN:
1978 mce_zhaoxin_feature_clear(c);
1986 static void mce_start_timer(struct timer_list *t)
1988 unsigned long iv = check_interval * HZ;
1990 if (mca_cfg.ignore_ce || !iv)
1993 this_cpu_write(mce_next_interval, iv);
1994 __start_timer(t, iv);
1997 static void __mcheck_cpu_setup_timer(void)
1999 struct timer_list *t = this_cpu_ptr(&mce_timer);
2001 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2004 static void __mcheck_cpu_init_timer(void)
2006 struct timer_list *t = this_cpu_ptr(&mce_timer);
2008 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2012 bool filter_mce(struct mce *m)
2014 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2015 return amd_filter_mce(m);
2016 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2017 return intel_filter_mce(m);
2022 /* Handle unconfigured int18 (should never happen) */
2023 static noinstr void unexpected_machine_check(struct pt_regs *regs)
2025 instrumentation_begin();
2026 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
2027 smp_processor_id());
2028 instrumentation_end();
2031 /* Call the installed machine check handler for this CPU setup. */
2032 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
2034 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2036 irqentry_state_t irq_state;
2038 WARN_ON_ONCE(user_mode(regs));
2041 * Only required when from kernel mode. See
2042 * mce_check_crashing_cpu() for details.
2044 if (machine_check_vector == do_machine_check &&
2045 mce_check_crashing_cpu())
2048 irq_state = irqentry_nmi_enter(regs);
2050 * The call targets are marked noinstr, but objtool can't figure
2051 * that out because it's an indirect call. Annotate it.
2053 instrumentation_begin();
2055 machine_check_vector(regs);
2057 instrumentation_end();
2058 irqentry_nmi_exit(regs, irq_state);
2061 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2063 irqentry_enter_from_user_mode(regs);
2064 instrumentation_begin();
2066 machine_check_vector(regs);
2068 instrumentation_end();
2069 irqentry_exit_to_user_mode(regs);
2072 #ifdef CONFIG_X86_64
2073 /* MCE hit kernel mode */
2074 DEFINE_IDTENTRY_MCE(exc_machine_check)
2078 dr7 = local_db_save();
2079 exc_machine_check_kernel(regs);
2080 local_db_restore(dr7);
2083 /* The user mode variant. */
2084 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2088 dr7 = local_db_save();
2089 exc_machine_check_user(regs);
2090 local_db_restore(dr7);
2093 /* 32bit unified entry point */
2094 DEFINE_IDTENTRY_RAW(exc_machine_check)
2098 dr7 = local_db_save();
2099 if (user_mode(regs))
2100 exc_machine_check_user(regs);
2102 exc_machine_check_kernel(regs);
2103 local_db_restore(dr7);
2108 * Called for each booted CPU to set up machine checks.
2109 * Must be called with preempt off:
2111 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2113 if (mca_cfg.disabled)
2116 if (__mcheck_cpu_ancient_init(c))
2119 if (!mce_available(c))
2122 __mcheck_cpu_cap_init();
2124 if (__mcheck_cpu_apply_quirks(c) < 0) {
2125 mca_cfg.disabled = 1;
2129 if (mce_gen_pool_init()) {
2130 mca_cfg.disabled = 1;
2131 pr_emerg("Couldn't allocate MCE records pool!\n");
2135 machine_check_vector = do_machine_check;
2137 __mcheck_cpu_init_early(c);
2138 __mcheck_cpu_init_generic();
2139 __mcheck_cpu_init_vendor(c);
2140 __mcheck_cpu_init_clear_banks();
2141 __mcheck_cpu_check_banks();
2142 __mcheck_cpu_setup_timer();
2146 * Called for each booted CPU to clear some machine checks opt-ins
2148 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2150 if (mca_cfg.disabled)
2153 if (!mce_available(c))
2157 * Possibly to clear general settings generic to x86
2158 * __mcheck_cpu_clear_generic(c);
2160 __mcheck_cpu_clear_vendor(c);
2164 static void __mce_disable_bank(void *arg)
2166 int bank = *((int *)arg);
2167 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2168 cmci_disable_bank(bank);
2171 void mce_disable_bank(int bank)
2173 if (bank >= this_cpu_read(mce_num_banks)) {
2175 "Ignoring request to disable invalid MCA bank %d.\n",
2179 set_bit(bank, mce_banks_ce_disabled);
2180 on_each_cpu(__mce_disable_bank, &bank, 1);
2184 * mce=off Disables machine check
2185 * mce=no_cmci Disables CMCI
2186 * mce=no_lmce Disables LMCE
2187 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2188 * mce=print_all Print all machine check logs to console
2189 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2190 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2191 * monarchtimeout is how long to wait for other CPUs on machine
2192 * check, or 0 to not wait
2193 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2195 * mce=nobootlog Don't log MCEs from before booting.
2196 * mce=bios_cmci_threshold Don't program the CMCI threshold
2197 * mce=recovery force enable copy_mc_fragile()
2199 static int __init mcheck_enable(char *str)
2201 struct mca_config *cfg = &mca_cfg;
2209 if (!strcmp(str, "off"))
2211 else if (!strcmp(str, "no_cmci"))
2212 cfg->cmci_disabled = true;
2213 else if (!strcmp(str, "no_lmce"))
2214 cfg->lmce_disabled = 1;
2215 else if (!strcmp(str, "dont_log_ce"))
2216 cfg->dont_log_ce = true;
2217 else if (!strcmp(str, "print_all"))
2218 cfg->print_all = true;
2219 else if (!strcmp(str, "ignore_ce"))
2220 cfg->ignore_ce = true;
2221 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2222 cfg->bootlog = (str[0] == 'b');
2223 else if (!strcmp(str, "bios_cmci_threshold"))
2224 cfg->bios_cmci_threshold = 1;
2225 else if (!strcmp(str, "recovery"))
2227 else if (isdigit(str[0])) {
2228 if (get_option(&str, &cfg->tolerant) == 2)
2229 get_option(&str, &(cfg->monarch_timeout));
2231 pr_info("mce argument %s ignored. Please use /sys\n", str);
2236 __setup("mce", mcheck_enable);
2238 int __init mcheck_init(void)
2240 mce_register_decode_chain(&early_nb);
2241 mce_register_decode_chain(&mce_uc_nb);
2242 mce_register_decode_chain(&mce_default_nb);
2243 mcheck_vendor_init_severity();
2245 INIT_WORK(&mce_work, mce_gen_pool_process);
2246 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2252 * mce_syscore: PM support
2256 * Disable machine checks on suspend and shutdown. We can't really handle
2259 static void mce_disable_error_reporting(void)
2261 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2264 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2265 struct mce_bank *b = &mce_banks[i];
2268 wrmsrl(msr_ops.ctl(i), 0);
2273 static void vendor_disable_error_reporting(void)
2276 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2277 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2278 * is bad, since it will inhibit reporting for all shared resources on
2279 * the socket like the last level cache (LLC), the integrated memory
2280 * controller (iMC), etc.
2282 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2283 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2284 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2285 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2288 mce_disable_error_reporting();
2291 static int mce_syscore_suspend(void)
2293 vendor_disable_error_reporting();
2297 static void mce_syscore_shutdown(void)
2299 vendor_disable_error_reporting();
2303 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2304 * Only one CPU is active at this time, the others get re-added later using
2307 static void mce_syscore_resume(void)
2309 __mcheck_cpu_init_generic();
2310 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2311 __mcheck_cpu_init_clear_banks();
2314 static struct syscore_ops mce_syscore_ops = {
2315 .suspend = mce_syscore_suspend,
2316 .shutdown = mce_syscore_shutdown,
2317 .resume = mce_syscore_resume,
2321 * mce_device: Sysfs support
2324 static void mce_cpu_restart(void *data)
2326 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2328 __mcheck_cpu_init_generic();
2329 __mcheck_cpu_init_clear_banks();
2330 __mcheck_cpu_init_timer();
2333 /* Reinit MCEs after user configuration changes */
2334 static void mce_restart(void)
2336 mce_timer_delete_all();
2337 on_each_cpu(mce_cpu_restart, NULL, 1);
2340 /* Toggle features for corrected errors */
2341 static void mce_disable_cmci(void *data)
2343 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2348 static void mce_enable_ce(void *all)
2350 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2355 __mcheck_cpu_init_timer();
2358 static struct bus_type mce_subsys = {
2359 .name = "machinecheck",
2360 .dev_name = "machinecheck",
2363 DEFINE_PER_CPU(struct device *, mce_device);
2365 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2367 return container_of(attr, struct mce_bank_dev, attr);
2370 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2373 u8 bank = attr_to_bank(attr)->bank;
2376 if (bank >= per_cpu(mce_num_banks, s->id))
2379 b = &per_cpu(mce_banks_array, s->id)[bank];
2384 return sprintf(buf, "%llx\n", b->ctl);
2387 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2388 const char *buf, size_t size)
2390 u8 bank = attr_to_bank(attr)->bank;
2394 if (kstrtou64(buf, 0, &new) < 0)
2397 if (bank >= per_cpu(mce_num_banks, s->id))
2400 b = &per_cpu(mce_banks_array, s->id)[bank];
2411 static ssize_t set_ignore_ce(struct device *s,
2412 struct device_attribute *attr,
2413 const char *buf, size_t size)
2417 if (kstrtou64(buf, 0, &new) < 0)
2420 mutex_lock(&mce_sysfs_mutex);
2421 if (mca_cfg.ignore_ce ^ !!new) {
2423 /* disable ce features */
2424 mce_timer_delete_all();
2425 on_each_cpu(mce_disable_cmci, NULL, 1);
2426 mca_cfg.ignore_ce = true;
2428 /* enable ce features */
2429 mca_cfg.ignore_ce = false;
2430 on_each_cpu(mce_enable_ce, (void *)1, 1);
2433 mutex_unlock(&mce_sysfs_mutex);
2438 static ssize_t set_cmci_disabled(struct device *s,
2439 struct device_attribute *attr,
2440 const char *buf, size_t size)
2444 if (kstrtou64(buf, 0, &new) < 0)
2447 mutex_lock(&mce_sysfs_mutex);
2448 if (mca_cfg.cmci_disabled ^ !!new) {
2451 on_each_cpu(mce_disable_cmci, NULL, 1);
2452 mca_cfg.cmci_disabled = true;
2455 mca_cfg.cmci_disabled = false;
2456 on_each_cpu(mce_enable_ce, NULL, 1);
2459 mutex_unlock(&mce_sysfs_mutex);
2464 static ssize_t store_int_with_restart(struct device *s,
2465 struct device_attribute *attr,
2466 const char *buf, size_t size)
2468 unsigned long old_check_interval = check_interval;
2469 ssize_t ret = device_store_ulong(s, attr, buf, size);
2471 if (check_interval == old_check_interval)
2474 mutex_lock(&mce_sysfs_mutex);
2476 mutex_unlock(&mce_sysfs_mutex);
2481 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2482 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2483 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2484 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2486 static struct dev_ext_attribute dev_attr_check_interval = {
2487 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2491 static struct dev_ext_attribute dev_attr_ignore_ce = {
2492 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2496 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2497 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2498 &mca_cfg.cmci_disabled
2501 static struct device_attribute *mce_device_attrs[] = {
2502 &dev_attr_tolerant.attr,
2503 &dev_attr_check_interval.attr,
2504 #ifdef CONFIG_X86_MCELOG_LEGACY
2507 &dev_attr_monarch_timeout.attr,
2508 &dev_attr_dont_log_ce.attr,
2509 &dev_attr_print_all.attr,
2510 &dev_attr_ignore_ce.attr,
2511 &dev_attr_cmci_disabled.attr,
2515 static cpumask_var_t mce_device_initialized;
2517 static void mce_device_release(struct device *dev)
2522 /* Per CPU device init. All of the CPUs still share the same bank device: */
2523 static int mce_device_create(unsigned int cpu)
2529 if (!mce_available(&boot_cpu_data))
2532 dev = per_cpu(mce_device, cpu);
2536 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2540 dev->bus = &mce_subsys;
2541 dev->release = &mce_device_release;
2543 err = device_register(dev);
2549 for (i = 0; mce_device_attrs[i]; i++) {
2550 err = device_create_file(dev, mce_device_attrs[i]);
2554 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2555 err = device_create_file(dev, &mce_bank_devs[j].attr);
2559 cpumask_set_cpu(cpu, mce_device_initialized);
2560 per_cpu(mce_device, cpu) = dev;
2565 device_remove_file(dev, &mce_bank_devs[j].attr);
2568 device_remove_file(dev, mce_device_attrs[i]);
2570 device_unregister(dev);
2575 static void mce_device_remove(unsigned int cpu)
2577 struct device *dev = per_cpu(mce_device, cpu);
2580 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2583 for (i = 0; mce_device_attrs[i]; i++)
2584 device_remove_file(dev, mce_device_attrs[i]);
2586 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2587 device_remove_file(dev, &mce_bank_devs[i].attr);
2589 device_unregister(dev);
2590 cpumask_clear_cpu(cpu, mce_device_initialized);
2591 per_cpu(mce_device, cpu) = NULL;
2594 /* Make sure there are no machine checks on offlined CPUs. */
2595 static void mce_disable_cpu(void)
2597 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2600 if (!cpuhp_tasks_frozen)
2603 vendor_disable_error_reporting();
2606 static void mce_reenable_cpu(void)
2608 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2611 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2614 if (!cpuhp_tasks_frozen)
2616 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2617 struct mce_bank *b = &mce_banks[i];
2620 wrmsrl(msr_ops.ctl(i), b->ctl);
2624 static int mce_cpu_dead(unsigned int cpu)
2626 mce_intel_hcpu_update(cpu);
2628 /* intentionally ignoring frozen here */
2629 if (!cpuhp_tasks_frozen)
2634 static int mce_cpu_online(unsigned int cpu)
2636 struct timer_list *t = this_cpu_ptr(&mce_timer);
2639 mce_device_create(cpu);
2641 ret = mce_threshold_create_device(cpu);
2643 mce_device_remove(cpu);
2651 static int mce_cpu_pre_down(unsigned int cpu)
2653 struct timer_list *t = this_cpu_ptr(&mce_timer);
2657 mce_threshold_remove_device(cpu);
2658 mce_device_remove(cpu);
2662 static __init void mce_init_banks(void)
2666 for (i = 0; i < MAX_NR_BANKS; i++) {
2667 struct mce_bank_dev *b = &mce_bank_devs[i];
2668 struct device_attribute *a = &b->attr;
2672 sysfs_attr_init(&a->attr);
2673 a->attr.name = b->attrname;
2674 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2676 a->attr.mode = 0644;
2677 a->show = show_bank;
2678 a->store = set_bank;
2683 * When running on XEN, this initcall is ordered against the XEN mcelog
2686 * device_initcall(xen_late_init_mcelog);
2687 * device_initcall_sync(mcheck_init_device);
2689 static __init int mcheck_init_device(void)
2694 * Check if we have a spare virtual bit. This will only become
2695 * a problem if/when we move beyond 5-level page tables.
2697 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2699 if (!mce_available(&boot_cpu_data)) {
2704 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2711 err = subsys_system_register(&mce_subsys, NULL);
2715 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2721 * Invokes mce_cpu_online() on all CPUs which are online when
2722 * the state is installed.
2724 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2725 mce_cpu_online, mce_cpu_pre_down);
2727 goto err_out_online;
2729 register_syscore_ops(&mce_syscore_ops);
2734 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2737 free_cpumask_var(mce_device_initialized);
2740 pr_err("Unable to init MCE device (rc: %d)\n", err);
2744 device_initcall_sync(mcheck_init_device);
2747 * Old style boot options parsing. Only for compatibility.
2749 static int __init mcheck_disable(char *str)
2751 mca_cfg.disabled = 1;
2754 __setup("nomce", mcheck_disable);
2756 #ifdef CONFIG_DEBUG_FS
2757 struct dentry *mce_get_debugfs_dir(void)
2759 static struct dentry *dmce;
2762 dmce = debugfs_create_dir("mce", NULL);
2767 static void mce_reset(void)
2770 atomic_set(&mce_fake_panicked, 0);
2771 atomic_set(&mce_executing, 0);
2772 atomic_set(&mce_callin, 0);
2773 atomic_set(&global_nwo, 0);
2774 cpumask_setall(&mce_missing_cpus);
2777 static int fake_panic_get(void *data, u64 *val)
2783 static int fake_panic_set(void *data, u64 val)
2790 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2793 static void __init mcheck_debugfs_init(void)
2795 struct dentry *dmce;
2797 dmce = mce_get_debugfs_dir();
2798 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2802 static void __init mcheck_debugfs_init(void) { }
2805 static int __init mcheck_late_init(void)
2807 if (mca_cfg.recovery)
2808 enable_copy_mc_fragile();
2810 mcheck_debugfs_init();
2813 * Flush out everything that has been logged during early boot, now that
2814 * everything has been initialized (workqueues, decoders, ...).
2816 mce_schedule_work();
2820 late_initcall(mcheck_late_init);