1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
24 #include <linux/topology.h>
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
40 static int __init forcempx_setup(char *__unused)
46 __setup("intel-skd-046-workaround=disable", forcempx_setup);
48 void check_mpx_erratum(struct cpuinfo_x86 *c)
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
70 * Processors which have self-snooping capability can handle conflicting
71 * memory type across CPUs by snooping its own cache. However, there exists
72 * CPU models in which having conflicting memory types still leads to
73 * unpredictable behavior, machine check errors, or hangs. Clear this
74 * feature to prevent its use on machines with known erratas.
76 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
78 switch (c->x86_model) {
79 case INTEL_FAM6_CORE_YONAH:
80 case INTEL_FAM6_CORE2_MEROM:
81 case INTEL_FAM6_CORE2_MEROM_L:
82 case INTEL_FAM6_CORE2_PENRYN:
83 case INTEL_FAM6_CORE2_DUNNINGTON:
84 case INTEL_FAM6_NEHALEM:
85 case INTEL_FAM6_NEHALEM_G:
86 case INTEL_FAM6_NEHALEM_EP:
87 case INTEL_FAM6_NEHALEM_EX:
88 case INTEL_FAM6_WESTMERE:
89 case INTEL_FAM6_WESTMERE_EP:
90 case INTEL_FAM6_SANDYBRIDGE:
91 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
95 static bool ring3mwait_disabled __read_mostly;
97 static int __init ring3mwait_disable(char *__unused)
99 ring3mwait_disabled = true;
102 __setup("ring3mwait=disable", ring3mwait_disable);
104 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
107 * Ring 3 MONITOR/MWAIT feature cannot be detected without
108 * cpu model and family comparison.
112 switch (c->x86_model) {
113 case INTEL_FAM6_XEON_PHI_KNL:
114 case INTEL_FAM6_XEON_PHI_KNM:
120 if (ring3mwait_disabled)
123 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
124 this_cpu_or(msr_misc_features_shadow,
125 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
127 if (c == &boot_cpu_data)
128 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
132 * Early microcode releases for the Spectre v2 mitigation were broken.
133 * Information taken from;
134 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
135 * - https://kb.vmware.com/s/article/52345
136 * - Microcode revisions observed in the wild
137 * - Release note from 20180108 microcode release
139 struct sku_microcode {
144 static const struct sku_microcode spectre_bad_microcodes[] = {
145 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
146 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
147 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
148 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
149 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
150 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
151 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
152 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
153 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
154 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
155 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
156 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
157 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
158 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
159 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
160 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
161 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
162 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
163 /* Observed in the wild */
164 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
165 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
168 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
173 * We know that the hypervisor lie to us on the microcode version so
174 * we may as well hope that it is running the correct version.
176 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
182 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
183 if (c->x86_model == spectre_bad_microcodes[i].model &&
184 c->x86_stepping == spectre_bad_microcodes[i].stepping)
185 return (c->microcode <= spectre_bad_microcodes[i].microcode);
190 static void early_init_intel(struct cpuinfo_x86 *c)
194 /* Unmask CPUID levels if masked: */
195 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
196 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
197 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
198 c->cpuid_level = cpuid_eax(0);
203 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
204 (c->x86 == 0x6 && c->x86_model >= 0x0e))
205 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
207 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
208 c->microcode = intel_get_microcode_revision();
210 /* Now if any of them are set, check the blacklist and clear the lot */
211 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
212 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
213 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
214 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
215 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
216 setup_clear_cpu_cap(X86_FEATURE_IBRS);
217 setup_clear_cpu_cap(X86_FEATURE_IBPB);
218 setup_clear_cpu_cap(X86_FEATURE_STIBP);
219 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
220 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
221 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
222 setup_clear_cpu_cap(X86_FEATURE_SSBD);
223 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
227 * Atom erratum AAE44/AAF40/AAG38/AAH41:
229 * A race condition between speculative fetches and invalidating
230 * a large page. This is worked around in microcode, but we
231 * need the microcode to have already been loaded... so if it is
232 * not, recommend a BIOS update and disable large pages.
234 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
235 c->microcode < 0x20e) {
236 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
237 clear_cpu_cap(c, X86_FEATURE_PSE);
241 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
243 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
244 if (c->x86 == 15 && c->x86_cache_alignment == 64)
245 c->x86_cache_alignment = 128;
248 /* CPUID workaround for 0F33/0F34 CPU */
249 if (c->x86 == 0xF && c->x86_model == 0x3
250 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
251 c->x86_phys_bits = 36;
254 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
255 * with P/T states and does not stop in deep C-states.
257 * It is also reliable across cores and sockets. (but not across
258 * cabinets - we turn it off in that case explicitly.)
260 if (c->x86_power & (1 << 8)) {
261 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
262 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
265 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
267 switch (c->x86_model) {
268 case INTEL_FAM6_ATOM_SALTWELL_MID:
269 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
270 case INTEL_FAM6_ATOM_SILVERMONT_MID:
271 case INTEL_FAM6_ATOM_AIRMONT_NP:
272 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
280 * There is a known erratum on Pentium III and Core Solo
282 * " Page with PAT set to WC while associated MTRR is UC
283 * may consolidate to UC "
284 * Because of this erratum, it is better to stick with
285 * setting WC in MTRR rather than using PAT on these CPUs.
287 * Enable PAT WC only on P4, Core 2 or later CPUs.
289 if (c->x86 == 6 && c->x86_model < 15)
290 clear_cpu_cap(c, X86_FEATURE_PAT);
293 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
294 * clear the fast string and enhanced fast string CPU capabilities.
296 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
297 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
298 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
299 pr_info("Disabled fast string operations\n");
300 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
301 setup_clear_cpu_cap(X86_FEATURE_ERMS);
306 * Intel Quark Core DevMan_001.pdf section 6.4.11
307 * "The operating system also is required to invalidate (i.e., flush)
308 * the TLB when any changes are made to any of the page table entries.
309 * The operating system must reload CR3 to cause the TLB to be flushed"
311 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
312 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
315 if (c->x86 == 5 && c->x86_model == 9) {
316 pr_info("Disabling PGE capability bit\n");
317 setup_clear_cpu_cap(X86_FEATURE_PGE);
320 if (c->cpuid_level >= 0x00000001) {
321 u32 eax, ebx, ecx, edx;
323 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
325 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
326 * apicids which are reserved per package. Store the resulting
327 * shift value for the package management code.
329 if (edx & (1U << 28))
330 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
333 check_mpx_erratum(c);
334 check_memory_type_self_snoop_errata(c);
337 * Get the number of SMT siblings early from the extended topology
338 * leaf, if available. Otherwise try the legacy SMT detection.
340 if (detect_extended_topology_early(c) < 0)
346 * Early probe support logic for ppro memory erratum #50
348 * This is called before we do cpu ident work
351 int ppro_with_ram_bug(void)
353 /* Uses data from early_cpu_detect now */
354 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
355 boot_cpu_data.x86 == 6 &&
356 boot_cpu_data.x86_model == 1 &&
357 boot_cpu_data.x86_stepping < 8) {
358 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
364 static void intel_smp_check(struct cpuinfo_x86 *c)
366 /* calling is from identify_secondary_cpu() ? */
371 * Mask B, Pentium, but not Pentium MMX
374 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
377 * Remember we have B step Pentia with bugs
379 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
380 "with B stepping processors.\n");
385 static int __init forcepae_setup(char *__unused)
390 __setup("forcepae", forcepae_setup);
392 static void intel_workarounds(struct cpuinfo_x86 *c)
394 #ifdef CONFIG_X86_F00F_BUG
396 * All models of Pentium and Pentium with MMX technology CPUs
397 * have the F0 0F bug, which lets nonprivileged users lock up the
398 * system. Announce that the fault handler will be checking for it.
399 * The Quark is also family 5, but does not have the same bug.
401 clear_cpu_bug(c, X86_BUG_F00F);
402 if (c->x86 == 5 && c->x86_model < 9) {
403 static int f00f_workaround_enabled;
405 set_cpu_bug(c, X86_BUG_F00F);
406 if (!f00f_workaround_enabled) {
407 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
408 f00f_workaround_enabled = 1;
414 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
417 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
418 clear_cpu_cap(c, X86_FEATURE_SEP);
421 * PAE CPUID issue: many Pentium M report no PAE but may have a
422 * functionally usable PAE implementation.
423 * Forcefully enable PAE if kernel parameter "forcepae" is present.
426 pr_warn("PAE forced!\n");
427 set_cpu_cap(c, X86_FEATURE_PAE);
428 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
432 * P4 Xeon erratum 037 workaround.
433 * Hardware prefetcher may cause stale data to be loaded into the cache.
435 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
436 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
437 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
438 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
439 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
444 * See if we have a good local APIC by checking for buggy Pentia,
445 * i.e. all B steppings and the C2 stepping of P54C when using their
446 * integrated APIC (see 11AP erratum in "Pentium Processor
447 * Specification Update").
449 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
450 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
451 set_cpu_bug(c, X86_BUG_11AP);
454 #ifdef CONFIG_X86_INTEL_USERCOPY
456 * Set up the preferred alignment for movsl bulk memory moves
459 case 4: /* 486: untested */
461 case 5: /* Old Pentia: untested */
463 case 6: /* PII/PIII only like movsl with 8-byte alignment */
466 case 15: /* P4 is OK down to 8-byte alignment */
475 static void intel_workarounds(struct cpuinfo_x86 *c)
480 static void srat_detect_node(struct cpuinfo_x86 *c)
484 int cpu = smp_processor_id();
486 /* Don't do the funky fallback heuristics the AMD version employs
488 node = numa_cpu_node(cpu);
489 if (node == NUMA_NO_NODE || !node_online(node)) {
490 /* reuse the value from init_cpu_to_node() */
491 node = cpu_to_node(cpu);
493 numa_set_node(cpu, node);
497 #define MSR_IA32_TME_ACTIVATE 0x982
499 /* Helpers to access TME_ACTIVATE MSR */
500 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
501 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
503 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
504 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
506 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
508 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
509 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
511 /* Values for mktme_status (SW only construct) */
512 #define MKTME_ENABLED 0
513 #define MKTME_DISABLED 1
514 #define MKTME_UNINITIALIZED 2
515 static int mktme_status = MKTME_UNINITIALIZED;
517 static void detect_tme(struct cpuinfo_x86 *c)
519 u64 tme_activate, tme_policy, tme_crypto_algs;
520 int keyid_bits = 0, nr_keyids = 0;
521 static u64 tme_activate_cpu0 = 0;
523 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
525 if (mktme_status != MKTME_UNINITIALIZED) {
526 if (tme_activate != tme_activate_cpu0) {
528 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
529 pr_err_once("x86/tme: MKTME is not usable\n");
530 mktme_status = MKTME_DISABLED;
532 /* Proceed. We may need to exclude bits from x86_phys_bits. */
535 tme_activate_cpu0 = tme_activate;
538 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
539 pr_info_once("x86/tme: not enabled by BIOS\n");
540 mktme_status = MKTME_DISABLED;
544 if (mktme_status != MKTME_UNINITIALIZED)
545 goto detect_keyid_bits;
547 pr_info("x86/tme: enabled by BIOS\n");
549 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
550 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
551 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
553 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
554 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
555 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
557 mktme_status = MKTME_DISABLED;
560 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
561 nr_keyids = (1UL << keyid_bits) - 1;
563 pr_info_once("x86/mktme: enabled by BIOS\n");
564 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
566 pr_info_once("x86/mktme: disabled by BIOS\n");
569 if (mktme_status == MKTME_UNINITIALIZED) {
570 /* MKTME is usable */
571 mktme_status = MKTME_ENABLED;
575 * KeyID bits effectively lower the number of physical address
576 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
578 c->x86_phys_bits -= keyid_bits;
581 static void init_cpuid_fault(struct cpuinfo_x86 *c)
585 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
586 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
587 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
591 static void init_intel_misc_features(struct cpuinfo_x86 *c)
595 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
598 /* Clear all MISC features */
599 this_cpu_write(msr_misc_features_shadow, 0);
601 /* Check features and update capabilities and shadow control bits */
603 probe_xeon_phi_r3mwait(c);
605 msr = this_cpu_read(msr_misc_features_shadow);
606 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
609 static void init_intel(struct cpuinfo_x86 *c)
613 intel_workarounds(c);
616 * Detect the extended topology information if available. This
617 * will reinitialise the initial_apicid which will be used
618 * in init_intel_cacheinfo()
620 detect_extended_topology(c);
622 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
624 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
627 detect_num_cpu_cores(c);
633 init_intel_cacheinfo(c);
635 if (c->cpuid_level > 9) {
636 unsigned eax = cpuid_eax(10);
637 /* Check for version and the number of counters */
638 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
639 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
642 if (cpu_has(c, X86_FEATURE_XMM2))
643 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
645 if (boot_cpu_has(X86_FEATURE_DS)) {
648 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
650 set_cpu_cap(c, X86_FEATURE_BTS);
652 set_cpu_cap(c, X86_FEATURE_PEBS);
655 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
656 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
657 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
659 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
660 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
661 set_cpu_bug(c, X86_BUG_MONITOR);
665 c->x86_cache_alignment = c->x86_clflush_size * 2;
667 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
670 * Names for the Pentium II/Celeron processors
671 * detectable only by also checking the cache size.
672 * Dixon is NOT a Celeron.
675 unsigned int l2 = c->x86_cache_size;
678 switch (c->x86_model) {
681 p = "Celeron (Covington)";
683 p = "Mobile Pentium II (Dixon)";
688 p = "Celeron (Mendocino)";
689 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
695 p = "Celeron (Coppermine)";
700 strcpy(c->x86_model_id, p);
704 set_cpu_cap(c, X86_FEATURE_P4);
706 set_cpu_cap(c, X86_FEATURE_P3);
709 /* Work around errata */
712 init_ia32_feat_ctl(c);
714 if (cpu_has(c, X86_FEATURE_TME))
717 init_intel_misc_features(c);
719 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
721 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
726 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
729 * Intel PIII Tualatin. This comes in two flavours.
730 * One has 256kb of cache, the other 512. We have no way
731 * to determine which, so we use a boottime override
732 * for the 512kb model, and assume 256 otherwise.
734 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
738 * Intel Quark SoC X1000 contains a 4-way set associative
739 * 16K cache with a 16 byte cache line and 256 lines per tag
741 if ((c->x86 == 5) && (c->x86_model == 9))
747 #define TLB_INST_4K 0x01
748 #define TLB_INST_4M 0x02
749 #define TLB_INST_2M_4M 0x03
751 #define TLB_INST_ALL 0x05
752 #define TLB_INST_1G 0x06
754 #define TLB_DATA_4K 0x11
755 #define TLB_DATA_4M 0x12
756 #define TLB_DATA_2M_4M 0x13
757 #define TLB_DATA_4K_4M 0x14
759 #define TLB_DATA_1G 0x16
761 #define TLB_DATA0_4K 0x21
762 #define TLB_DATA0_4M 0x22
763 #define TLB_DATA0_2M_4M 0x23
766 #define STLB_4K_2M 0x42
768 static const struct _tlb_table intel_tlb_table[] = {
769 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
770 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
771 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
772 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
773 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
774 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
775 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
776 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
777 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
778 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
779 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
780 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
781 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
782 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
783 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
784 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
785 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
786 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
787 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
788 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
789 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
790 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
791 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
792 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
793 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
794 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
795 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
796 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
797 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
798 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
799 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
800 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
801 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
802 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
803 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
804 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
808 static void intel_tlb_lookup(const unsigned char desc)
814 /* look up this descriptor in the table */
815 for (k = 0; intel_tlb_table[k].descriptor != desc &&
816 intel_tlb_table[k].descriptor != 0; k++)
819 if (intel_tlb_table[k].tlb_type == 0)
822 switch (intel_tlb_table[k].tlb_type) {
824 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
825 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
826 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
827 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
830 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
831 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
832 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
833 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
834 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
835 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
836 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
837 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
838 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
839 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
840 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
841 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
844 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
845 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
846 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
847 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
848 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
849 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
852 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
853 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
856 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
857 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
860 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
861 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
862 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
863 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
867 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
868 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
872 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
873 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
876 case TLB_DATA0_2M_4M:
877 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
878 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
879 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
880 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
883 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
884 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
885 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
886 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
889 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
890 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
895 static void intel_detect_tlb(struct cpuinfo_x86 *c)
898 unsigned int regs[4];
899 unsigned char *desc = (unsigned char *)regs;
901 if (c->cpuid_level < 2)
904 /* Number of times to iterate */
905 n = cpuid_eax(2) & 0xFF;
907 for (i = 0 ; i < n ; i++) {
908 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
910 /* If bit 31 is set, this is an unknown format */
911 for (j = 0 ; j < 3 ; j++)
912 if (regs[j] & (1 << 31))
915 /* Byte 0 is level count, not a descriptor */
916 for (j = 1 ; j < 16 ; j++)
917 intel_tlb_lookup(desc[j]);
921 static const struct cpu_dev intel_cpu_dev = {
923 .c_ident = { "GenuineIntel" },
926 { .family = 4, .model_names =
928 [0] = "486 DX-25/33",
939 { .family = 5, .model_names =
941 [0] = "Pentium 60/66 A-step",
942 [1] = "Pentium 60/66",
943 [2] = "Pentium 75 - 200",
944 [3] = "OverDrive PODP5V83",
946 [7] = "Mobile Pentium 75 - 200",
947 [8] = "Mobile Pentium MMX",
948 [9] = "Quark SoC X1000",
951 { .family = 6, .model_names =
953 [0] = "Pentium Pro A-step",
955 [3] = "Pentium II (Klamath)",
956 [4] = "Pentium II (Deschutes)",
957 [5] = "Pentium II (Deschutes)",
958 [6] = "Mobile Pentium II",
959 [7] = "Pentium III (Katmai)",
960 [8] = "Pentium III (Coppermine)",
961 [10] = "Pentium III (Cascades)",
962 [11] = "Pentium III (Tualatin)",
965 { .family = 15, .model_names =
967 [0] = "Pentium 4 (Unknown)",
968 [1] = "Pentium 4 (Willamette)",
969 [2] = "Pentium 4 (Northwood)",
970 [4] = "Pentium 4 (Foster)",
971 [5] = "Pentium 4 (Foster)",
975 .legacy_cache_size = intel_size_cache,
977 .c_detect_tlb = intel_detect_tlb,
978 .c_early_init = early_init_intel,
979 .c_init = init_intel,
980 .c_x86_vendor = X86_VENDOR_INTEL,
983 cpu_dev_register(intel_cpu_dev);