1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
24 #include <linux/topology.h>
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
35 * Processors which have self-snooping capability can handle conflicting
36 * memory type across CPUs by snooping its own cache. However, there exists
37 * CPU models in which having conflicting memory types still leads to
38 * unpredictable behavior, machine check errors, or hangs. Clear this
39 * feature to prevent its use on machines with known erratas.
41 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
43 switch (c->x86_model) {
44 case INTEL_FAM6_CORE_YONAH:
45 case INTEL_FAM6_CORE2_MEROM:
46 case INTEL_FAM6_CORE2_MEROM_L:
47 case INTEL_FAM6_CORE2_PENRYN:
48 case INTEL_FAM6_CORE2_DUNNINGTON:
49 case INTEL_FAM6_NEHALEM:
50 case INTEL_FAM6_NEHALEM_G:
51 case INTEL_FAM6_NEHALEM_EP:
52 case INTEL_FAM6_NEHALEM_EX:
53 case INTEL_FAM6_WESTMERE:
54 case INTEL_FAM6_WESTMERE_EP:
55 case INTEL_FAM6_SANDYBRIDGE:
56 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
60 static bool ring3mwait_disabled __read_mostly;
62 static int __init ring3mwait_disable(char *__unused)
64 ring3mwait_disabled = true;
67 __setup("ring3mwait=disable", ring3mwait_disable);
69 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
72 * Ring 3 MONITOR/MWAIT feature cannot be detected without
73 * cpu model and family comparison.
77 switch (c->x86_model) {
78 case INTEL_FAM6_XEON_PHI_KNL:
79 case INTEL_FAM6_XEON_PHI_KNM:
85 if (ring3mwait_disabled)
88 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
89 this_cpu_or(msr_misc_features_shadow,
90 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
92 if (c == &boot_cpu_data)
93 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
97 * Early microcode releases for the Spectre v2 mitigation were broken.
98 * Information taken from;
99 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
100 * - https://kb.vmware.com/s/article/52345
101 * - Microcode revisions observed in the wild
102 * - Release note from 20180108 microcode release
104 struct sku_microcode {
109 static const struct sku_microcode spectre_bad_microcodes[] = {
110 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
111 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
112 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
113 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
114 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
115 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
116 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
117 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
118 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
119 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
120 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
121 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
122 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
123 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
124 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
125 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
126 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
127 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
128 /* Observed in the wild */
129 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
130 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
133 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
138 * We know that the hypervisor lie to us on the microcode version so
139 * we may as well hope that it is running the correct version.
141 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
147 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
148 if (c->x86_model == spectre_bad_microcodes[i].model &&
149 c->x86_stepping == spectre_bad_microcodes[i].stepping)
150 return (c->microcode <= spectre_bad_microcodes[i].microcode);
155 static void early_init_intel(struct cpuinfo_x86 *c)
159 /* Unmask CPUID levels if masked: */
160 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
161 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
162 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
163 c->cpuid_level = cpuid_eax(0);
168 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
169 (c->x86 == 0x6 && c->x86_model >= 0x0e))
170 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
172 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
173 c->microcode = intel_get_microcode_revision();
175 /* Now if any of them are set, check the blacklist and clear the lot */
176 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
177 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
178 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
179 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
180 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
181 setup_clear_cpu_cap(X86_FEATURE_IBRS);
182 setup_clear_cpu_cap(X86_FEATURE_IBPB);
183 setup_clear_cpu_cap(X86_FEATURE_STIBP);
184 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
185 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
186 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
187 setup_clear_cpu_cap(X86_FEATURE_SSBD);
188 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
192 * Atom erratum AAE44/AAF40/AAG38/AAH41:
194 * A race condition between speculative fetches and invalidating
195 * a large page. This is worked around in microcode, but we
196 * need the microcode to have already been loaded... so if it is
197 * not, recommend a BIOS update and disable large pages.
199 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
200 c->microcode < 0x20e) {
201 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
202 clear_cpu_cap(c, X86_FEATURE_PSE);
206 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
208 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
209 if (c->x86 == 15 && c->x86_cache_alignment == 64)
210 c->x86_cache_alignment = 128;
213 /* CPUID workaround for 0F33/0F34 CPU */
214 if (c->x86 == 0xF && c->x86_model == 0x3
215 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
216 c->x86_phys_bits = 36;
219 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
220 * with P/T states and does not stop in deep C-states.
222 * It is also reliable across cores and sockets. (but not across
223 * cabinets - we turn it off in that case explicitly.)
225 if (c->x86_power & (1 << 8)) {
226 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
227 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
230 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
232 switch (c->x86_model) {
233 case INTEL_FAM6_ATOM_SALTWELL_MID:
234 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
235 case INTEL_FAM6_ATOM_SILVERMONT_MID:
236 case INTEL_FAM6_ATOM_AIRMONT_NP:
237 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
245 * There is a known erratum on Pentium III and Core Solo
247 * " Page with PAT set to WC while associated MTRR is UC
248 * may consolidate to UC "
249 * Because of this erratum, it is better to stick with
250 * setting WC in MTRR rather than using PAT on these CPUs.
252 * Enable PAT WC only on P4, Core 2 or later CPUs.
254 if (c->x86 == 6 && c->x86_model < 15)
255 clear_cpu_cap(c, X86_FEATURE_PAT);
258 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
259 * clear the fast string and enhanced fast string CPU capabilities.
261 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
262 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
263 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
264 pr_info("Disabled fast string operations\n");
265 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
266 setup_clear_cpu_cap(X86_FEATURE_ERMS);
271 * Intel Quark Core DevMan_001.pdf section 6.4.11
272 * "The operating system also is required to invalidate (i.e., flush)
273 * the TLB when any changes are made to any of the page table entries.
274 * The operating system must reload CR3 to cause the TLB to be flushed"
276 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
277 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
280 if (c->x86 == 5 && c->x86_model == 9) {
281 pr_info("Disabling PGE capability bit\n");
282 setup_clear_cpu_cap(X86_FEATURE_PGE);
285 if (c->cpuid_level >= 0x00000001) {
286 u32 eax, ebx, ecx, edx;
288 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
290 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
291 * apicids which are reserved per package. Store the resulting
292 * shift value for the package management code.
294 if (edx & (1U << 28))
295 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
298 check_memory_type_self_snoop_errata(c);
301 * Get the number of SMT siblings early from the extended topology
302 * leaf, if available. Otherwise try the legacy SMT detection.
304 if (detect_extended_topology_early(c) < 0)
310 * Early probe support logic for ppro memory erratum #50
312 * This is called before we do cpu ident work
315 int ppro_with_ram_bug(void)
317 /* Uses data from early_cpu_detect now */
318 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
319 boot_cpu_data.x86 == 6 &&
320 boot_cpu_data.x86_model == 1 &&
321 boot_cpu_data.x86_stepping < 8) {
322 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
328 static void intel_smp_check(struct cpuinfo_x86 *c)
330 /* calling is from identify_secondary_cpu() ? */
335 * Mask B, Pentium, but not Pentium MMX
338 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
341 * Remember we have B step Pentia with bugs
343 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
344 "with B stepping processors.\n");
349 static int __init forcepae_setup(char *__unused)
354 __setup("forcepae", forcepae_setup);
356 static void intel_workarounds(struct cpuinfo_x86 *c)
358 #ifdef CONFIG_X86_F00F_BUG
360 * All models of Pentium and Pentium with MMX technology CPUs
361 * have the F0 0F bug, which lets nonprivileged users lock up the
362 * system. Announce that the fault handler will be checking for it.
363 * The Quark is also family 5, but does not have the same bug.
365 clear_cpu_bug(c, X86_BUG_F00F);
366 if (c->x86 == 5 && c->x86_model < 9) {
367 static int f00f_workaround_enabled;
369 set_cpu_bug(c, X86_BUG_F00F);
370 if (!f00f_workaround_enabled) {
371 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
372 f00f_workaround_enabled = 1;
378 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
381 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
382 clear_cpu_cap(c, X86_FEATURE_SEP);
385 * PAE CPUID issue: many Pentium M report no PAE but may have a
386 * functionally usable PAE implementation.
387 * Forcefully enable PAE if kernel parameter "forcepae" is present.
390 pr_warn("PAE forced!\n");
391 set_cpu_cap(c, X86_FEATURE_PAE);
392 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
396 * P4 Xeon erratum 037 workaround.
397 * Hardware prefetcher may cause stale data to be loaded into the cache.
399 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
400 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
401 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
402 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
403 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
408 * See if we have a good local APIC by checking for buggy Pentia,
409 * i.e. all B steppings and the C2 stepping of P54C when using their
410 * integrated APIC (see 11AP erratum in "Pentium Processor
411 * Specification Update").
413 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
414 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
415 set_cpu_bug(c, X86_BUG_11AP);
418 #ifdef CONFIG_X86_INTEL_USERCOPY
420 * Set up the preferred alignment for movsl bulk memory moves
423 case 4: /* 486: untested */
425 case 5: /* Old Pentia: untested */
427 case 6: /* PII/PIII only like movsl with 8-byte alignment */
430 case 15: /* P4 is OK down to 8-byte alignment */
439 static void intel_workarounds(struct cpuinfo_x86 *c)
444 static void srat_detect_node(struct cpuinfo_x86 *c)
448 int cpu = smp_processor_id();
450 /* Don't do the funky fallback heuristics the AMD version employs
452 node = numa_cpu_node(cpu);
453 if (node == NUMA_NO_NODE || !node_online(node)) {
454 /* reuse the value from init_cpu_to_node() */
455 node = cpu_to_node(cpu);
457 numa_set_node(cpu, node);
461 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
463 /* Intel VMX MSR indicated features */
464 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
465 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
466 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
467 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
468 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
469 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
470 #define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000
472 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
473 u32 msr_vpid_cap, msr_ept_cap;
475 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
476 clear_cpu_cap(c, X86_FEATURE_VNMI);
477 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
478 clear_cpu_cap(c, X86_FEATURE_EPT);
479 clear_cpu_cap(c, X86_FEATURE_VPID);
480 clear_cpu_cap(c, X86_FEATURE_EPT_AD);
482 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
483 msr_ctl = vmx_msr_high | vmx_msr_low;
484 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
485 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
486 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
487 set_cpu_cap(c, X86_FEATURE_VNMI);
488 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
489 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
490 vmx_msr_low, vmx_msr_high);
491 msr_ctl2 = vmx_msr_high | vmx_msr_low;
492 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
493 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
494 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
495 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) {
496 set_cpu_cap(c, X86_FEATURE_EPT);
497 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
498 msr_ept_cap, msr_vpid_cap);
499 if (msr_ept_cap & x86_VMX_FEATURE_EPT_CAP_AD)
500 set_cpu_cap(c, X86_FEATURE_EPT_AD);
502 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
503 set_cpu_cap(c, X86_FEATURE_VPID);
507 #define MSR_IA32_TME_ACTIVATE 0x982
509 /* Helpers to access TME_ACTIVATE MSR */
510 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
511 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
513 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
514 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
516 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
518 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
519 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
521 /* Values for mktme_status (SW only construct) */
522 #define MKTME_ENABLED 0
523 #define MKTME_DISABLED 1
524 #define MKTME_UNINITIALIZED 2
525 static int mktme_status = MKTME_UNINITIALIZED;
527 static void detect_tme(struct cpuinfo_x86 *c)
529 u64 tme_activate, tme_policy, tme_crypto_algs;
530 int keyid_bits = 0, nr_keyids = 0;
531 static u64 tme_activate_cpu0 = 0;
533 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
535 if (mktme_status != MKTME_UNINITIALIZED) {
536 if (tme_activate != tme_activate_cpu0) {
538 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
539 pr_err_once("x86/tme: MKTME is not usable\n");
540 mktme_status = MKTME_DISABLED;
542 /* Proceed. We may need to exclude bits from x86_phys_bits. */
545 tme_activate_cpu0 = tme_activate;
548 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
549 pr_info_once("x86/tme: not enabled by BIOS\n");
550 mktme_status = MKTME_DISABLED;
554 if (mktme_status != MKTME_UNINITIALIZED)
555 goto detect_keyid_bits;
557 pr_info("x86/tme: enabled by BIOS\n");
559 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
560 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
561 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
563 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
564 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
565 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
567 mktme_status = MKTME_DISABLED;
570 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
571 nr_keyids = (1UL << keyid_bits) - 1;
573 pr_info_once("x86/mktme: enabled by BIOS\n");
574 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
576 pr_info_once("x86/mktme: disabled by BIOS\n");
579 if (mktme_status == MKTME_UNINITIALIZED) {
580 /* MKTME is usable */
581 mktme_status = MKTME_ENABLED;
585 * KeyID bits effectively lower the number of physical address
586 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
588 c->x86_phys_bits -= keyid_bits;
591 static void init_cpuid_fault(struct cpuinfo_x86 *c)
595 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
596 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
597 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
601 static void init_intel_misc_features(struct cpuinfo_x86 *c)
605 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
608 /* Clear all MISC features */
609 this_cpu_write(msr_misc_features_shadow, 0);
611 /* Check features and update capabilities and shadow control bits */
613 probe_xeon_phi_r3mwait(c);
615 msr = this_cpu_read(msr_misc_features_shadow);
616 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
619 static void init_intel(struct cpuinfo_x86 *c)
623 intel_workarounds(c);
626 * Detect the extended topology information if available. This
627 * will reinitialise the initial_apicid which will be used
628 * in init_intel_cacheinfo()
630 detect_extended_topology(c);
632 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
634 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
637 detect_num_cpu_cores(c);
643 init_intel_cacheinfo(c);
645 if (c->cpuid_level > 9) {
646 unsigned eax = cpuid_eax(10);
647 /* Check for version and the number of counters */
648 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
649 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
652 if (cpu_has(c, X86_FEATURE_XMM2))
653 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
655 if (boot_cpu_has(X86_FEATURE_DS)) {
658 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
660 set_cpu_cap(c, X86_FEATURE_BTS);
662 set_cpu_cap(c, X86_FEATURE_PEBS);
665 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
666 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
667 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
669 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
670 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
671 set_cpu_bug(c, X86_BUG_MONITOR);
675 c->x86_cache_alignment = c->x86_clflush_size * 2;
677 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
680 * Names for the Pentium II/Celeron processors
681 * detectable only by also checking the cache size.
682 * Dixon is NOT a Celeron.
685 unsigned int l2 = c->x86_cache_size;
688 switch (c->x86_model) {
691 p = "Celeron (Covington)";
693 p = "Mobile Pentium II (Dixon)";
698 p = "Celeron (Mendocino)";
699 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
705 p = "Celeron (Coppermine)";
710 strcpy(c->x86_model_id, p);
714 set_cpu_cap(c, X86_FEATURE_P4);
716 set_cpu_cap(c, X86_FEATURE_P3);
719 /* Work around errata */
722 if (cpu_has(c, X86_FEATURE_VMX))
723 detect_vmx_virtcap(c);
725 if (cpu_has(c, X86_FEATURE_TME))
728 init_intel_misc_features(c);
730 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
732 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
737 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
740 * Intel PIII Tualatin. This comes in two flavours.
741 * One has 256kb of cache, the other 512. We have no way
742 * to determine which, so we use a boottime override
743 * for the 512kb model, and assume 256 otherwise.
745 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
749 * Intel Quark SoC X1000 contains a 4-way set associative
750 * 16K cache with a 16 byte cache line and 256 lines per tag
752 if ((c->x86 == 5) && (c->x86_model == 9))
758 #define TLB_INST_4K 0x01
759 #define TLB_INST_4M 0x02
760 #define TLB_INST_2M_4M 0x03
762 #define TLB_INST_ALL 0x05
763 #define TLB_INST_1G 0x06
765 #define TLB_DATA_4K 0x11
766 #define TLB_DATA_4M 0x12
767 #define TLB_DATA_2M_4M 0x13
768 #define TLB_DATA_4K_4M 0x14
770 #define TLB_DATA_1G 0x16
772 #define TLB_DATA0_4K 0x21
773 #define TLB_DATA0_4M 0x22
774 #define TLB_DATA0_2M_4M 0x23
777 #define STLB_4K_2M 0x42
779 static const struct _tlb_table intel_tlb_table[] = {
780 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
781 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
782 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
783 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
784 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
785 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
786 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
787 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
788 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
789 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
790 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
791 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
792 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
793 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
794 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
795 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
796 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
797 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
798 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
799 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
800 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
801 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
802 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
803 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
804 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
805 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
806 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
807 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
808 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
809 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
810 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
811 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
812 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
813 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
814 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
815 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
819 static void intel_tlb_lookup(const unsigned char desc)
825 /* look up this descriptor in the table */
826 for (k = 0; intel_tlb_table[k].descriptor != desc && \
827 intel_tlb_table[k].descriptor != 0; k++)
830 if (intel_tlb_table[k].tlb_type == 0)
833 switch (intel_tlb_table[k].tlb_type) {
835 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
836 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
837 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
838 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
841 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
842 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
843 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
844 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
845 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
846 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
847 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
848 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
849 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
850 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
851 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
852 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
855 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
856 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
857 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
858 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
859 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
860 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
863 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
864 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
867 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
868 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
871 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
872 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
873 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
874 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
878 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
879 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
883 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
884 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
887 case TLB_DATA0_2M_4M:
888 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
890 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
891 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
894 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
895 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
896 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
897 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
900 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
901 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
906 static void intel_detect_tlb(struct cpuinfo_x86 *c)
909 unsigned int regs[4];
910 unsigned char *desc = (unsigned char *)regs;
912 if (c->cpuid_level < 2)
915 /* Number of times to iterate */
916 n = cpuid_eax(2) & 0xFF;
918 for (i = 0 ; i < n ; i++) {
919 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
921 /* If bit 31 is set, this is an unknown format */
922 for (j = 0 ; j < 3 ; j++)
923 if (regs[j] & (1 << 31))
926 /* Byte 0 is level count, not a descriptor */
927 for (j = 1 ; j < 16 ; j++)
928 intel_tlb_lookup(desc[j]);
932 static const struct cpu_dev intel_cpu_dev = {
934 .c_ident = { "GenuineIntel" },
937 { .family = 4, .model_names =
939 [0] = "486 DX-25/33",
950 { .family = 5, .model_names =
952 [0] = "Pentium 60/66 A-step",
953 [1] = "Pentium 60/66",
954 [2] = "Pentium 75 - 200",
955 [3] = "OverDrive PODP5V83",
957 [7] = "Mobile Pentium 75 - 200",
958 [8] = "Mobile Pentium MMX",
959 [9] = "Quark SoC X1000",
962 { .family = 6, .model_names =
964 [0] = "Pentium Pro A-step",
966 [3] = "Pentium II (Klamath)",
967 [4] = "Pentium II (Deschutes)",
968 [5] = "Pentium II (Deschutes)",
969 [6] = "Mobile Pentium II",
970 [7] = "Pentium III (Katmai)",
971 [8] = "Pentium III (Coppermine)",
972 [10] = "Pentium III (Cascades)",
973 [11] = "Pentium III (Tualatin)",
976 { .family = 15, .model_names =
978 [0] = "Pentium 4 (Unknown)",
979 [1] = "Pentium 4 (Willamette)",
980 [2] = "Pentium 4 (Northwood)",
981 [4] = "Pentium 4 (Foster)",
982 [5] = "Pentium 4 (Foster)",
986 .legacy_cache_size = intel_size_cache,
988 .c_detect_tlb = intel_detect_tlb,
989 .c_early_init = early_init_intel,
990 .c_init = init_intel,
991 .c_x86_vendor = X86_VENDOR_INTEL,
994 cpu_dev_register(intel_cpu_dev);