1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/api.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/microcode_intel.h>
63 #include <asm/intel-family.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/uv/uv.h>
66 #include <asm/set_memory.h>
67 #include <asm/traps.h>
72 u32 elf_hwcap2 __read_mostly;
74 /* Number of siblings per CPU package */
75 int smp_num_siblings = 1;
76 EXPORT_SYMBOL(smp_num_siblings);
78 /* Last level cache ID of each logical CPU */
79 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
81 u16 get_llc_id(unsigned int cpu)
83 return per_cpu(cpu_llc_id, cpu);
85 EXPORT_SYMBOL_GPL(get_llc_id);
87 /* L2 cache ID of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID;
90 static struct ppin_info {
95 [X86_VENDOR_INTEL] = {
96 .feature = X86_FEATURE_INTEL_PPIN,
97 .msr_ppin_ctl = MSR_PPIN_CTL,
101 .feature = X86_FEATURE_AMD_PPIN,
102 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
103 .msr_ppin = MSR_AMD_PPIN
107 static const struct x86_cpu_id ppin_cpuids[] = {
108 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
109 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
111 /* Legacy models without CPUID enumeration */
112 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
113 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
114 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
115 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
116 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
117 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
118 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
127 static void ppin_init(struct cpuinfo_x86 *c)
129 const struct x86_cpu_id *id;
130 unsigned long long val;
131 struct ppin_info *info;
133 id = x86_match_cpu(ppin_cpuids);
138 * Testing the presence of the MSR is not enough. Need to check
139 * that the PPIN_CTL allows reading of the PPIN.
141 info = (struct ppin_info *)id->driver_data;
143 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
146 if ((val & 3UL) == 1UL) {
147 /* PPIN locked in disabled mode */
151 /* If PPIN is disabled, try to enable */
153 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
154 rdmsrl_safe(info->msr_ppin_ctl, &val);
157 /* Is the enable bit set? */
159 c->ppin = __rdmsr(info->msr_ppin);
160 set_cpu_cap(c, info->feature);
165 clear_cpu_cap(c, info->feature);
168 static void default_init(struct cpuinfo_x86 *c)
171 cpu_detect_cache_sizes(c);
173 /* Not much we can do here... */
174 /* Check if at least it has cpuid */
175 if (c->cpuid_level == -1) {
176 /* No cpuid. It must be an ancient CPU */
178 strcpy(c->x86_model_id, "486");
179 else if (c->x86 == 3)
180 strcpy(c->x86_model_id, "386");
185 static const struct cpu_dev default_cpu = {
186 .c_init = default_init,
187 .c_vendor = "Unknown",
188 .c_x86_vendor = X86_VENDOR_UNKNOWN,
191 static const struct cpu_dev *this_cpu = &default_cpu;
193 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
196 * We need valid kernel segments for data and code in long mode too
197 * IRET will check the segment types kkeil 2000/10/28
198 * Also sysret mandates a special GDT layout
200 * TLS descriptors are currently at a different place compared to i386.
201 * Hopefully nobody expects them at a fixed place (Wine?)
203 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
204 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
205 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
206 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
207 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
208 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
210 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
211 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
212 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
213 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
215 * Segments used for calling PnP BIOS have byte granularity.
216 * They code segments and data segments have fixed 64k limits,
217 * the transfer segment sizes are set at run time.
220 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
222 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
224 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
226 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
228 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
230 * The APM segments have byte granularity and their bases
231 * are set at run time. All have 64k limits.
234 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
236 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
238 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
240 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
241 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
244 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
247 static int __init x86_nopcid_setup(char *s)
249 /* nopcid doesn't accept parameters */
253 /* do not emit a message if the feature is not present */
254 if (!boot_cpu_has(X86_FEATURE_PCID))
257 setup_clear_cpu_cap(X86_FEATURE_PCID);
258 pr_info("nopcid: PCID feature disabled\n");
261 early_param("nopcid", x86_nopcid_setup);
264 static int __init x86_noinvpcid_setup(char *s)
266 /* noinvpcid doesn't accept parameters */
270 /* do not emit a message if the feature is not present */
271 if (!boot_cpu_has(X86_FEATURE_INVPCID))
274 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
275 pr_info("noinvpcid: INVPCID feature disabled\n");
278 early_param("noinvpcid", x86_noinvpcid_setup);
281 static int cachesize_override = -1;
282 static int disable_x86_serial_nr = 1;
284 static int __init cachesize_setup(char *str)
286 get_option(&str, &cachesize_override);
289 __setup("cachesize=", cachesize_setup);
291 /* Standard macro to see if a specific flag is changeable */
292 static inline int flag_is_changeable_p(u32 flag)
297 * Cyrix and IDT cpus allow disabling of CPUID
298 * so the code below may return different results
299 * when it is executed before and after enabling
300 * the CPUID. Add "volatile" to not allow gcc to
301 * optimize the subsequent calls to this function.
303 asm volatile ("pushfl \n\t"
314 : "=&r" (f1), "=&r" (f2)
317 return ((f1^f2) & flag) != 0;
320 /* Probe for the CPUID instruction */
321 int have_cpuid_p(void)
323 return flag_is_changeable_p(X86_EFLAGS_ID);
326 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
328 unsigned long lo, hi;
330 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
333 /* Disable processor serial number: */
335 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
337 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
339 pr_notice("CPU serial number disabled.\n");
340 clear_cpu_cap(c, X86_FEATURE_PN);
342 /* Disabling the serial number may affect the cpuid level */
343 c->cpuid_level = cpuid_eax(0);
346 static int __init x86_serial_nr_setup(char *s)
348 disable_x86_serial_nr = 0;
351 __setup("serialnumber", x86_serial_nr_setup);
353 static inline int flag_is_changeable_p(u32 flag)
357 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
362 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
364 if (cpu_has(c, X86_FEATURE_SMEP))
365 cr4_set_bits(X86_CR4_SMEP);
368 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
370 unsigned long eflags = native_save_fl();
372 /* This should have been cleared long ago */
373 BUG_ON(eflags & X86_EFLAGS_AC);
375 if (cpu_has(c, X86_FEATURE_SMAP))
376 cr4_set_bits(X86_CR4_SMAP);
379 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
381 /* Check the boot processor, plus build option for UMIP. */
382 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
385 /* Check the current processor's cpuid bits. */
386 if (!cpu_has(c, X86_FEATURE_UMIP))
389 cr4_set_bits(X86_CR4_UMIP);
391 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
397 * Make sure UMIP is disabled in case it was enabled in a
398 * previous boot (e.g., via kexec).
400 cr4_clear_bits(X86_CR4_UMIP);
403 /* These bits should not change their value after CPU init is finished. */
404 static const unsigned long cr4_pinned_mask =
405 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
406 X86_CR4_FSGSBASE | X86_CR4_CET;
407 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
408 static unsigned long cr4_pinned_bits __ro_after_init;
410 void native_write_cr0(unsigned long val)
412 unsigned long bits_missing = 0;
415 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
417 if (static_branch_likely(&cr_pinning)) {
418 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
419 bits_missing = X86_CR0_WP;
423 /* Warn after we've set the missing bits. */
424 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
427 EXPORT_SYMBOL(native_write_cr0);
429 void __no_profile native_write_cr4(unsigned long val)
431 unsigned long bits_changed = 0;
434 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
436 if (static_branch_likely(&cr_pinning)) {
437 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
438 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
439 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
442 /* Warn after we've corrected the changed bits. */
443 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
447 #if IS_MODULE(CONFIG_LKDTM)
448 EXPORT_SYMBOL_GPL(native_write_cr4);
451 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
453 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
455 lockdep_assert_irqs_disabled();
457 newval = (cr4 & ~clear) | set;
459 this_cpu_write(cpu_tlbstate.cr4, newval);
463 EXPORT_SYMBOL(cr4_update_irqsoff);
465 /* Read the CR4 shadow. */
466 unsigned long cr4_read_shadow(void)
468 return this_cpu_read(cpu_tlbstate.cr4);
470 EXPORT_SYMBOL_GPL(cr4_read_shadow);
474 unsigned long cr4 = __read_cr4();
476 if (boot_cpu_has(X86_FEATURE_PCID))
477 cr4 |= X86_CR4_PCIDE;
478 if (static_branch_likely(&cr_pinning))
479 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
483 /* Initialize cr4 shadow for this CPU. */
484 this_cpu_write(cpu_tlbstate.cr4, cr4);
488 * Once CPU feature detection is finished (and boot params have been
489 * parsed), record any of the sensitive CR bits that are set, and
492 static void __init setup_cr_pinning(void)
494 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
495 static_key_enable(&cr_pinning.key);
498 static __init int x86_nofsgsbase_setup(char *arg)
500 /* Require an exact match without trailing characters. */
504 /* Do not emit a message if the feature is not present. */
505 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
508 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
509 pr_info("FSGSBASE disabled via kernel command line\n");
512 __setup("nofsgsbase", x86_nofsgsbase_setup);
515 * Protection Keys are not available in 32-bit mode.
517 static bool pku_disabled;
519 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
521 if (c == &boot_cpu_data) {
522 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
525 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
526 * bit to be set. Enforce it.
528 setup_force_cpu_cap(X86_FEATURE_OSPKE);
530 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
534 cr4_set_bits(X86_CR4_PKE);
535 /* Load the default PKRU value */
536 pkru_write_default();
539 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
540 static __init int setup_disable_pku(char *arg)
543 * Do not clear the X86_FEATURE_PKU bit. All of the
544 * runtime checks are against OSPKE so clearing the
547 * This way, we will see "pku" in cpuinfo, but not
548 * "ospke", which is exactly what we want. It shows
549 * that the CPU has PKU, but the OS has not enabled it.
550 * This happens to be exactly how a system would look
551 * if we disabled the config option.
553 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
557 __setup("nopku", setup_disable_pku);
560 #ifdef CONFIG_X86_KERNEL_IBT
562 __noendbr u64 ibt_save(bool disable)
566 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
567 rdmsrl(MSR_IA32_S_CET, msr);
569 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
575 __noendbr void ibt_restore(u64 save)
579 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
580 rdmsrl(MSR_IA32_S_CET, msr);
581 msr &= ~CET_ENDBR_EN;
582 msr |= (save & CET_ENDBR_EN);
583 wrmsrl(MSR_IA32_S_CET, msr);
589 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
591 u64 msr = CET_ENDBR_EN;
593 if (!HAS_KERNEL_IBT ||
594 !cpu_feature_enabled(X86_FEATURE_IBT))
597 wrmsrl(MSR_IA32_S_CET, msr);
598 cr4_set_bits(X86_CR4_CET);
600 if (!ibt_selftest()) {
601 pr_err("IBT selftest: Failed!\n");
602 wrmsrl(MSR_IA32_S_CET, 0);
603 setup_clear_cpu_cap(X86_FEATURE_IBT);
608 __noendbr void cet_disable(void)
610 if (cpu_feature_enabled(X86_FEATURE_IBT))
611 wrmsrl(MSR_IA32_S_CET, 0);
615 * Some CPU features depend on higher CPUID levels, which may not always
616 * be available due to CPUID level capping or broken virtualization
617 * software. Add those features to this table to auto-disable them.
619 struct cpuid_dependent_feature {
624 static const struct cpuid_dependent_feature
625 cpuid_dependent_features[] = {
626 { X86_FEATURE_MWAIT, 0x00000005 },
627 { X86_FEATURE_DCA, 0x00000009 },
628 { X86_FEATURE_XSAVE, 0x0000000d },
632 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
634 const struct cpuid_dependent_feature *df;
636 for (df = cpuid_dependent_features; df->feature; df++) {
638 if (!cpu_has(c, df->feature))
641 * Note: cpuid_level is set to -1 if unavailable, but
642 * extended_extended_level is set to 0 if unavailable
643 * and the legitimate extended levels are all negative
644 * when signed; hence the weird messing around with
647 if (!((s32)df->level < 0 ?
648 (u32)df->level > (u32)c->extended_cpuid_level :
649 (s32)df->level > (s32)c->cpuid_level))
652 clear_cpu_cap(c, df->feature);
656 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
657 x86_cap_flag(df->feature), df->level);
662 * Naming convention should be: <Name> [(<Codename>)]
663 * This table only is used unless init_<vendor>() below doesn't set it;
664 * in particular, if CPUID levels 0x80000002..4 are supported, this
668 /* Look up CPU names by table lookup. */
669 static const char *table_lookup_model(struct cpuinfo_x86 *c)
672 const struct legacy_cpu_model_info *info;
674 if (c->x86_model >= 16)
675 return NULL; /* Range check */
680 info = this_cpu->legacy_models;
682 while (info->family) {
683 if (info->family == c->x86)
684 return info->model_names[c->x86_model];
688 return NULL; /* Not found */
691 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
692 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
693 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
696 /* The 32-bit entry code needs to find cpu_entry_area. */
697 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
700 /* Load the original GDT from the per-cpu structure */
701 void load_direct_gdt(int cpu)
703 struct desc_ptr gdt_descr;
705 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
706 gdt_descr.size = GDT_SIZE - 1;
707 load_gdt(&gdt_descr);
709 EXPORT_SYMBOL_GPL(load_direct_gdt);
711 /* Load a fixmap remapping of the per-cpu GDT */
712 void load_fixmap_gdt(int cpu)
714 struct desc_ptr gdt_descr;
716 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
717 gdt_descr.size = GDT_SIZE - 1;
718 load_gdt(&gdt_descr);
720 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
723 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
724 * @cpu: The CPU number for which this is invoked
726 * Invoked during early boot to switch from early GDT and early per CPU to
727 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
728 * switch is implicit by loading the direct GDT. On 64bit this requires
731 void __init switch_gdt_and_percpu_base(int cpu)
733 load_direct_gdt(cpu);
737 * No need to load %gs. It is already correct.
739 * Writing %gs on 64bit would zero GSBASE which would make any per
740 * CPU operation up to the point of the wrmsrl() fault.
742 * Set GSBASE to the new offset. Until the wrmsrl() happens the
743 * early mapping is still valid. That means the GSBASE update will
744 * lose any prior per CPU data which was not copied over in
745 * setup_per_cpu_areas().
747 * This works even with stackprotector enabled because the
748 * per CPU stack canary is 0 in both per CPU areas.
750 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
753 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
754 * it is required to load FS again so that the 'hidden' part is
755 * updated from the new GDT. Up to this point the early per CPU
756 * translation is active. Any content of the early per CPU data
757 * which was not copied over in setup_per_cpu_areas() is lost.
759 loadsegment(fs, __KERNEL_PERCPU);
763 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
765 static void get_model_name(struct cpuinfo_x86 *c)
770 if (c->extended_cpuid_level < 0x80000004)
773 v = (unsigned int *)c->x86_model_id;
774 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
775 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
776 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
777 c->x86_model_id[48] = 0;
779 /* Trim whitespace */
780 p = q = s = &c->x86_model_id[0];
786 /* Note the last non-whitespace index */
796 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
798 unsigned int eax, ebx, ecx, edx;
800 c->x86_max_cores = 1;
801 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
804 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
806 c->x86_max_cores = (eax >> 26) + 1;
809 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
811 unsigned int n, dummy, ebx, ecx, edx, l2size;
813 n = c->extended_cpuid_level;
815 if (n >= 0x80000005) {
816 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
817 c->x86_cache_size = (ecx>>24) + (edx>>24);
819 /* On K8 L1 TLB is inclusive, so don't count it */
824 if (n < 0x80000006) /* Some chips just has a large L1. */
827 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
831 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
833 /* do processor-specific cache resizing */
834 if (this_cpu->legacy_cache_size)
835 l2size = this_cpu->legacy_cache_size(c, l2size);
837 /* Allow user to override all this if necessary. */
838 if (cachesize_override != -1)
839 l2size = cachesize_override;
842 return; /* Again, no L2 cache is possible */
845 c->x86_cache_size = l2size;
848 u16 __read_mostly tlb_lli_4k[NR_INFO];
849 u16 __read_mostly tlb_lli_2m[NR_INFO];
850 u16 __read_mostly tlb_lli_4m[NR_INFO];
851 u16 __read_mostly tlb_lld_4k[NR_INFO];
852 u16 __read_mostly tlb_lld_2m[NR_INFO];
853 u16 __read_mostly tlb_lld_4m[NR_INFO];
854 u16 __read_mostly tlb_lld_1g[NR_INFO];
856 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
858 if (this_cpu->c_detect_tlb)
859 this_cpu->c_detect_tlb(c);
861 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
862 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
863 tlb_lli_4m[ENTRIES]);
865 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
866 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
867 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
870 int detect_ht_early(struct cpuinfo_x86 *c)
873 u32 eax, ebx, ecx, edx;
875 if (!cpu_has(c, X86_FEATURE_HT))
878 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
881 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
884 cpuid(1, &eax, &ebx, &ecx, &edx);
886 smp_num_siblings = (ebx & 0xff0000) >> 16;
887 if (smp_num_siblings == 1)
888 pr_info_once("CPU0: Hyper-Threading is disabled\n");
893 void detect_ht(struct cpuinfo_x86 *c)
896 int index_msb, core_bits;
898 if (detect_ht_early(c) < 0)
901 index_msb = get_count_order(smp_num_siblings);
902 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
904 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
906 index_msb = get_count_order(smp_num_siblings);
908 core_bits = get_count_order(c->x86_max_cores);
910 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
911 ((1 << core_bits) - 1);
915 static void get_cpu_vendor(struct cpuinfo_x86 *c)
917 char *v = c->x86_vendor_id;
920 for (i = 0; i < X86_VENDOR_NUM; i++) {
924 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
925 (cpu_devs[i]->c_ident[1] &&
926 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
928 this_cpu = cpu_devs[i];
929 c->x86_vendor = this_cpu->c_x86_vendor;
934 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
935 "CPU: Your system may be unstable.\n", v);
937 c->x86_vendor = X86_VENDOR_UNKNOWN;
938 this_cpu = &default_cpu;
941 void cpu_detect(struct cpuinfo_x86 *c)
943 /* Get vendor name */
944 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
945 (unsigned int *)&c->x86_vendor_id[0],
946 (unsigned int *)&c->x86_vendor_id[8],
947 (unsigned int *)&c->x86_vendor_id[4]);
950 /* Intel-defined flags: level 0x00000001 */
951 if (c->cpuid_level >= 0x00000001) {
952 u32 junk, tfms, cap0, misc;
954 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
955 c->x86 = x86_family(tfms);
956 c->x86_model = x86_model(tfms);
957 c->x86_stepping = x86_stepping(tfms);
959 if (cap0 & (1<<19)) {
960 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
961 c->x86_cache_alignment = c->x86_clflush_size;
966 static void apply_forced_caps(struct cpuinfo_x86 *c)
970 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
971 c->x86_capability[i] &= ~cpu_caps_cleared[i];
972 c->x86_capability[i] |= cpu_caps_set[i];
976 static void init_speculation_control(struct cpuinfo_x86 *c)
979 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
980 * and they also have a different bit for STIBP support. Also,
981 * a hypervisor might have set the individual AMD bits even on
982 * Intel CPUs, for finer-grained selection of what's available.
984 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
985 set_cpu_cap(c, X86_FEATURE_IBRS);
986 set_cpu_cap(c, X86_FEATURE_IBPB);
987 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
990 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
991 set_cpu_cap(c, X86_FEATURE_STIBP);
993 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
994 cpu_has(c, X86_FEATURE_VIRT_SSBD))
995 set_cpu_cap(c, X86_FEATURE_SSBD);
997 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
998 set_cpu_cap(c, X86_FEATURE_IBRS);
999 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1002 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
1003 set_cpu_cap(c, X86_FEATURE_IBPB);
1005 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1006 set_cpu_cap(c, X86_FEATURE_STIBP);
1007 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1010 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
1011 set_cpu_cap(c, X86_FEATURE_SSBD);
1012 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1013 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
1017 void get_cpu_cap(struct cpuinfo_x86 *c)
1019 u32 eax, ebx, ecx, edx;
1021 /* Intel-defined flags: level 0x00000001 */
1022 if (c->cpuid_level >= 0x00000001) {
1023 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
1025 c->x86_capability[CPUID_1_ECX] = ecx;
1026 c->x86_capability[CPUID_1_EDX] = edx;
1029 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1030 if (c->cpuid_level >= 0x00000006)
1031 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
1033 /* Additional Intel-defined flags: level 0x00000007 */
1034 if (c->cpuid_level >= 0x00000007) {
1035 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
1036 c->x86_capability[CPUID_7_0_EBX] = ebx;
1037 c->x86_capability[CPUID_7_ECX] = ecx;
1038 c->x86_capability[CPUID_7_EDX] = edx;
1040 /* Check valid sub-leaf index before accessing it */
1042 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
1043 c->x86_capability[CPUID_7_1_EAX] = eax;
1047 /* Extended state features: level 0x0000000d */
1048 if (c->cpuid_level >= 0x0000000d) {
1049 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1051 c->x86_capability[CPUID_D_1_EAX] = eax;
1054 /* AMD-defined flags: level 0x80000001 */
1055 eax = cpuid_eax(0x80000000);
1056 c->extended_cpuid_level = eax;
1058 if ((eax & 0xffff0000) == 0x80000000) {
1059 if (eax >= 0x80000001) {
1060 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1062 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1063 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1067 if (c->extended_cpuid_level >= 0x80000007) {
1068 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1070 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1074 if (c->extended_cpuid_level >= 0x80000008) {
1075 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1076 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1079 if (c->extended_cpuid_level >= 0x8000000a)
1080 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1082 if (c->extended_cpuid_level >= 0x8000001f)
1083 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1085 if (c->extended_cpuid_level >= 0x80000021)
1086 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1088 init_scattered_cpuid_features(c);
1089 init_speculation_control(c);
1092 * Clear/Set all flags overridden by options, after probe.
1093 * This needs to happen each time we re-probe, which may happen
1094 * several times during CPU initialization.
1096 apply_forced_caps(c);
1099 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1101 u32 eax, ebx, ecx, edx;
1103 if (c->extended_cpuid_level >= 0x80000008) {
1104 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1106 c->x86_virt_bits = (eax >> 8) & 0xff;
1107 c->x86_phys_bits = eax & 0xff;
1109 #ifdef CONFIG_X86_32
1110 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
1111 c->x86_phys_bits = 36;
1113 c->x86_cache_bits = c->x86_phys_bits;
1116 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1118 #ifdef CONFIG_X86_32
1122 * First of all, decide if this is a 486 or higher
1123 * It's a 486 if we can modify the AC flag
1125 if (flag_is_changeable_p(X86_EFLAGS_AC))
1130 for (i = 0; i < X86_VENDOR_NUM; i++)
1131 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1132 c->x86_vendor_id[0] = 0;
1133 cpu_devs[i]->c_identify(c);
1134 if (c->x86_vendor_id[0]) {
1142 #define NO_SPECULATION BIT(0)
1143 #define NO_MELTDOWN BIT(1)
1144 #define NO_SSB BIT(2)
1145 #define NO_L1TF BIT(3)
1146 #define NO_MDS BIT(4)
1147 #define MSBDS_ONLY BIT(5)
1148 #define NO_SWAPGS BIT(6)
1149 #define NO_ITLB_MULTIHIT BIT(7)
1150 #define NO_SPECTRE_V2 BIT(8)
1151 #define NO_MMIO BIT(9)
1152 #define NO_EIBRS_PBRSB BIT(10)
1154 #define VULNWL(vendor, family, model, whitelist) \
1155 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1157 #define VULNWL_INTEL(model, whitelist) \
1158 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1160 #define VULNWL_AMD(family, whitelist) \
1161 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1163 #define VULNWL_HYGON(family, whitelist) \
1164 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1166 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1167 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1168 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1169 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1170 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1171 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1172 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1174 /* Intel Family 6 */
1175 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1176 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1177 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1178 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1180 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1181 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1182 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1183 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1184 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1186 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1187 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1188 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1189 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1190 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1191 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1193 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1195 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1196 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1198 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1199 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1200 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1203 * Technically, swapgs isn't serializing on AMD (despite it previously
1204 * being documented as such in the APM). But according to AMD, %gs is
1205 * updated non-speculatively, and the issuing of %gs-relative memory
1206 * operands will be blocked until the %gs update completes, which is
1207 * good enough for our purposes.
1210 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
1211 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1212 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1214 /* AMD Family 0xf - 0x12 */
1215 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1216 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1217 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1218 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1220 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1221 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1222 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1224 /* Zhaoxin Family 7 */
1225 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1226 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1230 #define VULNBL(vendor, family, model, blacklist) \
1231 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1233 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1234 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1235 INTEL_FAM6_##model, steppings, \
1236 X86_FEATURE_ANY, issues)
1238 #define VULNBL_AMD(family, blacklist) \
1239 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1241 #define VULNBL_HYGON(family, blacklist) \
1242 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1244 #define SRBDS BIT(0)
1245 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1247 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1248 #define MMIO_SBDS BIT(2)
1249 /* CPU is affected by RETbleed, speculating where you would not expect it */
1250 #define RETBLEED BIT(3)
1251 /* CPU is affected by SMT (cross-thread) return predictions */
1252 #define SMT_RSB BIT(4)
1253 /* CPU is affected by SRSO */
1255 /* CPU is affected by GDS */
1258 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1259 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1260 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1261 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1262 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1263 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1264 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1265 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1266 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1267 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1268 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1269 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1270 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED),
1271 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS),
1272 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS),
1273 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1274 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1275 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1276 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1277 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1278 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1279 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1280 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1281 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS),
1282 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1283 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1284 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1285 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO),
1286 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1288 VULNBL_AMD(0x15, RETBLEED),
1289 VULNBL_AMD(0x16, RETBLEED),
1290 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1291 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB),
1292 VULNBL_AMD(0x19, SRSO),
1296 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1298 const struct x86_cpu_id *m = x86_match_cpu(table);
1300 return m && !!(m->driver_data & which);
1303 u64 x86_read_arch_cap_msr(void)
1307 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1308 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1313 static bool arch_cap_mmio_immune(u64 ia32_cap)
1315 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1316 ia32_cap & ARCH_CAP_PSDP_NO &&
1317 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1320 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1322 u64 ia32_cap = x86_read_arch_cap_msr();
1324 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1325 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1326 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1327 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1329 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1332 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1334 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1335 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1337 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1338 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1339 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1340 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1343 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1344 * flag and protect from vendor-specific bugs via the whitelist.
1346 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) {
1347 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1348 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1349 !(ia32_cap & ARCH_CAP_PBRSB_NO))
1350 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1353 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1354 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1355 setup_force_cpu_bug(X86_BUG_MDS);
1356 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1357 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1360 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1361 setup_force_cpu_bug(X86_BUG_SWAPGS);
1364 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1365 * - TSX is supported or
1366 * - TSX_CTRL is present
1368 * TSX_CTRL check is needed for cases when TSX could be disabled before
1369 * the kernel boot e.g. kexec.
1370 * TSX_CTRL check alone is not sufficient for cases when the microcode
1371 * update is not present or running as guest that don't get TSX_CTRL.
1373 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1374 (cpu_has(c, X86_FEATURE_RTM) ||
1375 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1376 setup_force_cpu_bug(X86_BUG_TAA);
1379 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1380 * in the vulnerability blacklist.
1382 * Some of the implications and mitigation of Shared Buffers Data
1383 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1386 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1387 cpu_has(c, X86_FEATURE_RDSEED)) &&
1388 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1389 setup_force_cpu_bug(X86_BUG_SRBDS);
1392 * Processor MMIO Stale Data bug enumeration
1394 * Affected CPU list is generally enough to enumerate the vulnerability,
1395 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1396 * not want the guest to enumerate the bug.
1398 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1399 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1401 if (!arch_cap_mmio_immune(ia32_cap)) {
1402 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1403 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1404 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1405 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1408 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1409 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))
1410 setup_force_cpu_bug(X86_BUG_RETBLEED);
1413 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1414 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1416 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1417 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1418 setup_force_cpu_bug(X86_BUG_SRSO);
1422 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1423 * an affected processor, the VMM may have disabled the use of GATHER by
1424 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1425 * which means that AVX will be disabled.
1427 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) &&
1428 boot_cpu_has(X86_FEATURE_AVX))
1429 setup_force_cpu_bug(X86_BUG_GDS);
1431 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1434 /* Rogue Data Cache Load? No! */
1435 if (ia32_cap & ARCH_CAP_RDCL_NO)
1438 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1440 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1443 setup_force_cpu_bug(X86_BUG_L1TF);
1447 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1448 * unfortunately, that's not true in practice because of early VIA
1449 * chips and (more importantly) broken virtualizers that are not easy
1450 * to detect. In the latter case it doesn't even *fail* reliably, so
1451 * probing for it doesn't even work. Disable it completely on 32-bit
1452 * unless we can find a reliable way to detect all the broken cases.
1453 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1455 static void detect_nopl(void)
1457 #ifdef CONFIG_X86_32
1458 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1460 setup_force_cpu_cap(X86_FEATURE_NOPL);
1465 * We parse cpu parameters early because fpu__init_system() is executed
1466 * before parse_early_param().
1468 static void __init cpu_parse_early_param(void)
1471 char *argptr = arg, *opt;
1472 int arglen, taint = 0;
1474 #ifdef CONFIG_X86_32
1475 if (cmdline_find_option_bool(boot_command_line, "no387"))
1476 #ifdef CONFIG_MATH_EMULATION
1477 setup_clear_cpu_cap(X86_FEATURE_FPU);
1479 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1482 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1483 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1486 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1487 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1489 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1490 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1492 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1493 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1495 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1499 pr_info("Clearing CPUID bits:");
1502 bool found __maybe_unused = false;
1505 opt = strsep(&argptr, ",");
1508 * Handle naked numbers first for feature flags which don't
1511 if (!kstrtouint(opt, 10, &bit)) {
1512 if (bit < NCAPINTS * 32) {
1514 /* empty-string, i.e., ""-defined feature flags */
1515 if (!x86_cap_flags[bit])
1516 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1518 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1520 setup_clear_cpu_cap(bit);
1524 * The assumption is that there are no feature names with only
1525 * numbers in the name thus go to the next argument.
1530 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1531 if (!x86_cap_flag(bit))
1534 if (strcmp(x86_cap_flag(bit), opt))
1537 pr_cont(" %s", opt);
1538 setup_clear_cpu_cap(bit);
1545 pr_cont(" (unknown: %s)", opt);
1550 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1554 * Do minimum CPU detection early.
1555 * Fields really needed: vendor, cpuid_level, family, model, mask,
1557 * The others are not touched to avoid unwanted side effects.
1559 * WARNING: this function is only called on the boot CPU. Don't add code
1560 * here that is supposed to run on all CPUs.
1562 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1564 #ifdef CONFIG_X86_64
1565 c->x86_clflush_size = 64;
1566 c->x86_phys_bits = 36;
1567 c->x86_virt_bits = 48;
1569 c->x86_clflush_size = 32;
1570 c->x86_phys_bits = 32;
1571 c->x86_virt_bits = 32;
1573 c->x86_cache_alignment = c->x86_clflush_size;
1575 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1576 c->extended_cpuid_level = 0;
1578 if (!have_cpuid_p())
1579 identify_cpu_without_cpuid(c);
1581 /* cyrix could have cpuid enabled via c_identify()*/
1582 if (have_cpuid_p()) {
1586 get_cpu_address_sizes(c);
1587 setup_force_cpu_cap(X86_FEATURE_CPUID);
1588 cpu_parse_early_param();
1590 if (this_cpu->c_early_init)
1591 this_cpu->c_early_init(c);
1594 filter_cpuid_features(c, false);
1596 if (this_cpu->c_bsp_init)
1597 this_cpu->c_bsp_init(c);
1599 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1602 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1604 cpu_set_bug_bits(c);
1608 #ifdef CONFIG_X86_32
1610 * Regardless of whether PCID is enumerated, the SDM says
1611 * that it can't be enabled in 32-bit mode.
1613 setup_clear_cpu_cap(X86_FEATURE_PCID);
1617 * Later in the boot process pgtable_l5_enabled() relies on
1618 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1619 * enabled by this point we need to clear the feature bit to avoid
1620 * false-positives at the later stage.
1622 * pgtable_l5_enabled() can be false here for several reasons:
1623 * - 5-level paging is disabled compile-time;
1624 * - it's 32-bit kernel;
1625 * - machine doesn't support 5-level paging;
1626 * - user specified 'no5lvl' in kernel command line.
1628 if (!pgtable_l5_enabled())
1629 setup_clear_cpu_cap(X86_FEATURE_LA57);
1634 void __init early_cpu_init(void)
1636 const struct cpu_dev *const *cdev;
1639 #ifdef CONFIG_PROCESSOR_SELECT
1640 pr_info("KERNEL supported cpus:\n");
1643 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1644 const struct cpu_dev *cpudev = *cdev;
1646 if (count >= X86_VENDOR_NUM)
1648 cpu_devs[count] = cpudev;
1651 #ifdef CONFIG_PROCESSOR_SELECT
1655 for (j = 0; j < 2; j++) {
1656 if (!cpudev->c_ident[j])
1658 pr_info(" %s %s\n", cpudev->c_vendor,
1659 cpudev->c_ident[j]);
1664 early_identify_cpu(&boot_cpu_data);
1667 static bool detect_null_seg_behavior(void)
1670 * Empirically, writing zero to a segment selector on AMD does
1671 * not clear the base, whereas writing zero to a segment
1672 * selector on Intel does clear the base. Intel's behavior
1673 * allows slightly faster context switches in the common case
1674 * where GS is unused by the prev and next threads.
1676 * Since neither vendor documents this anywhere that I can see,
1677 * detect it directly instead of hard-coding the choice by
1680 * I've designated AMD's behavior as the "bug" because it's
1681 * counterintuitive and less friendly.
1684 unsigned long old_base, tmp;
1685 rdmsrl(MSR_FS_BASE, old_base);
1686 wrmsrl(MSR_FS_BASE, 1);
1688 rdmsrl(MSR_FS_BASE, tmp);
1689 wrmsrl(MSR_FS_BASE, old_base);
1693 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1695 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1696 if (!IS_ENABLED(CONFIG_X86_64))
1699 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1703 * CPUID bit above wasn't set. If this kernel is still running
1704 * as a HV guest, then the HV has decided not to advertize
1705 * that CPUID bit for whatever reason. For example, one
1706 * member of the migration pool might be vulnerable. Which
1707 * means, the bug is present: set the BUG flag and return.
1709 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1710 set_cpu_bug(c, X86_BUG_NULL_SEG);
1715 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1716 * 0x18 is the respective family for Hygon.
1718 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1719 detect_null_seg_behavior())
1722 /* All the remaining ones are affected */
1723 set_cpu_bug(c, X86_BUG_NULL_SEG);
1726 static void generic_identify(struct cpuinfo_x86 *c)
1728 c->extended_cpuid_level = 0;
1730 if (!have_cpuid_p())
1731 identify_cpu_without_cpuid(c);
1733 /* cyrix could have cpuid enabled via c_identify()*/
1734 if (!have_cpuid_p())
1743 get_cpu_address_sizes(c);
1745 if (c->cpuid_level >= 0x00000001) {
1746 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1747 #ifdef CONFIG_X86_32
1749 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1751 c->apicid = c->initial_apicid;
1754 c->phys_proc_id = c->initial_apicid;
1757 get_model_name(c); /* Default name */
1760 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1761 * systems that run Linux at CPL > 0 may or may not have the
1762 * issue, but, even if they have the issue, there's absolutely
1763 * nothing we can do about it because we can't use the real IRET
1766 * NB: For the time being, only 32-bit kernels support
1767 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1768 * whether to apply espfix using paravirt hooks. If any
1769 * non-paravirt system ever shows up that does *not* have the
1770 * ESPFIX issue, we can change this.
1772 #ifdef CONFIG_X86_32
1773 set_cpu_bug(c, X86_BUG_ESPFIX);
1778 * Validate that ACPI/mptables have the same information about the
1779 * effective APIC id and update the package map.
1781 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1784 unsigned int apicid, cpu = smp_processor_id();
1786 apicid = apic->cpu_present_to_apicid(cpu);
1788 if (apicid != c->apicid) {
1789 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1790 cpu, apicid, c->initial_apicid);
1792 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1793 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1795 c->logical_proc_id = 0;
1800 * This does the hard work of actually picking apart the CPU stuff...
1802 static void identify_cpu(struct cpuinfo_x86 *c)
1806 c->loops_per_jiffy = loops_per_jiffy;
1807 c->x86_cache_size = 0;
1808 c->x86_vendor = X86_VENDOR_UNKNOWN;
1809 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1810 c->x86_vendor_id[0] = '\0'; /* Unset */
1811 c->x86_model_id[0] = '\0'; /* Unset */
1812 c->x86_max_cores = 1;
1813 c->x86_coreid_bits = 0;
1815 #ifdef CONFIG_X86_64
1816 c->x86_clflush_size = 64;
1817 c->x86_phys_bits = 36;
1818 c->x86_virt_bits = 48;
1820 c->cpuid_level = -1; /* CPUID not detected */
1821 c->x86_clflush_size = 32;
1822 c->x86_phys_bits = 32;
1823 c->x86_virt_bits = 32;
1825 c->x86_cache_alignment = c->x86_clflush_size;
1826 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1827 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1828 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1831 generic_identify(c);
1833 if (this_cpu->c_identify)
1834 this_cpu->c_identify(c);
1836 /* Clear/Set all flags overridden by options, after probe */
1837 apply_forced_caps(c);
1839 #ifdef CONFIG_X86_64
1840 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1844 * Vendor-specific initialization. In this section we
1845 * canonicalize the feature flags, meaning if there are
1846 * features a certain CPU supports which CPUID doesn't
1847 * tell us, CPUID claiming incorrect flags, or other bugs,
1848 * we handle them here.
1850 * At the end of this section, c->x86_capability better
1851 * indicate the features this CPU genuinely supports!
1853 if (this_cpu->c_init)
1854 this_cpu->c_init(c);
1856 /* Disable the PN if appropriate */
1857 squash_the_stupid_serial_number(c);
1859 /* Set up SMEP/SMAP/UMIP */
1864 /* Enable FSGSBASE instructions if available. */
1865 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1866 cr4_set_bits(X86_CR4_FSGSBASE);
1867 elf_hwcap2 |= HWCAP2_FSGSBASE;
1871 * The vendor-specific functions might have changed features.
1872 * Now we do "generic changes."
1875 /* Filter out anything that depends on CPUID levels we don't have */
1876 filter_cpuid_features(c, true);
1878 /* If the model name is still unset, do table lookup. */
1879 if (!c->x86_model_id[0]) {
1881 p = table_lookup_model(c);
1883 strcpy(c->x86_model_id, p);
1885 /* Last resort... */
1886 sprintf(c->x86_model_id, "%02x/%02x",
1887 c->x86, c->x86_model);
1890 #ifdef CONFIG_X86_64
1899 * Clear/Set all flags overridden by options, need do it
1900 * before following smp all cpus cap AND.
1902 apply_forced_caps(c);
1905 * On SMP, boot_cpu_data holds the common feature set between
1906 * all CPUs; so make sure that we indicate which features are
1907 * common between the CPUs. The first time this routine gets
1908 * executed, c == &boot_cpu_data.
1910 if (c != &boot_cpu_data) {
1911 /* AND the already accumulated flags with these */
1912 for (i = 0; i < NCAPINTS; i++)
1913 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1915 /* OR, i.e. replicate the bug flags */
1916 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1917 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1922 /* Init Machine Check Exception if available. */
1925 select_idle_routine(c);
1928 numa_add_cpu(smp_processor_id());
1933 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1934 * on 32-bit kernels:
1936 #ifdef CONFIG_X86_32
1937 void enable_sep_cpu(void)
1939 struct tss_struct *tss;
1942 if (!boot_cpu_has(X86_FEATURE_SEP))
1946 tss = &per_cpu(cpu_tss_rw, cpu);
1949 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1950 * see the big comment in struct x86_hw_tss's definition.
1953 tss->x86_tss.ss1 = __KERNEL_CS;
1954 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1955 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1956 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1962 void __init identify_boot_cpu(void)
1964 identify_cpu(&boot_cpu_data);
1965 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1966 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1967 #ifdef CONFIG_X86_32
1970 cpu_detect_tlb(&boot_cpu_data);
1977 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1979 BUG_ON(c == &boot_cpu_data);
1981 #ifdef CONFIG_X86_32
1984 validate_apic_and_package_id(c);
1985 x86_spec_ctrl_setup_ap();
1987 if (boot_cpu_has_bug(X86_BUG_GDS))
1993 void print_cpu_info(struct cpuinfo_x86 *c)
1995 const char *vendor = NULL;
1997 if (c->x86_vendor < X86_VENDOR_NUM) {
1998 vendor = this_cpu->c_vendor;
2000 if (c->cpuid_level >= 0)
2001 vendor = c->x86_vendor_id;
2004 if (vendor && !strstr(c->x86_model_id, vendor))
2005 pr_cont("%s ", vendor);
2007 if (c->x86_model_id[0])
2008 pr_cont("%s", c->x86_model_id);
2010 pr_cont("%d86", c->x86);
2012 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
2014 if (c->x86_stepping || c->cpuid_level >= 0)
2015 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
2021 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
2022 * function prevents it from becoming an environment variable for init.
2024 static __init int setup_clearcpuid(char *arg)
2028 __setup("clearcpuid=", setup_clearcpuid);
2030 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2031 .current_task = &init_task,
2032 .preempt_count = INIT_PREEMPT_COUNT,
2033 .top_of_stack = TOP_OF_INIT_STACK,
2035 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2037 #ifdef CONFIG_X86_64
2038 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2039 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2040 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2042 static void wrmsrl_cstar(unsigned long val)
2045 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2046 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2047 * guest. Avoid the pointless write on all Intel CPUs.
2049 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2050 wrmsrl(MSR_CSTAR, val);
2053 /* May not be marked __init: used by software suspend */
2054 void syscall_init(void)
2056 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
2057 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2059 #ifdef CONFIG_IA32_EMULATION
2060 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2062 * This only works on Intel CPUs.
2063 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2064 * This does not cause SYSENTER to jump to the wrong location, because
2065 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2067 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2068 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2069 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2070 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2072 wrmsrl_cstar((unsigned long)ignore_sysret);
2073 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2074 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2075 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2079 * Flags to clear on syscall; clear as much as possible
2080 * to minimize user space-kernel interference.
2082 wrmsrl(MSR_SYSCALL_MASK,
2083 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2084 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2085 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2086 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2087 X86_EFLAGS_AC|X86_EFLAGS_ID);
2090 #else /* CONFIG_X86_64 */
2092 #ifdef CONFIG_STACKPROTECTOR
2093 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2094 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2097 #endif /* CONFIG_X86_64 */
2100 * Clear all 6 debug registers:
2102 static void clear_all_debug_regs(void)
2106 for (i = 0; i < 8; i++) {
2107 /* Ignore db4, db5 */
2108 if ((i == 4) || (i == 5))
2117 * Restore debug regs if using kgdbwait and you have a kernel debugger
2118 * connection established.
2120 static void dbg_restore_debug_regs(void)
2122 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2123 arch_kgdb_ops.correct_hw_break();
2125 #else /* ! CONFIG_KGDB */
2126 #define dbg_restore_debug_regs()
2127 #endif /* ! CONFIG_KGDB */
2129 static inline void setup_getcpu(int cpu)
2131 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2132 struct desc_struct d = { };
2134 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2135 wrmsr(MSR_TSC_AUX, cpudata, 0);
2137 /* Store CPU and node number in limit. */
2139 d.limit1 = cpudata >> 16;
2141 d.type = 5; /* RO data, expand down, accessed */
2142 d.dpl = 3; /* Visible to user code */
2143 d.s = 1; /* Not a system segment */
2144 d.p = 1; /* Present */
2145 d.d = 1; /* 32-bit */
2147 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2150 #ifdef CONFIG_X86_64
2151 static inline void ucode_cpu_init(int cpu) { }
2153 static inline void tss_setup_ist(struct tss_struct *tss)
2155 /* Set up the per-CPU TSS IST stacks */
2156 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2157 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2158 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2159 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2160 /* Only mapped when SEV-ES is active */
2161 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2164 #else /* CONFIG_X86_64 */
2166 static inline void ucode_cpu_init(int cpu)
2168 show_ucode_info_early();
2171 static inline void tss_setup_ist(struct tss_struct *tss) { }
2173 #endif /* !CONFIG_X86_64 */
2175 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2177 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2179 #ifdef CONFIG_X86_IOPL_IOPERM
2180 tss->io_bitmap.prev_max = 0;
2181 tss->io_bitmap.prev_sequence = 0;
2182 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2184 * Invalidate the extra array entry past the end of the all
2185 * permission bitmap as required by the hardware.
2187 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2192 * Setup everything needed to handle exceptions from the IDT, including the IST
2193 * exceptions which use paranoid_entry().
2195 void cpu_init_exception_handling(void)
2197 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2198 int cpu = raw_smp_processor_id();
2200 /* paranoid_entry() gets the CPU number from the GDT */
2203 /* IST vectors need TSS to be set up. */
2205 tss_setup_io_bitmap(tss);
2206 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2210 /* GHCB needs to be setup to handle #VC. */
2213 /* Finally load the IDT */
2218 * cpu_init() initializes state that is per-CPU. Some data is already
2219 * initialized (naturally) in the bootstrap process, such as the GDT. We
2220 * reload it nevertheless, this function acts as a 'CPU state barrier',
2221 * nothing should get across.
2225 struct task_struct *cur = current;
2226 int cpu = raw_smp_processor_id();
2228 ucode_cpu_init(cpu);
2231 if (this_cpu_read(numa_node) == 0 &&
2232 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2233 set_numa_node(early_cpu_to_node(cpu));
2235 pr_debug("Initializing CPU#%d\n", cpu);
2237 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2238 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2239 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2241 if (IS_ENABLED(CONFIG_X86_64)) {
2243 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2246 wrmsrl(MSR_FS_BASE, 0);
2247 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2254 cur->active_mm = &init_mm;
2256 initialize_tlbstate_and_flush();
2257 enter_lazy_tlb(&init_mm, cur);
2260 * sp0 points to the entry trampoline stack regardless of what task
2263 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2265 load_mm_ldt(&init_mm);
2267 clear_all_debug_regs();
2268 dbg_restore_debug_regs();
2270 doublefault_init_cpu_tss();
2275 load_fixmap_gdt(cpu);
2278 #ifdef CONFIG_MICROCODE_LATE_LOADING
2280 * store_cpu_caps() - Store a snapshot of CPU capabilities
2281 * @curr_info: Pointer where to store it
2285 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2287 /* Reload CPUID max function as it might've changed. */
2288 curr_info->cpuid_level = cpuid_eax(0);
2290 /* Copy all capability leafs and pick up the synthetic ones. */
2291 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2292 sizeof(curr_info->x86_capability));
2294 /* Get the hardware CPUID leafs */
2295 get_cpu_cap(curr_info);
2299 * microcode_check() - Check if any CPU capabilities changed after an update.
2300 * @prev_info: CPU capabilities stored before an update.
2302 * The microcode loader calls this upon late microcode load to recheck features,
2303 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2308 void microcode_check(struct cpuinfo_x86 *prev_info)
2310 struct cpuinfo_x86 curr_info;
2312 perf_check_microcode();
2314 amd_check_microcode();
2316 store_cpu_caps(&curr_info);
2318 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2319 sizeof(prev_info->x86_capability)))
2322 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2323 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2328 * Invoked from core CPU hotplug code after hotplug operations
2330 void arch_smt_update(void)
2332 /* Handle the speculative execution misfeatures */
2333 cpu_bugs_smt_update();
2334 /* Check whether IPI broadcasting can be enabled */
2338 void __init arch_cpu_finalize_init(void)
2340 identify_boot_cpu();
2343 * identify_boot_cpu() initialized SMT support information, let the
2346 cpu_smt_check_topology();
2348 if (!IS_ENABLED(CONFIG_SMP)) {
2350 print_cpu_info(&boot_cpu_data);
2353 cpu_select_mitigations();
2357 if (IS_ENABLED(CONFIG_X86_32)) {
2359 * Check whether this is a real i386 which is not longer
2360 * supported and fixup the utsname.
2362 if (boot_cpu_data.x86 < 4)
2363 panic("Kernel requires i486+ for 'invlpg' and other features");
2365 init_utsname()->machine[1] =
2366 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2370 * Must be before alternatives because it might set or clear
2376 alternative_instructions();
2378 if (IS_ENABLED(CONFIG_X86_64)) {
2380 * Make sure the first 2MB area is not mapped by huge pages
2381 * There are typically fixed size MTRRs in there and overlapping
2382 * MTRRs into large pages causes slow downs.
2384 * Right now we don't do that with gbpages because there seems
2385 * very little benefit for that case.
2387 if (!direct_gbpages)
2388 set_memory_4k((unsigned long)__va(0), 1);
2390 fpu__init_check_bugs();
2394 * This needs to be called before any devices perform DMA
2395 * operations that might use the SWIOTLB bounce buffers. It will
2396 * mark the bounce buffers as decrypted so that their usage will
2397 * not cause "plain-text" data to be decrypted when accessed. It
2398 * must be called after late_time_init() so that Hyper-V x86/x64
2399 * hypercalls work when the SWIOTLB bounce buffers are decrypted.