1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/api.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/intel-family.h>
63 #include <asm/cpu_device_id.h>
64 #include <asm/uv/uv.h>
65 #include <asm/set_memory.h>
66 #include <asm/traps.h>
71 u32 elf_hwcap2 __read_mostly;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings = 1;
75 EXPORT_SYMBOL(smp_num_siblings);
77 /* Last level cache ID of each logical CPU */
78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
80 u16 get_llc_id(unsigned int cpu)
82 return per_cpu(cpu_llc_id, cpu);
84 EXPORT_SYMBOL_GPL(get_llc_id);
86 /* L2 cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID;
89 static struct ppin_info {
94 [X86_VENDOR_INTEL] = {
95 .feature = X86_FEATURE_INTEL_PPIN,
96 .msr_ppin_ctl = MSR_PPIN_CTL,
100 .feature = X86_FEATURE_AMD_PPIN,
101 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
102 .msr_ppin = MSR_AMD_PPIN
106 static const struct x86_cpu_id ppin_cpuids[] = {
107 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
108 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
110 /* Legacy models without CPUID enumeration */
111 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
112 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
113 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
114 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
115 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
116 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
117 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
118 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
126 static void ppin_init(struct cpuinfo_x86 *c)
128 const struct x86_cpu_id *id;
129 unsigned long long val;
130 struct ppin_info *info;
132 id = x86_match_cpu(ppin_cpuids);
137 * Testing the presence of the MSR is not enough. Need to check
138 * that the PPIN_CTL allows reading of the PPIN.
140 info = (struct ppin_info *)id->driver_data;
142 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
145 if ((val & 3UL) == 1UL) {
146 /* PPIN locked in disabled mode */
150 /* If PPIN is disabled, try to enable */
152 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
153 rdmsrl_safe(info->msr_ppin_ctl, &val);
156 /* Is the enable bit set? */
158 c->ppin = __rdmsr(info->msr_ppin);
159 set_cpu_cap(c, info->feature);
164 clear_cpu_cap(c, info->feature);
167 static void default_init(struct cpuinfo_x86 *c)
170 cpu_detect_cache_sizes(c);
172 /* Not much we can do here... */
173 /* Check if at least it has cpuid */
174 if (c->cpuid_level == -1) {
175 /* No cpuid. It must be an ancient CPU */
177 strcpy(c->x86_model_id, "486");
178 else if (c->x86 == 3)
179 strcpy(c->x86_model_id, "386");
184 static const struct cpu_dev default_cpu = {
185 .c_init = default_init,
186 .c_vendor = "Unknown",
187 .c_x86_vendor = X86_VENDOR_UNKNOWN,
190 static const struct cpu_dev *this_cpu = &default_cpu;
192 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
195 * We need valid kernel segments for data and code in long mode too
196 * IRET will check the segment types kkeil 2000/10/28
197 * Also sysret mandates a special GDT layout
199 * TLS descriptors are currently at a different place compared to i386.
200 * Hopefully nobody expects them at a fixed place (Wine?)
202 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
203 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
204 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
205 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
206 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
207 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
209 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
210 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
211 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
212 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
214 * Segments used for calling PnP BIOS have byte granularity.
215 * They code segments and data segments have fixed 64k limits,
216 * the transfer segment sizes are set at run time.
219 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
221 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
223 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
225 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
227 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
229 * The APM segments have byte granularity and their bases
230 * are set at run time. All have 64k limits.
233 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
235 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
237 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
239 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
240 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
243 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
246 static int __init x86_nopcid_setup(char *s)
248 /* nopcid doesn't accept parameters */
252 /* do not emit a message if the feature is not present */
253 if (!boot_cpu_has(X86_FEATURE_PCID))
256 setup_clear_cpu_cap(X86_FEATURE_PCID);
257 pr_info("nopcid: PCID feature disabled\n");
260 early_param("nopcid", x86_nopcid_setup);
263 static int __init x86_noinvpcid_setup(char *s)
265 /* noinvpcid doesn't accept parameters */
269 /* do not emit a message if the feature is not present */
270 if (!boot_cpu_has(X86_FEATURE_INVPCID))
273 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
274 pr_info("noinvpcid: INVPCID feature disabled\n");
277 early_param("noinvpcid", x86_noinvpcid_setup);
280 static int cachesize_override = -1;
281 static int disable_x86_serial_nr = 1;
283 static int __init cachesize_setup(char *str)
285 get_option(&str, &cachesize_override);
288 __setup("cachesize=", cachesize_setup);
290 /* Standard macro to see if a specific flag is changeable */
291 static inline int flag_is_changeable_p(u32 flag)
296 * Cyrix and IDT cpus allow disabling of CPUID
297 * so the code below may return different results
298 * when it is executed before and after enabling
299 * the CPUID. Add "volatile" to not allow gcc to
300 * optimize the subsequent calls to this function.
302 asm volatile ("pushfl \n\t"
313 : "=&r" (f1), "=&r" (f2)
316 return ((f1^f2) & flag) != 0;
319 /* Probe for the CPUID instruction */
320 int have_cpuid_p(void)
322 return flag_is_changeable_p(X86_EFLAGS_ID);
325 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
327 unsigned long lo, hi;
329 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
332 /* Disable processor serial number: */
334 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
336 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
338 pr_notice("CPU serial number disabled.\n");
339 clear_cpu_cap(c, X86_FEATURE_PN);
341 /* Disabling the serial number may affect the cpuid level */
342 c->cpuid_level = cpuid_eax(0);
345 static int __init x86_serial_nr_setup(char *s)
347 disable_x86_serial_nr = 0;
350 __setup("serialnumber", x86_serial_nr_setup);
352 static inline int flag_is_changeable_p(u32 flag)
356 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
361 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
363 if (cpu_has(c, X86_FEATURE_SMEP))
364 cr4_set_bits(X86_CR4_SMEP);
367 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
369 unsigned long eflags = native_save_fl();
371 /* This should have been cleared long ago */
372 BUG_ON(eflags & X86_EFLAGS_AC);
374 if (cpu_has(c, X86_FEATURE_SMAP))
375 cr4_set_bits(X86_CR4_SMAP);
378 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
380 /* Check the boot processor, plus build option for UMIP. */
381 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
384 /* Check the current processor's cpuid bits. */
385 if (!cpu_has(c, X86_FEATURE_UMIP))
388 cr4_set_bits(X86_CR4_UMIP);
390 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
396 * Make sure UMIP is disabled in case it was enabled in a
397 * previous boot (e.g., via kexec).
399 cr4_clear_bits(X86_CR4_UMIP);
402 /* These bits should not change their value after CPU init is finished. */
403 static const unsigned long cr4_pinned_mask =
404 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
405 X86_CR4_FSGSBASE | X86_CR4_CET;
406 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
407 static unsigned long cr4_pinned_bits __ro_after_init;
409 void native_write_cr0(unsigned long val)
411 unsigned long bits_missing = 0;
414 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
416 if (static_branch_likely(&cr_pinning)) {
417 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
418 bits_missing = X86_CR0_WP;
422 /* Warn after we've set the missing bits. */
423 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
426 EXPORT_SYMBOL(native_write_cr0);
428 void __no_profile native_write_cr4(unsigned long val)
430 unsigned long bits_changed = 0;
433 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
435 if (static_branch_likely(&cr_pinning)) {
436 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
437 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
438 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
441 /* Warn after we've corrected the changed bits. */
442 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
446 #if IS_MODULE(CONFIG_LKDTM)
447 EXPORT_SYMBOL_GPL(native_write_cr4);
450 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
452 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
454 lockdep_assert_irqs_disabled();
456 newval = (cr4 & ~clear) | set;
458 this_cpu_write(cpu_tlbstate.cr4, newval);
462 EXPORT_SYMBOL(cr4_update_irqsoff);
464 /* Read the CR4 shadow. */
465 unsigned long cr4_read_shadow(void)
467 return this_cpu_read(cpu_tlbstate.cr4);
469 EXPORT_SYMBOL_GPL(cr4_read_shadow);
473 unsigned long cr4 = __read_cr4();
475 if (boot_cpu_has(X86_FEATURE_PCID))
476 cr4 |= X86_CR4_PCIDE;
477 if (static_branch_likely(&cr_pinning))
478 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
482 /* Initialize cr4 shadow for this CPU. */
483 this_cpu_write(cpu_tlbstate.cr4, cr4);
487 * Once CPU feature detection is finished (and boot params have been
488 * parsed), record any of the sensitive CR bits that are set, and
491 static void __init setup_cr_pinning(void)
493 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
494 static_key_enable(&cr_pinning.key);
497 static __init int x86_nofsgsbase_setup(char *arg)
499 /* Require an exact match without trailing characters. */
503 /* Do not emit a message if the feature is not present. */
504 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
507 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
508 pr_info("FSGSBASE disabled via kernel command line\n");
511 __setup("nofsgsbase", x86_nofsgsbase_setup);
514 * Protection Keys are not available in 32-bit mode.
516 static bool pku_disabled;
518 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
520 if (c == &boot_cpu_data) {
521 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
524 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
525 * bit to be set. Enforce it.
527 setup_force_cpu_cap(X86_FEATURE_OSPKE);
529 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
533 cr4_set_bits(X86_CR4_PKE);
534 /* Load the default PKRU value */
535 pkru_write_default();
538 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
539 static __init int setup_disable_pku(char *arg)
542 * Do not clear the X86_FEATURE_PKU bit. All of the
543 * runtime checks are against OSPKE so clearing the
546 * This way, we will see "pku" in cpuinfo, but not
547 * "ospke", which is exactly what we want. It shows
548 * that the CPU has PKU, but the OS has not enabled it.
549 * This happens to be exactly how a system would look
550 * if we disabled the config option.
552 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
556 __setup("nopku", setup_disable_pku);
559 #ifdef CONFIG_X86_KERNEL_IBT
561 __noendbr u64 ibt_save(bool disable)
565 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
566 rdmsrl(MSR_IA32_S_CET, msr);
568 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
574 __noendbr void ibt_restore(u64 save)
578 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
579 rdmsrl(MSR_IA32_S_CET, msr);
580 msr &= ~CET_ENDBR_EN;
581 msr |= (save & CET_ENDBR_EN);
582 wrmsrl(MSR_IA32_S_CET, msr);
588 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
590 bool user_shstk, kernel_ibt;
592 if (!IS_ENABLED(CONFIG_X86_CET))
595 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
596 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
597 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
599 if (!kernel_ibt && !user_shstk)
603 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
606 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
608 wrmsrl(MSR_IA32_S_CET, 0);
610 cr4_set_bits(X86_CR4_CET);
612 if (kernel_ibt && ibt_selftest()) {
613 pr_err("IBT selftest: Failed!\n");
614 wrmsrl(MSR_IA32_S_CET, 0);
615 setup_clear_cpu_cap(X86_FEATURE_IBT);
619 __noendbr void cet_disable(void)
621 if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
622 cpu_feature_enabled(X86_FEATURE_SHSTK)))
625 wrmsrl(MSR_IA32_S_CET, 0);
626 wrmsrl(MSR_IA32_U_CET, 0);
630 * Some CPU features depend on higher CPUID levels, which may not always
631 * be available due to CPUID level capping or broken virtualization
632 * software. Add those features to this table to auto-disable them.
634 struct cpuid_dependent_feature {
639 static const struct cpuid_dependent_feature
640 cpuid_dependent_features[] = {
641 { X86_FEATURE_MWAIT, 0x00000005 },
642 { X86_FEATURE_DCA, 0x00000009 },
643 { X86_FEATURE_XSAVE, 0x0000000d },
647 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
649 const struct cpuid_dependent_feature *df;
651 for (df = cpuid_dependent_features; df->feature; df++) {
653 if (!cpu_has(c, df->feature))
656 * Note: cpuid_level is set to -1 if unavailable, but
657 * extended_extended_level is set to 0 if unavailable
658 * and the legitimate extended levels are all negative
659 * when signed; hence the weird messing around with
662 if (!((s32)df->level < 0 ?
663 (u32)df->level > (u32)c->extended_cpuid_level :
664 (s32)df->level > (s32)c->cpuid_level))
667 clear_cpu_cap(c, df->feature);
671 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
672 x86_cap_flag(df->feature), df->level);
677 * Naming convention should be: <Name> [(<Codename>)]
678 * This table only is used unless init_<vendor>() below doesn't set it;
679 * in particular, if CPUID levels 0x80000002..4 are supported, this
683 /* Look up CPU names by table lookup. */
684 static const char *table_lookup_model(struct cpuinfo_x86 *c)
687 const struct legacy_cpu_model_info *info;
689 if (c->x86_model >= 16)
690 return NULL; /* Range check */
695 info = this_cpu->legacy_models;
697 while (info->family) {
698 if (info->family == c->x86)
699 return info->model_names[c->x86_model];
703 return NULL; /* Not found */
706 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
707 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
708 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
711 /* The 32-bit entry code needs to find cpu_entry_area. */
712 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
715 /* Load the original GDT from the per-cpu structure */
716 void load_direct_gdt(int cpu)
718 struct desc_ptr gdt_descr;
720 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
721 gdt_descr.size = GDT_SIZE - 1;
722 load_gdt(&gdt_descr);
724 EXPORT_SYMBOL_GPL(load_direct_gdt);
726 /* Load a fixmap remapping of the per-cpu GDT */
727 void load_fixmap_gdt(int cpu)
729 struct desc_ptr gdt_descr;
731 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
732 gdt_descr.size = GDT_SIZE - 1;
733 load_gdt(&gdt_descr);
735 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
738 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
739 * @cpu: The CPU number for which this is invoked
741 * Invoked during early boot to switch from early GDT and early per CPU to
742 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
743 * switch is implicit by loading the direct GDT. On 64bit this requires
746 void __init switch_gdt_and_percpu_base(int cpu)
748 load_direct_gdt(cpu);
752 * No need to load %gs. It is already correct.
754 * Writing %gs on 64bit would zero GSBASE which would make any per
755 * CPU operation up to the point of the wrmsrl() fault.
757 * Set GSBASE to the new offset. Until the wrmsrl() happens the
758 * early mapping is still valid. That means the GSBASE update will
759 * lose any prior per CPU data which was not copied over in
760 * setup_per_cpu_areas().
762 * This works even with stackprotector enabled because the
763 * per CPU stack canary is 0 in both per CPU areas.
765 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
768 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
769 * it is required to load FS again so that the 'hidden' part is
770 * updated from the new GDT. Up to this point the early per CPU
771 * translation is active. Any content of the early per CPU data
772 * which was not copied over in setup_per_cpu_areas() is lost.
774 loadsegment(fs, __KERNEL_PERCPU);
778 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
780 static void get_model_name(struct cpuinfo_x86 *c)
785 if (c->extended_cpuid_level < 0x80000004)
788 v = (unsigned int *)c->x86_model_id;
789 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
790 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
791 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
792 c->x86_model_id[48] = 0;
794 /* Trim whitespace */
795 p = q = s = &c->x86_model_id[0];
801 /* Note the last non-whitespace index */
811 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
813 unsigned int eax, ebx, ecx, edx;
815 c->x86_max_cores = 1;
816 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
819 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
821 c->x86_max_cores = (eax >> 26) + 1;
824 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
826 unsigned int n, dummy, ebx, ecx, edx, l2size;
828 n = c->extended_cpuid_level;
830 if (n >= 0x80000005) {
831 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
832 c->x86_cache_size = (ecx>>24) + (edx>>24);
834 /* On K8 L1 TLB is inclusive, so don't count it */
839 if (n < 0x80000006) /* Some chips just has a large L1. */
842 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
846 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
848 /* do processor-specific cache resizing */
849 if (this_cpu->legacy_cache_size)
850 l2size = this_cpu->legacy_cache_size(c, l2size);
852 /* Allow user to override all this if necessary. */
853 if (cachesize_override != -1)
854 l2size = cachesize_override;
857 return; /* Again, no L2 cache is possible */
860 c->x86_cache_size = l2size;
863 u16 __read_mostly tlb_lli_4k[NR_INFO];
864 u16 __read_mostly tlb_lli_2m[NR_INFO];
865 u16 __read_mostly tlb_lli_4m[NR_INFO];
866 u16 __read_mostly tlb_lld_4k[NR_INFO];
867 u16 __read_mostly tlb_lld_2m[NR_INFO];
868 u16 __read_mostly tlb_lld_4m[NR_INFO];
869 u16 __read_mostly tlb_lld_1g[NR_INFO];
871 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
873 if (this_cpu->c_detect_tlb)
874 this_cpu->c_detect_tlb(c);
876 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
877 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
878 tlb_lli_4m[ENTRIES]);
880 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
881 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
882 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
885 int detect_ht_early(struct cpuinfo_x86 *c)
888 u32 eax, ebx, ecx, edx;
890 if (!cpu_has(c, X86_FEATURE_HT))
893 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
896 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
899 cpuid(1, &eax, &ebx, &ecx, &edx);
901 smp_num_siblings = (ebx & 0xff0000) >> 16;
902 if (smp_num_siblings == 1)
903 pr_info_once("CPU0: Hyper-Threading is disabled\n");
908 void detect_ht(struct cpuinfo_x86 *c)
911 int index_msb, core_bits;
913 if (detect_ht_early(c) < 0)
916 index_msb = get_count_order(smp_num_siblings);
917 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
919 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
921 index_msb = get_count_order(smp_num_siblings);
923 core_bits = get_count_order(c->x86_max_cores);
925 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
926 ((1 << core_bits) - 1);
930 static void get_cpu_vendor(struct cpuinfo_x86 *c)
932 char *v = c->x86_vendor_id;
935 for (i = 0; i < X86_VENDOR_NUM; i++) {
939 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
940 (cpu_devs[i]->c_ident[1] &&
941 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
943 this_cpu = cpu_devs[i];
944 c->x86_vendor = this_cpu->c_x86_vendor;
949 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
950 "CPU: Your system may be unstable.\n", v);
952 c->x86_vendor = X86_VENDOR_UNKNOWN;
953 this_cpu = &default_cpu;
956 void cpu_detect(struct cpuinfo_x86 *c)
958 /* Get vendor name */
959 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
960 (unsigned int *)&c->x86_vendor_id[0],
961 (unsigned int *)&c->x86_vendor_id[8],
962 (unsigned int *)&c->x86_vendor_id[4]);
965 /* Intel-defined flags: level 0x00000001 */
966 if (c->cpuid_level >= 0x00000001) {
967 u32 junk, tfms, cap0, misc;
969 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
970 c->x86 = x86_family(tfms);
971 c->x86_model = x86_model(tfms);
972 c->x86_stepping = x86_stepping(tfms);
974 if (cap0 & (1<<19)) {
975 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
976 c->x86_cache_alignment = c->x86_clflush_size;
981 static void apply_forced_caps(struct cpuinfo_x86 *c)
985 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
986 c->x86_capability[i] &= ~cpu_caps_cleared[i];
987 c->x86_capability[i] |= cpu_caps_set[i];
991 static void init_speculation_control(struct cpuinfo_x86 *c)
994 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
995 * and they also have a different bit for STIBP support. Also,
996 * a hypervisor might have set the individual AMD bits even on
997 * Intel CPUs, for finer-grained selection of what's available.
999 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
1000 set_cpu_cap(c, X86_FEATURE_IBRS);
1001 set_cpu_cap(c, X86_FEATURE_IBPB);
1002 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1005 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
1006 set_cpu_cap(c, X86_FEATURE_STIBP);
1008 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
1009 cpu_has(c, X86_FEATURE_VIRT_SSBD))
1010 set_cpu_cap(c, X86_FEATURE_SSBD);
1012 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
1013 set_cpu_cap(c, X86_FEATURE_IBRS);
1014 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1017 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
1018 set_cpu_cap(c, X86_FEATURE_IBPB);
1020 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1021 set_cpu_cap(c, X86_FEATURE_STIBP);
1022 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1025 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
1026 set_cpu_cap(c, X86_FEATURE_SSBD);
1027 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1028 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
1032 void get_cpu_cap(struct cpuinfo_x86 *c)
1034 u32 eax, ebx, ecx, edx;
1036 /* Intel-defined flags: level 0x00000001 */
1037 if (c->cpuid_level >= 0x00000001) {
1038 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
1040 c->x86_capability[CPUID_1_ECX] = ecx;
1041 c->x86_capability[CPUID_1_EDX] = edx;
1044 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1045 if (c->cpuid_level >= 0x00000006)
1046 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
1048 /* Additional Intel-defined flags: level 0x00000007 */
1049 if (c->cpuid_level >= 0x00000007) {
1050 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
1051 c->x86_capability[CPUID_7_0_EBX] = ebx;
1052 c->x86_capability[CPUID_7_ECX] = ecx;
1053 c->x86_capability[CPUID_7_EDX] = edx;
1055 /* Check valid sub-leaf index before accessing it */
1057 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
1058 c->x86_capability[CPUID_7_1_EAX] = eax;
1062 /* Extended state features: level 0x0000000d */
1063 if (c->cpuid_level >= 0x0000000d) {
1064 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1066 c->x86_capability[CPUID_D_1_EAX] = eax;
1069 /* AMD-defined flags: level 0x80000001 */
1070 eax = cpuid_eax(0x80000000);
1071 c->extended_cpuid_level = eax;
1073 if ((eax & 0xffff0000) == 0x80000000) {
1074 if (eax >= 0x80000001) {
1075 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1077 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1078 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1082 if (c->extended_cpuid_level >= 0x80000007) {
1083 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1085 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1089 if (c->extended_cpuid_level >= 0x80000008) {
1090 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1091 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1094 if (c->extended_cpuid_level >= 0x8000000a)
1095 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1097 if (c->extended_cpuid_level >= 0x8000001f)
1098 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1100 if (c->extended_cpuid_level >= 0x80000021)
1101 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1103 init_scattered_cpuid_features(c);
1104 init_speculation_control(c);
1107 * Clear/Set all flags overridden by options, after probe.
1108 * This needs to happen each time we re-probe, which may happen
1109 * several times during CPU initialization.
1111 apply_forced_caps(c);
1114 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1116 u32 eax, ebx, ecx, edx;
1118 if (c->extended_cpuid_level >= 0x80000008) {
1119 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1121 c->x86_virt_bits = (eax >> 8) & 0xff;
1122 c->x86_phys_bits = eax & 0xff;
1124 #ifdef CONFIG_X86_32
1125 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
1126 c->x86_phys_bits = 36;
1128 c->x86_cache_bits = c->x86_phys_bits;
1131 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1133 #ifdef CONFIG_X86_32
1137 * First of all, decide if this is a 486 or higher
1138 * It's a 486 if we can modify the AC flag
1140 if (flag_is_changeable_p(X86_EFLAGS_AC))
1145 for (i = 0; i < X86_VENDOR_NUM; i++)
1146 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1147 c->x86_vendor_id[0] = 0;
1148 cpu_devs[i]->c_identify(c);
1149 if (c->x86_vendor_id[0]) {
1157 #define NO_SPECULATION BIT(0)
1158 #define NO_MELTDOWN BIT(1)
1159 #define NO_SSB BIT(2)
1160 #define NO_L1TF BIT(3)
1161 #define NO_MDS BIT(4)
1162 #define MSBDS_ONLY BIT(5)
1163 #define NO_SWAPGS BIT(6)
1164 #define NO_ITLB_MULTIHIT BIT(7)
1165 #define NO_SPECTRE_V2 BIT(8)
1166 #define NO_MMIO BIT(9)
1167 #define NO_EIBRS_PBRSB BIT(10)
1169 #define VULNWL(vendor, family, model, whitelist) \
1170 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1172 #define VULNWL_INTEL(model, whitelist) \
1173 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1175 #define VULNWL_AMD(family, whitelist) \
1176 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1178 #define VULNWL_HYGON(family, whitelist) \
1179 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1181 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1182 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1183 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1184 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1185 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1186 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1187 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1189 /* Intel Family 6 */
1190 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1191 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1192 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1193 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1195 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1196 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1197 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1198 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1199 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1201 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1202 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1203 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1204 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1205 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1206 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1208 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1210 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1211 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1213 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1214 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1215 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1218 * Technically, swapgs isn't serializing on AMD (despite it previously
1219 * being documented as such in the APM). But according to AMD, %gs is
1220 * updated non-speculatively, and the issuing of %gs-relative memory
1221 * operands will be blocked until the %gs update completes, which is
1222 * good enough for our purposes.
1225 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
1226 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1227 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1229 /* AMD Family 0xf - 0x12 */
1230 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1231 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1232 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1233 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1235 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1236 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1237 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1239 /* Zhaoxin Family 7 */
1240 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1241 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1245 #define VULNBL(vendor, family, model, blacklist) \
1246 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1248 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1249 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1250 INTEL_FAM6_##model, steppings, \
1251 X86_FEATURE_ANY, issues)
1253 #define VULNBL_AMD(family, blacklist) \
1254 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1256 #define VULNBL_HYGON(family, blacklist) \
1257 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1259 #define SRBDS BIT(0)
1260 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1262 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1263 #define MMIO_SBDS BIT(2)
1264 /* CPU is affected by RETbleed, speculating where you would not expect it */
1265 #define RETBLEED BIT(3)
1266 /* CPU is affected by SMT (cross-thread) return predictions */
1267 #define SMT_RSB BIT(4)
1268 /* CPU is affected by SRSO */
1270 /* CPU is affected by GDS */
1273 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1274 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1275 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1276 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1277 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1278 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1279 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1280 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1281 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1282 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1283 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1284 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1285 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1286 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1287 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1288 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1289 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1290 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1291 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1292 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1293 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1294 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1295 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1296 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS),
1297 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1298 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1299 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1300 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO),
1301 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1303 VULNBL_AMD(0x15, RETBLEED),
1304 VULNBL_AMD(0x16, RETBLEED),
1305 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1306 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1307 VULNBL_AMD(0x19, SRSO),
1311 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1313 const struct x86_cpu_id *m = x86_match_cpu(table);
1315 return m && !!(m->driver_data & which);
1318 u64 x86_read_arch_cap_msr(void)
1322 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1323 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1328 static bool arch_cap_mmio_immune(u64 ia32_cap)
1330 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1331 ia32_cap & ARCH_CAP_PSDP_NO &&
1332 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1335 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1337 u64 ia32_cap = x86_read_arch_cap_msr();
1339 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1340 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1341 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1342 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1344 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1347 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1349 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1350 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1352 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1353 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1354 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1355 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1358 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1359 * flag and protect from vendor-specific bugs via the whitelist.
1361 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) {
1362 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1363 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1364 !(ia32_cap & ARCH_CAP_PBRSB_NO))
1365 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1368 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1369 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1370 setup_force_cpu_bug(X86_BUG_MDS);
1371 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1372 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1375 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1376 setup_force_cpu_bug(X86_BUG_SWAPGS);
1379 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1380 * - TSX is supported or
1381 * - TSX_CTRL is present
1383 * TSX_CTRL check is needed for cases when TSX could be disabled before
1384 * the kernel boot e.g. kexec.
1385 * TSX_CTRL check alone is not sufficient for cases when the microcode
1386 * update is not present or running as guest that don't get TSX_CTRL.
1388 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1389 (cpu_has(c, X86_FEATURE_RTM) ||
1390 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1391 setup_force_cpu_bug(X86_BUG_TAA);
1394 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1395 * in the vulnerability blacklist.
1397 * Some of the implications and mitigation of Shared Buffers Data
1398 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1401 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1402 cpu_has(c, X86_FEATURE_RDSEED)) &&
1403 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1404 setup_force_cpu_bug(X86_BUG_SRBDS);
1407 * Processor MMIO Stale Data bug enumeration
1409 * Affected CPU list is generally enough to enumerate the vulnerability,
1410 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1411 * not want the guest to enumerate the bug.
1413 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1414 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1416 if (!arch_cap_mmio_immune(ia32_cap)) {
1417 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1418 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1419 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1420 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1423 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1424 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))
1425 setup_force_cpu_bug(X86_BUG_RETBLEED);
1428 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1429 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1431 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1432 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1433 setup_force_cpu_bug(X86_BUG_SRSO);
1437 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1438 * an affected processor, the VMM may have disabled the use of GATHER by
1439 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1440 * which means that AVX will be disabled.
1442 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) &&
1443 boot_cpu_has(X86_FEATURE_AVX))
1444 setup_force_cpu_bug(X86_BUG_GDS);
1446 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1449 /* Rogue Data Cache Load? No! */
1450 if (ia32_cap & ARCH_CAP_RDCL_NO)
1453 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1455 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1458 setup_force_cpu_bug(X86_BUG_L1TF);
1462 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1463 * unfortunately, that's not true in practice because of early VIA
1464 * chips and (more importantly) broken virtualizers that are not easy
1465 * to detect. In the latter case it doesn't even *fail* reliably, so
1466 * probing for it doesn't even work. Disable it completely on 32-bit
1467 * unless we can find a reliable way to detect all the broken cases.
1468 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1470 static void detect_nopl(void)
1472 #ifdef CONFIG_X86_32
1473 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1475 setup_force_cpu_cap(X86_FEATURE_NOPL);
1480 * We parse cpu parameters early because fpu__init_system() is executed
1481 * before parse_early_param().
1483 static void __init cpu_parse_early_param(void)
1486 char *argptr = arg, *opt;
1487 int arglen, taint = 0;
1489 #ifdef CONFIG_X86_32
1490 if (cmdline_find_option_bool(boot_command_line, "no387"))
1491 #ifdef CONFIG_MATH_EMULATION
1492 setup_clear_cpu_cap(X86_FEATURE_FPU);
1494 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1497 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1498 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1501 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1502 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1504 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1505 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1507 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1508 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1510 if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1511 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1513 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1517 pr_info("Clearing CPUID bits:");
1520 bool found __maybe_unused = false;
1523 opt = strsep(&argptr, ",");
1526 * Handle naked numbers first for feature flags which don't
1529 if (!kstrtouint(opt, 10, &bit)) {
1530 if (bit < NCAPINTS * 32) {
1532 /* empty-string, i.e., ""-defined feature flags */
1533 if (!x86_cap_flags[bit])
1534 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1536 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1538 setup_clear_cpu_cap(bit);
1542 * The assumption is that there are no feature names with only
1543 * numbers in the name thus go to the next argument.
1548 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1549 if (!x86_cap_flag(bit))
1552 if (strcmp(x86_cap_flag(bit), opt))
1555 pr_cont(" %s", opt);
1556 setup_clear_cpu_cap(bit);
1563 pr_cont(" (unknown: %s)", opt);
1568 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1572 * Do minimum CPU detection early.
1573 * Fields really needed: vendor, cpuid_level, family, model, mask,
1575 * The others are not touched to avoid unwanted side effects.
1577 * WARNING: this function is only called on the boot CPU. Don't add code
1578 * here that is supposed to run on all CPUs.
1580 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1582 #ifdef CONFIG_X86_64
1583 c->x86_clflush_size = 64;
1584 c->x86_phys_bits = 36;
1585 c->x86_virt_bits = 48;
1587 c->x86_clflush_size = 32;
1588 c->x86_phys_bits = 32;
1589 c->x86_virt_bits = 32;
1591 c->x86_cache_alignment = c->x86_clflush_size;
1593 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1594 c->extended_cpuid_level = 0;
1596 if (!have_cpuid_p())
1597 identify_cpu_without_cpuid(c);
1599 /* cyrix could have cpuid enabled via c_identify()*/
1600 if (have_cpuid_p()) {
1604 get_cpu_address_sizes(c);
1605 setup_force_cpu_cap(X86_FEATURE_CPUID);
1606 cpu_parse_early_param();
1608 if (this_cpu->c_early_init)
1609 this_cpu->c_early_init(c);
1612 filter_cpuid_features(c, false);
1614 if (this_cpu->c_bsp_init)
1615 this_cpu->c_bsp_init(c);
1617 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1620 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1622 cpu_set_bug_bits(c);
1626 #ifdef CONFIG_X86_32
1628 * Regardless of whether PCID is enumerated, the SDM says
1629 * that it can't be enabled in 32-bit mode.
1631 setup_clear_cpu_cap(X86_FEATURE_PCID);
1635 * Later in the boot process pgtable_l5_enabled() relies on
1636 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1637 * enabled by this point we need to clear the feature bit to avoid
1638 * false-positives at the later stage.
1640 * pgtable_l5_enabled() can be false here for several reasons:
1641 * - 5-level paging is disabled compile-time;
1642 * - it's 32-bit kernel;
1643 * - machine doesn't support 5-level paging;
1644 * - user specified 'no5lvl' in kernel command line.
1646 if (!pgtable_l5_enabled())
1647 setup_clear_cpu_cap(X86_FEATURE_LA57);
1652 void __init early_cpu_init(void)
1654 const struct cpu_dev *const *cdev;
1657 #ifdef CONFIG_PROCESSOR_SELECT
1658 pr_info("KERNEL supported cpus:\n");
1661 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1662 const struct cpu_dev *cpudev = *cdev;
1664 if (count >= X86_VENDOR_NUM)
1666 cpu_devs[count] = cpudev;
1669 #ifdef CONFIG_PROCESSOR_SELECT
1673 for (j = 0; j < 2; j++) {
1674 if (!cpudev->c_ident[j])
1676 pr_info(" %s %s\n", cpudev->c_vendor,
1677 cpudev->c_ident[j]);
1682 early_identify_cpu(&boot_cpu_data);
1685 static bool detect_null_seg_behavior(void)
1688 * Empirically, writing zero to a segment selector on AMD does
1689 * not clear the base, whereas writing zero to a segment
1690 * selector on Intel does clear the base. Intel's behavior
1691 * allows slightly faster context switches in the common case
1692 * where GS is unused by the prev and next threads.
1694 * Since neither vendor documents this anywhere that I can see,
1695 * detect it directly instead of hard-coding the choice by
1698 * I've designated AMD's behavior as the "bug" because it's
1699 * counterintuitive and less friendly.
1702 unsigned long old_base, tmp;
1703 rdmsrl(MSR_FS_BASE, old_base);
1704 wrmsrl(MSR_FS_BASE, 1);
1706 rdmsrl(MSR_FS_BASE, tmp);
1707 wrmsrl(MSR_FS_BASE, old_base);
1711 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1713 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1714 if (!IS_ENABLED(CONFIG_X86_64))
1717 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1721 * CPUID bit above wasn't set. If this kernel is still running
1722 * as a HV guest, then the HV has decided not to advertize
1723 * that CPUID bit for whatever reason. For example, one
1724 * member of the migration pool might be vulnerable. Which
1725 * means, the bug is present: set the BUG flag and return.
1727 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1728 set_cpu_bug(c, X86_BUG_NULL_SEG);
1733 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1734 * 0x18 is the respective family for Hygon.
1736 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1737 detect_null_seg_behavior())
1740 /* All the remaining ones are affected */
1741 set_cpu_bug(c, X86_BUG_NULL_SEG);
1744 static void generic_identify(struct cpuinfo_x86 *c)
1746 c->extended_cpuid_level = 0;
1748 if (!have_cpuid_p())
1749 identify_cpu_without_cpuid(c);
1751 /* cyrix could have cpuid enabled via c_identify()*/
1752 if (!have_cpuid_p())
1761 get_cpu_address_sizes(c);
1763 if (c->cpuid_level >= 0x00000001) {
1764 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1765 #ifdef CONFIG_X86_32
1767 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1769 c->apicid = c->initial_apicid;
1772 c->phys_proc_id = c->initial_apicid;
1775 get_model_name(c); /* Default name */
1778 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1779 * systems that run Linux at CPL > 0 may or may not have the
1780 * issue, but, even if they have the issue, there's absolutely
1781 * nothing we can do about it because we can't use the real IRET
1784 * NB: For the time being, only 32-bit kernels support
1785 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1786 * whether to apply espfix using paravirt hooks. If any
1787 * non-paravirt system ever shows up that does *not* have the
1788 * ESPFIX issue, we can change this.
1790 #ifdef CONFIG_X86_32
1791 set_cpu_bug(c, X86_BUG_ESPFIX);
1796 * Validate that ACPI/mptables have the same information about the
1797 * effective APIC id and update the package map.
1799 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1802 unsigned int apicid, cpu = smp_processor_id();
1804 apicid = apic->cpu_present_to_apicid(cpu);
1806 if (apicid != c->apicid) {
1807 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1808 cpu, apicid, c->initial_apicid);
1810 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1811 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1813 c->logical_proc_id = 0;
1818 * This does the hard work of actually picking apart the CPU stuff...
1820 static void identify_cpu(struct cpuinfo_x86 *c)
1824 c->loops_per_jiffy = loops_per_jiffy;
1825 c->x86_cache_size = 0;
1826 c->x86_vendor = X86_VENDOR_UNKNOWN;
1827 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1828 c->x86_vendor_id[0] = '\0'; /* Unset */
1829 c->x86_model_id[0] = '\0'; /* Unset */
1830 c->x86_max_cores = 1;
1831 c->x86_coreid_bits = 0;
1833 #ifdef CONFIG_X86_64
1834 c->x86_clflush_size = 64;
1835 c->x86_phys_bits = 36;
1836 c->x86_virt_bits = 48;
1838 c->cpuid_level = -1; /* CPUID not detected */
1839 c->x86_clflush_size = 32;
1840 c->x86_phys_bits = 32;
1841 c->x86_virt_bits = 32;
1843 c->x86_cache_alignment = c->x86_clflush_size;
1844 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1845 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1846 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1849 generic_identify(c);
1851 if (this_cpu->c_identify)
1852 this_cpu->c_identify(c);
1854 /* Clear/Set all flags overridden by options, after probe */
1855 apply_forced_caps(c);
1857 #ifdef CONFIG_X86_64
1858 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1862 * Vendor-specific initialization. In this section we
1863 * canonicalize the feature flags, meaning if there are
1864 * features a certain CPU supports which CPUID doesn't
1865 * tell us, CPUID claiming incorrect flags, or other bugs,
1866 * we handle them here.
1868 * At the end of this section, c->x86_capability better
1869 * indicate the features this CPU genuinely supports!
1871 if (this_cpu->c_init)
1872 this_cpu->c_init(c);
1874 /* Disable the PN if appropriate */
1875 squash_the_stupid_serial_number(c);
1877 /* Set up SMEP/SMAP/UMIP */
1882 /* Enable FSGSBASE instructions if available. */
1883 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1884 cr4_set_bits(X86_CR4_FSGSBASE);
1885 elf_hwcap2 |= HWCAP2_FSGSBASE;
1889 * The vendor-specific functions might have changed features.
1890 * Now we do "generic changes."
1893 /* Filter out anything that depends on CPUID levels we don't have */
1894 filter_cpuid_features(c, true);
1896 /* If the model name is still unset, do table lookup. */
1897 if (!c->x86_model_id[0]) {
1899 p = table_lookup_model(c);
1901 strcpy(c->x86_model_id, p);
1903 /* Last resort... */
1904 sprintf(c->x86_model_id, "%02x/%02x",
1905 c->x86, c->x86_model);
1908 #ifdef CONFIG_X86_64
1917 * Clear/Set all flags overridden by options, need do it
1918 * before following smp all cpus cap AND.
1920 apply_forced_caps(c);
1923 * On SMP, boot_cpu_data holds the common feature set between
1924 * all CPUs; so make sure that we indicate which features are
1925 * common between the CPUs. The first time this routine gets
1926 * executed, c == &boot_cpu_data.
1928 if (c != &boot_cpu_data) {
1929 /* AND the already accumulated flags with these */
1930 for (i = 0; i < NCAPINTS; i++)
1931 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1933 /* OR, i.e. replicate the bug flags */
1934 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1935 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1940 /* Init Machine Check Exception if available. */
1943 select_idle_routine(c);
1946 numa_add_cpu(smp_processor_id());
1951 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1952 * on 32-bit kernels:
1954 #ifdef CONFIG_X86_32
1955 void enable_sep_cpu(void)
1957 struct tss_struct *tss;
1960 if (!boot_cpu_has(X86_FEATURE_SEP))
1964 tss = &per_cpu(cpu_tss_rw, cpu);
1967 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1968 * see the big comment in struct x86_hw_tss's definition.
1971 tss->x86_tss.ss1 = __KERNEL_CS;
1972 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1973 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1974 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1980 static __init void identify_boot_cpu(void)
1982 identify_cpu(&boot_cpu_data);
1983 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1984 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1985 #ifdef CONFIG_X86_32
1988 cpu_detect_tlb(&boot_cpu_data);
1995 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1997 BUG_ON(c == &boot_cpu_data);
1999 #ifdef CONFIG_X86_32
2002 validate_apic_and_package_id(c);
2003 x86_spec_ctrl_setup_ap();
2005 if (boot_cpu_has_bug(X86_BUG_GDS))
2011 void print_cpu_info(struct cpuinfo_x86 *c)
2013 const char *vendor = NULL;
2015 if (c->x86_vendor < X86_VENDOR_NUM) {
2016 vendor = this_cpu->c_vendor;
2018 if (c->cpuid_level >= 0)
2019 vendor = c->x86_vendor_id;
2022 if (vendor && !strstr(c->x86_model_id, vendor))
2023 pr_cont("%s ", vendor);
2025 if (c->x86_model_id[0])
2026 pr_cont("%s", c->x86_model_id);
2028 pr_cont("%d86", c->x86);
2030 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
2032 if (c->x86_stepping || c->cpuid_level >= 0)
2033 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
2039 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
2040 * function prevents it from becoming an environment variable for init.
2042 static __init int setup_clearcpuid(char *arg)
2046 __setup("clearcpuid=", setup_clearcpuid);
2048 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2049 .current_task = &init_task,
2050 .preempt_count = INIT_PREEMPT_COUNT,
2051 .top_of_stack = TOP_OF_INIT_STACK,
2053 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2055 #ifdef CONFIG_X86_64
2056 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2057 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2058 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2060 static void wrmsrl_cstar(unsigned long val)
2063 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2064 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2065 * guest. Avoid the pointless write on all Intel CPUs.
2067 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2068 wrmsrl(MSR_CSTAR, val);
2071 /* May not be marked __init: used by software suspend */
2072 void syscall_init(void)
2074 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
2075 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2077 #ifdef CONFIG_IA32_EMULATION
2078 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2080 * This only works on Intel CPUs.
2081 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2082 * This does not cause SYSENTER to jump to the wrong location, because
2083 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2085 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2086 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2087 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2088 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2090 wrmsrl_cstar((unsigned long)ignore_sysret);
2091 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2092 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2093 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2097 * Flags to clear on syscall; clear as much as possible
2098 * to minimize user space-kernel interference.
2100 wrmsrl(MSR_SYSCALL_MASK,
2101 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2102 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2103 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2104 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2105 X86_EFLAGS_AC|X86_EFLAGS_ID);
2108 #else /* CONFIG_X86_64 */
2110 #ifdef CONFIG_STACKPROTECTOR
2111 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2112 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2115 #endif /* CONFIG_X86_64 */
2118 * Clear all 6 debug registers:
2120 static void clear_all_debug_regs(void)
2124 for (i = 0; i < 8; i++) {
2125 /* Ignore db4, db5 */
2126 if ((i == 4) || (i == 5))
2135 * Restore debug regs if using kgdbwait and you have a kernel debugger
2136 * connection established.
2138 static void dbg_restore_debug_regs(void)
2140 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2141 arch_kgdb_ops.correct_hw_break();
2143 #else /* ! CONFIG_KGDB */
2144 #define dbg_restore_debug_regs()
2145 #endif /* ! CONFIG_KGDB */
2147 static inline void setup_getcpu(int cpu)
2149 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2150 struct desc_struct d = { };
2152 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2153 wrmsr(MSR_TSC_AUX, cpudata, 0);
2155 /* Store CPU and node number in limit. */
2157 d.limit1 = cpudata >> 16;
2159 d.type = 5; /* RO data, expand down, accessed */
2160 d.dpl = 3; /* Visible to user code */
2161 d.s = 1; /* Not a system segment */
2162 d.p = 1; /* Present */
2163 d.d = 1; /* 32-bit */
2165 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2168 #ifdef CONFIG_X86_64
2169 static inline void ucode_cpu_init(int cpu) { }
2171 static inline void tss_setup_ist(struct tss_struct *tss)
2173 /* Set up the per-CPU TSS IST stacks */
2174 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2175 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2176 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2177 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2178 /* Only mapped when SEV-ES is active */
2179 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2182 #else /* CONFIG_X86_64 */
2184 static inline void ucode_cpu_init(int cpu)
2186 show_ucode_info_early();
2189 static inline void tss_setup_ist(struct tss_struct *tss) { }
2191 #endif /* !CONFIG_X86_64 */
2193 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2195 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2197 #ifdef CONFIG_X86_IOPL_IOPERM
2198 tss->io_bitmap.prev_max = 0;
2199 tss->io_bitmap.prev_sequence = 0;
2200 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2202 * Invalidate the extra array entry past the end of the all
2203 * permission bitmap as required by the hardware.
2205 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2210 * Setup everything needed to handle exceptions from the IDT, including the IST
2211 * exceptions which use paranoid_entry().
2213 void cpu_init_exception_handling(void)
2215 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2216 int cpu = raw_smp_processor_id();
2218 /* paranoid_entry() gets the CPU number from the GDT */
2221 /* IST vectors need TSS to be set up. */
2223 tss_setup_io_bitmap(tss);
2224 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2228 /* GHCB needs to be setup to handle #VC. */
2231 /* Finally load the IDT */
2236 * cpu_init() initializes state that is per-CPU. Some data is already
2237 * initialized (naturally) in the bootstrap process, such as the GDT. We
2238 * reload it nevertheless, this function acts as a 'CPU state barrier',
2239 * nothing should get across.
2243 struct task_struct *cur = current;
2244 int cpu = raw_smp_processor_id();
2246 ucode_cpu_init(cpu);
2249 if (this_cpu_read(numa_node) == 0 &&
2250 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2251 set_numa_node(early_cpu_to_node(cpu));
2253 pr_debug("Initializing CPU#%d\n", cpu);
2255 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2256 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2257 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2259 if (IS_ENABLED(CONFIG_X86_64)) {
2261 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2264 wrmsrl(MSR_FS_BASE, 0);
2265 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2272 cur->active_mm = &init_mm;
2274 initialize_tlbstate_and_flush();
2275 enter_lazy_tlb(&init_mm, cur);
2278 * sp0 points to the entry trampoline stack regardless of what task
2281 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2283 load_mm_ldt(&init_mm);
2285 clear_all_debug_regs();
2286 dbg_restore_debug_regs();
2288 doublefault_init_cpu_tss();
2293 load_fixmap_gdt(cpu);
2296 #ifdef CONFIG_MICROCODE_LATE_LOADING
2298 * store_cpu_caps() - Store a snapshot of CPU capabilities
2299 * @curr_info: Pointer where to store it
2303 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2305 /* Reload CPUID max function as it might've changed. */
2306 curr_info->cpuid_level = cpuid_eax(0);
2308 /* Copy all capability leafs and pick up the synthetic ones. */
2309 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2310 sizeof(curr_info->x86_capability));
2312 /* Get the hardware CPUID leafs */
2313 get_cpu_cap(curr_info);
2317 * microcode_check() - Check if any CPU capabilities changed after an update.
2318 * @prev_info: CPU capabilities stored before an update.
2320 * The microcode loader calls this upon late microcode load to recheck features,
2321 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2325 void microcode_check(struct cpuinfo_x86 *prev_info)
2327 struct cpuinfo_x86 curr_info;
2329 perf_check_microcode();
2331 amd_check_microcode();
2333 store_cpu_caps(&curr_info);
2335 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2336 sizeof(prev_info->x86_capability)))
2339 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2340 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2345 * Invoked from core CPU hotplug code after hotplug operations
2347 void arch_smt_update(void)
2349 /* Handle the speculative execution misfeatures */
2350 cpu_bugs_smt_update();
2351 /* Check whether IPI broadcasting can be enabled */
2355 void __init arch_cpu_finalize_init(void)
2357 identify_boot_cpu();
2360 * identify_boot_cpu() initialized SMT support information, let the
2363 cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings);
2365 if (!IS_ENABLED(CONFIG_SMP)) {
2367 print_cpu_info(&boot_cpu_data);
2370 cpu_select_mitigations();
2374 if (IS_ENABLED(CONFIG_X86_32)) {
2376 * Check whether this is a real i386 which is not longer
2377 * supported and fixup the utsname.
2379 if (boot_cpu_data.x86 < 4)
2380 panic("Kernel requires i486+ for 'invlpg' and other features");
2382 init_utsname()->machine[1] =
2383 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2387 * Must be before alternatives because it might set or clear
2393 alternative_instructions();
2395 if (IS_ENABLED(CONFIG_X86_64)) {
2397 * Make sure the first 2MB area is not mapped by huge pages
2398 * There are typically fixed size MTRRs in there and overlapping
2399 * MTRRs into large pages causes slow downs.
2401 * Right now we don't do that with gbpages because there seems
2402 * very little benefit for that case.
2404 if (!direct_gbpages)
2405 set_memory_4k((unsigned long)__va(0), 1);
2407 fpu__init_check_bugs();
2411 * This needs to be called before any devices perform DMA
2412 * operations that might use the SWIOTLB bounce buffers. It will
2413 * mark the bounce buffers as decrypted so that their usage will
2414 * not cause "plain-text" data to be decrypted when accessed. It
2415 * must be called after late_time_init() so that Hyper-V x86/x64
2416 * hypercalls work when the SWIOTLB bounce buffers are decrypted.