1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched/mm.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
50 #include <asm/intel-family.h>
51 #include <asm/cpu_device_id.h>
53 #ifdef CONFIG_X86_LOCAL_APIC
54 #include <asm/uv/uv.h>
59 u32 elf_hwcap2 __read_mostly;
61 /* all of these masks are initialized in setup_cpu_local_masks() */
62 cpumask_var_t cpu_initialized_mask;
63 cpumask_var_t cpu_callout_mask;
64 cpumask_var_t cpu_callin_mask;
66 /* representing cpus for which sibling maps can be computed */
67 cpumask_var_t cpu_sibling_setup_mask;
69 /* correctly size the local cpu masks */
70 void __init setup_cpu_local_masks(void)
72 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
73 alloc_bootmem_cpumask_var(&cpu_callin_mask);
74 alloc_bootmem_cpumask_var(&cpu_callout_mask);
75 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
78 static void default_init(struct cpuinfo_x86 *c)
81 cpu_detect_cache_sizes(c);
83 /* Not much we can do here... */
84 /* Check if at least it has cpuid */
85 if (c->cpuid_level == -1) {
86 /* No cpuid. It must be an ancient CPU */
88 strcpy(c->x86_model_id, "486");
90 strcpy(c->x86_model_id, "386");
95 static const struct cpu_dev default_cpu = {
96 .c_init = default_init,
97 .c_vendor = "Unknown",
98 .c_x86_vendor = X86_VENDOR_UNKNOWN,
101 static const struct cpu_dev *this_cpu = &default_cpu;
103 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
106 * We need valid kernel segments for data and code in long mode too
107 * IRET will check the segment types kkeil 2000/10/28
108 * Also sysret mandates a special GDT layout
110 * TLS descriptors are currently at a different place compared to i386.
111 * Hopefully nobody expects them at a fixed place (Wine?)
113 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
118 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
120 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
121 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
122 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
123 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
125 * Segments used for calling PnP BIOS have byte granularity.
126 * They code segments and data segments have fixed 64k limits,
127 * the transfer segment sizes are set at run time.
130 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
132 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
136 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
138 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
140 * The APM segments have byte granularity and their bases
141 * are set at run time. All have 64k limits.
144 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
146 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
148 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
150 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
151 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
152 GDT_STACK_CANARY_INIT
155 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
157 static int __init x86_mpx_setup(char *s)
159 /* require an exact match without trailing characters */
163 /* do not emit a message if the feature is not present */
164 if (!boot_cpu_has(X86_FEATURE_MPX))
167 setup_clear_cpu_cap(X86_FEATURE_MPX);
168 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
171 __setup("nompx", x86_mpx_setup);
174 static int __init x86_nopcid_setup(char *s)
176 /* nopcid doesn't accept parameters */
180 /* do not emit a message if the feature is not present */
181 if (!boot_cpu_has(X86_FEATURE_PCID))
184 setup_clear_cpu_cap(X86_FEATURE_PCID);
185 pr_info("nopcid: PCID feature disabled\n");
188 early_param("nopcid", x86_nopcid_setup);
191 static int __init x86_noinvpcid_setup(char *s)
193 /* noinvpcid doesn't accept parameters */
197 /* do not emit a message if the feature is not present */
198 if (!boot_cpu_has(X86_FEATURE_INVPCID))
201 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
202 pr_info("noinvpcid: INVPCID feature disabled\n");
205 early_param("noinvpcid", x86_noinvpcid_setup);
208 static int cachesize_override = -1;
209 static int disable_x86_serial_nr = 1;
211 static int __init cachesize_setup(char *str)
213 get_option(&str, &cachesize_override);
216 __setup("cachesize=", cachesize_setup);
218 static int __init x86_sep_setup(char *s)
220 setup_clear_cpu_cap(X86_FEATURE_SEP);
223 __setup("nosep", x86_sep_setup);
225 /* Standard macro to see if a specific flag is changeable */
226 static inline int flag_is_changeable_p(u32 flag)
231 * Cyrix and IDT cpus allow disabling of CPUID
232 * so the code below may return different results
233 * when it is executed before and after enabling
234 * the CPUID. Add "volatile" to not allow gcc to
235 * optimize the subsequent calls to this function.
237 asm volatile ("pushfl \n\t"
248 : "=&r" (f1), "=&r" (f2)
251 return ((f1^f2) & flag) != 0;
254 /* Probe for the CPUID instruction */
255 int have_cpuid_p(void)
257 return flag_is_changeable_p(X86_EFLAGS_ID);
260 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
262 unsigned long lo, hi;
264 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
267 /* Disable processor serial number: */
269 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
271 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
273 pr_notice("CPU serial number disabled.\n");
274 clear_cpu_cap(c, X86_FEATURE_PN);
276 /* Disabling the serial number may affect the cpuid level */
277 c->cpuid_level = cpuid_eax(0);
280 static int __init x86_serial_nr_setup(char *s)
282 disable_x86_serial_nr = 0;
285 __setup("serialnumber", x86_serial_nr_setup);
287 static inline int flag_is_changeable_p(u32 flag)
291 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
296 static __init int setup_disable_smep(char *arg)
298 setup_clear_cpu_cap(X86_FEATURE_SMEP);
299 /* Check for things that depend on SMEP being enabled: */
300 check_mpx_erratum(&boot_cpu_data);
303 __setup("nosmep", setup_disable_smep);
305 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
307 if (cpu_has(c, X86_FEATURE_SMEP))
308 cr4_set_bits(X86_CR4_SMEP);
311 static __init int setup_disable_smap(char *arg)
313 setup_clear_cpu_cap(X86_FEATURE_SMAP);
316 __setup("nosmap", setup_disable_smap);
318 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
320 unsigned long eflags = native_save_fl();
322 /* This should have been cleared long ago */
323 BUG_ON(eflags & X86_EFLAGS_AC);
325 if (cpu_has(c, X86_FEATURE_SMAP)) {
326 #ifdef CONFIG_X86_SMAP
327 cr4_set_bits(X86_CR4_SMAP);
329 cr4_clear_bits(X86_CR4_SMAP);
334 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
336 /* Check the boot processor, plus build option for UMIP. */
337 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
340 /* Check the current processor's cpuid bits. */
341 if (!cpu_has(c, X86_FEATURE_UMIP))
344 cr4_set_bits(X86_CR4_UMIP);
346 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
352 * Make sure UMIP is disabled in case it was enabled in a
353 * previous boot (e.g., via kexec).
355 cr4_clear_bits(X86_CR4_UMIP);
359 * Protection Keys are not available in 32-bit mode.
361 static bool pku_disabled;
363 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
365 /* check the boot processor, plus compile options for PKU: */
366 if (!cpu_feature_enabled(X86_FEATURE_PKU))
368 /* checks the actual processor's cpuid bits: */
369 if (!cpu_has(c, X86_FEATURE_PKU))
374 cr4_set_bits(X86_CR4_PKE);
376 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
377 * cpuid bit to be set. We need to ensure that we
378 * update that bit in this CPU's "cpu_info".
383 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
384 static __init int setup_disable_pku(char *arg)
387 * Do not clear the X86_FEATURE_PKU bit. All of the
388 * runtime checks are against OSPKE so clearing the
391 * This way, we will see "pku" in cpuinfo, but not
392 * "ospke", which is exactly what we want. It shows
393 * that the CPU has PKU, but the OS has not enabled it.
394 * This happens to be exactly how a system would look
395 * if we disabled the config option.
397 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
401 __setup("nopku", setup_disable_pku);
402 #endif /* CONFIG_X86_64 */
405 * Some CPU features depend on higher CPUID levels, which may not always
406 * be available due to CPUID level capping or broken virtualization
407 * software. Add those features to this table to auto-disable them.
409 struct cpuid_dependent_feature {
414 static const struct cpuid_dependent_feature
415 cpuid_dependent_features[] = {
416 { X86_FEATURE_MWAIT, 0x00000005 },
417 { X86_FEATURE_DCA, 0x00000009 },
418 { X86_FEATURE_XSAVE, 0x0000000d },
422 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
424 const struct cpuid_dependent_feature *df;
426 for (df = cpuid_dependent_features; df->feature; df++) {
428 if (!cpu_has(c, df->feature))
431 * Note: cpuid_level is set to -1 if unavailable, but
432 * extended_extended_level is set to 0 if unavailable
433 * and the legitimate extended levels are all negative
434 * when signed; hence the weird messing around with
437 if (!((s32)df->level < 0 ?
438 (u32)df->level > (u32)c->extended_cpuid_level :
439 (s32)df->level > (s32)c->cpuid_level))
442 clear_cpu_cap(c, df->feature);
446 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
447 x86_cap_flag(df->feature), df->level);
452 * Naming convention should be: <Name> [(<Codename>)]
453 * This table only is used unless init_<vendor>() below doesn't set it;
454 * in particular, if CPUID levels 0x80000002..4 are supported, this
458 /* Look up CPU names by table lookup. */
459 static const char *table_lookup_model(struct cpuinfo_x86 *c)
462 const struct legacy_cpu_model_info *info;
464 if (c->x86_model >= 16)
465 return NULL; /* Range check */
470 info = this_cpu->legacy_models;
472 while (info->family) {
473 if (info->family == c->x86)
474 return info->model_names[c->x86_model];
478 return NULL; /* Not found */
481 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
482 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
484 void load_percpu_segment(int cpu)
487 loadsegment(fs, __KERNEL_PERCPU);
489 __loadsegment_simple(gs, 0);
490 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
492 load_stack_canary_segment();
496 /* The 32-bit entry code needs to find cpu_entry_area. */
497 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
502 * Special IST stacks which the CPU switches to when it calls
503 * an IST-marked descriptor entry. Up to 7 stacks (hardware
504 * limit), all of them are 4K, except the debug stack which
507 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
508 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
509 [DEBUG_STACK - 1] = DEBUG_STKSZ
513 /* Load the original GDT from the per-cpu structure */
514 void load_direct_gdt(int cpu)
516 struct desc_ptr gdt_descr;
518 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
519 gdt_descr.size = GDT_SIZE - 1;
520 load_gdt(&gdt_descr);
522 EXPORT_SYMBOL_GPL(load_direct_gdt);
524 /* Load a fixmap remapping of the per-cpu GDT */
525 void load_fixmap_gdt(int cpu)
527 struct desc_ptr gdt_descr;
529 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
530 gdt_descr.size = GDT_SIZE - 1;
531 load_gdt(&gdt_descr);
533 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
536 * Current gdt points %fs at the "master" per-cpu area: after this,
537 * it's on the real one.
539 void switch_to_new_gdt(int cpu)
541 /* Load the original GDT */
542 load_direct_gdt(cpu);
543 /* Reload the per-cpu base */
544 load_percpu_segment(cpu);
547 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
549 static void get_model_name(struct cpuinfo_x86 *c)
554 if (c->extended_cpuid_level < 0x80000004)
557 v = (unsigned int *)c->x86_model_id;
558 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
559 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
560 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
561 c->x86_model_id[48] = 0;
563 /* Trim whitespace */
564 p = q = s = &c->x86_model_id[0];
570 /* Note the last non-whitespace index */
580 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
582 unsigned int n, dummy, ebx, ecx, edx, l2size;
584 n = c->extended_cpuid_level;
586 if (n >= 0x80000005) {
587 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
588 c->x86_cache_size = (ecx>>24) + (edx>>24);
590 /* On K8 L1 TLB is inclusive, so don't count it */
595 if (n < 0x80000006) /* Some chips just has a large L1. */
598 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
602 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
604 /* do processor-specific cache resizing */
605 if (this_cpu->legacy_cache_size)
606 l2size = this_cpu->legacy_cache_size(c, l2size);
608 /* Allow user to override all this if necessary. */
609 if (cachesize_override != -1)
610 l2size = cachesize_override;
613 return; /* Again, no L2 cache is possible */
616 c->x86_cache_size = l2size;
619 u16 __read_mostly tlb_lli_4k[NR_INFO];
620 u16 __read_mostly tlb_lli_2m[NR_INFO];
621 u16 __read_mostly tlb_lli_4m[NR_INFO];
622 u16 __read_mostly tlb_lld_4k[NR_INFO];
623 u16 __read_mostly tlb_lld_2m[NR_INFO];
624 u16 __read_mostly tlb_lld_4m[NR_INFO];
625 u16 __read_mostly tlb_lld_1g[NR_INFO];
627 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
629 if (this_cpu->c_detect_tlb)
630 this_cpu->c_detect_tlb(c);
632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
633 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
634 tlb_lli_4m[ENTRIES]);
636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
637 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
638 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
641 void detect_ht(struct cpuinfo_x86 *c)
644 u32 eax, ebx, ecx, edx;
645 int index_msb, core_bits;
648 if (!cpu_has(c, X86_FEATURE_HT))
651 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
654 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
657 cpuid(1, &eax, &ebx, &ecx, &edx);
659 smp_num_siblings = (ebx & 0xff0000) >> 16;
661 if (smp_num_siblings == 1) {
662 pr_info_once("CPU0: Hyper-Threading is disabled\n");
666 if (smp_num_siblings <= 1)
669 index_msb = get_count_order(smp_num_siblings);
670 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
672 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
674 index_msb = get_count_order(smp_num_siblings);
676 core_bits = get_count_order(c->x86_max_cores);
678 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
679 ((1 << core_bits) - 1);
682 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
683 pr_info("CPU: Physical Processor ID: %d\n",
685 pr_info("CPU: Processor Core ID: %d\n",
692 static void get_cpu_vendor(struct cpuinfo_x86 *c)
694 char *v = c->x86_vendor_id;
697 for (i = 0; i < X86_VENDOR_NUM; i++) {
701 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
702 (cpu_devs[i]->c_ident[1] &&
703 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
705 this_cpu = cpu_devs[i];
706 c->x86_vendor = this_cpu->c_x86_vendor;
711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
712 "CPU: Your system may be unstable.\n", v);
714 c->x86_vendor = X86_VENDOR_UNKNOWN;
715 this_cpu = &default_cpu;
718 void cpu_detect(struct cpuinfo_x86 *c)
720 /* Get vendor name */
721 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
722 (unsigned int *)&c->x86_vendor_id[0],
723 (unsigned int *)&c->x86_vendor_id[8],
724 (unsigned int *)&c->x86_vendor_id[4]);
727 /* Intel-defined flags: level 0x00000001 */
728 if (c->cpuid_level >= 0x00000001) {
729 u32 junk, tfms, cap0, misc;
731 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
732 c->x86 = x86_family(tfms);
733 c->x86_model = x86_model(tfms);
734 c->x86_stepping = x86_stepping(tfms);
736 if (cap0 & (1<<19)) {
737 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
738 c->x86_cache_alignment = c->x86_clflush_size;
743 static void apply_forced_caps(struct cpuinfo_x86 *c)
747 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
748 c->x86_capability[i] &= ~cpu_caps_cleared[i];
749 c->x86_capability[i] |= cpu_caps_set[i];
753 static void init_speculation_control(struct cpuinfo_x86 *c)
756 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
757 * and they also have a different bit for STIBP support. Also,
758 * a hypervisor might have set the individual AMD bits even on
759 * Intel CPUs, for finer-grained selection of what's available.
761 * We use the AMD bits in 0x8000_0008 EBX as the generic hardware
762 * features, which are visible in /proc/cpuinfo and used by the
763 * kernel. So set those accordingly from the Intel bits.
765 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
766 set_cpu_cap(c, X86_FEATURE_IBRS);
767 set_cpu_cap(c, X86_FEATURE_IBPB);
769 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
770 set_cpu_cap(c, X86_FEATURE_STIBP);
773 void get_cpu_cap(struct cpuinfo_x86 *c)
775 u32 eax, ebx, ecx, edx;
777 /* Intel-defined flags: level 0x00000001 */
778 if (c->cpuid_level >= 0x00000001) {
779 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
781 c->x86_capability[CPUID_1_ECX] = ecx;
782 c->x86_capability[CPUID_1_EDX] = edx;
785 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
786 if (c->cpuid_level >= 0x00000006)
787 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
789 /* Additional Intel-defined flags: level 0x00000007 */
790 if (c->cpuid_level >= 0x00000007) {
791 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
792 c->x86_capability[CPUID_7_0_EBX] = ebx;
793 c->x86_capability[CPUID_7_ECX] = ecx;
794 c->x86_capability[CPUID_7_EDX] = edx;
797 /* Extended state features: level 0x0000000d */
798 if (c->cpuid_level >= 0x0000000d) {
799 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
801 c->x86_capability[CPUID_D_1_EAX] = eax;
804 /* Additional Intel-defined flags: level 0x0000000F */
805 if (c->cpuid_level >= 0x0000000F) {
807 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
808 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
809 c->x86_capability[CPUID_F_0_EDX] = edx;
811 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
812 /* will be overridden if occupancy monitoring exists */
813 c->x86_cache_max_rmid = ebx;
815 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
816 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
817 c->x86_capability[CPUID_F_1_EDX] = edx;
819 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
820 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
821 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
822 c->x86_cache_max_rmid = ecx;
823 c->x86_cache_occ_scale = ebx;
826 c->x86_cache_max_rmid = -1;
827 c->x86_cache_occ_scale = -1;
831 /* AMD-defined flags: level 0x80000001 */
832 eax = cpuid_eax(0x80000000);
833 c->extended_cpuid_level = eax;
835 if ((eax & 0xffff0000) == 0x80000000) {
836 if (eax >= 0x80000001) {
837 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
839 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
840 c->x86_capability[CPUID_8000_0001_EDX] = edx;
844 if (c->extended_cpuid_level >= 0x80000007) {
845 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
847 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
851 if (c->extended_cpuid_level >= 0x80000008) {
852 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
854 c->x86_virt_bits = (eax >> 8) & 0xff;
855 c->x86_phys_bits = eax & 0xff;
856 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
859 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
860 c->x86_phys_bits = 36;
863 if (c->extended_cpuid_level >= 0x8000000a)
864 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
866 init_scattered_cpuid_features(c);
867 init_speculation_control(c);
870 * Clear/Set all flags overridden by options, after probe.
871 * This needs to happen each time we re-probe, which may happen
872 * several times during CPU initialization.
874 apply_forced_caps(c);
877 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
883 * First of all, decide if this is a 486 or higher
884 * It's a 486 if we can modify the AC flag
886 if (flag_is_changeable_p(X86_EFLAGS_AC))
891 for (i = 0; i < X86_VENDOR_NUM; i++)
892 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
893 c->x86_vendor_id[0] = 0;
894 cpu_devs[i]->c_identify(c);
895 if (c->x86_vendor_id[0]) {
903 static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
904 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY },
905 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY },
906 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY },
907 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY },
908 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY },
909 { X86_VENDOR_CENTAUR, 5 },
910 { X86_VENDOR_INTEL, 5 },
911 { X86_VENDOR_NSC, 5 },
912 { X86_VENDOR_ANY, 4 },
916 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
921 static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c)
925 if (x86_match_cpu(cpu_no_meltdown))
928 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
929 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
931 /* Rogue Data Cache Load? No! */
932 if (ia32_cap & ARCH_CAP_RDCL_NO)
939 * Do minimum CPU detection early.
940 * Fields really needed: vendor, cpuid_level, family, model, mask,
942 * The others are not touched to avoid unwanted side effects.
944 * WARNING: this function is only called on the boot CPU. Don't add code
945 * here that is supposed to run on all CPUs.
947 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
950 c->x86_clflush_size = 64;
951 c->x86_phys_bits = 36;
952 c->x86_virt_bits = 48;
954 c->x86_clflush_size = 32;
955 c->x86_phys_bits = 32;
956 c->x86_virt_bits = 32;
958 c->x86_cache_alignment = c->x86_clflush_size;
960 memset(&c->x86_capability, 0, sizeof c->x86_capability);
961 c->extended_cpuid_level = 0;
963 /* cyrix could have cpuid enabled via c_identify()*/
964 if (have_cpuid_p()) {
968 setup_force_cpu_cap(X86_FEATURE_CPUID);
970 if (this_cpu->c_early_init)
971 this_cpu->c_early_init(c);
974 filter_cpuid_features(c, false);
976 if (this_cpu->c_bsp_init)
977 this_cpu->c_bsp_init(c);
979 identify_cpu_without_cpuid(c);
980 setup_clear_cpu_cap(X86_FEATURE_CPUID);
983 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
985 if (!x86_match_cpu(cpu_no_speculation)) {
986 if (cpu_vulnerable_to_meltdown(c))
987 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
988 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
989 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
996 * Regardless of whether PCID is enumerated, the SDM says
997 * that it can't be enabled in 32-bit mode.
999 setup_clear_cpu_cap(X86_FEATURE_PCID);
1003 void __init early_cpu_init(void)
1005 const struct cpu_dev *const *cdev;
1008 #ifdef CONFIG_PROCESSOR_SELECT
1009 pr_info("KERNEL supported cpus:\n");
1012 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1013 const struct cpu_dev *cpudev = *cdev;
1015 if (count >= X86_VENDOR_NUM)
1017 cpu_devs[count] = cpudev;
1020 #ifdef CONFIG_PROCESSOR_SELECT
1024 for (j = 0; j < 2; j++) {
1025 if (!cpudev->c_ident[j])
1027 pr_info(" %s %s\n", cpudev->c_vendor,
1028 cpudev->c_ident[j]);
1033 early_identify_cpu(&boot_cpu_data);
1037 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1038 * unfortunately, that's not true in practice because of early VIA
1039 * chips and (more importantly) broken virtualizers that are not easy
1040 * to detect. In the latter case it doesn't even *fail* reliably, so
1041 * probing for it doesn't even work. Disable it completely on 32-bit
1042 * unless we can find a reliable way to detect all the broken cases.
1043 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1045 static void detect_nopl(struct cpuinfo_x86 *c)
1047 #ifdef CONFIG_X86_32
1048 clear_cpu_cap(c, X86_FEATURE_NOPL);
1050 set_cpu_cap(c, X86_FEATURE_NOPL);
1054 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1056 #ifdef CONFIG_X86_64
1058 * Empirically, writing zero to a segment selector on AMD does
1059 * not clear the base, whereas writing zero to a segment
1060 * selector on Intel does clear the base. Intel's behavior
1061 * allows slightly faster context switches in the common case
1062 * where GS is unused by the prev and next threads.
1064 * Since neither vendor documents this anywhere that I can see,
1065 * detect it directly instead of hardcoding the choice by
1068 * I've designated AMD's behavior as the "bug" because it's
1069 * counterintuitive and less friendly.
1072 unsigned long old_base, tmp;
1073 rdmsrl(MSR_FS_BASE, old_base);
1074 wrmsrl(MSR_FS_BASE, 1);
1076 rdmsrl(MSR_FS_BASE, tmp);
1078 set_cpu_bug(c, X86_BUG_NULL_SEG);
1079 wrmsrl(MSR_FS_BASE, old_base);
1083 static void generic_identify(struct cpuinfo_x86 *c)
1085 c->extended_cpuid_level = 0;
1087 if (!have_cpuid_p())
1088 identify_cpu_without_cpuid(c);
1090 /* cyrix could have cpuid enabled via c_identify()*/
1091 if (!have_cpuid_p())
1100 if (c->cpuid_level >= 0x00000001) {
1101 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1102 #ifdef CONFIG_X86_32
1104 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1106 c->apicid = c->initial_apicid;
1109 c->phys_proc_id = c->initial_apicid;
1112 get_model_name(c); /* Default name */
1116 detect_null_seg_behavior(c);
1119 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1120 * systems that run Linux at CPL > 0 may or may not have the
1121 * issue, but, even if they have the issue, there's absolutely
1122 * nothing we can do about it because we can't use the real IRET
1125 * NB: For the time being, only 32-bit kernels support
1126 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1127 * whether to apply espfix using paravirt hooks. If any
1128 * non-paravirt system ever shows up that does *not* have the
1129 * ESPFIX issue, we can change this.
1131 #ifdef CONFIG_X86_32
1132 # ifdef CONFIG_PARAVIRT
1134 extern void native_iret(void);
1135 if (pv_cpu_ops.iret == native_iret)
1136 set_cpu_bug(c, X86_BUG_ESPFIX);
1139 set_cpu_bug(c, X86_BUG_ESPFIX);
1144 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1147 * The heavy lifting of max_rmid and cache_occ_scale are handled
1148 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1149 * in case CQM bits really aren't there in this CPU.
1151 if (c != &boot_cpu_data) {
1152 boot_cpu_data.x86_cache_max_rmid =
1153 min(boot_cpu_data.x86_cache_max_rmid,
1154 c->x86_cache_max_rmid);
1159 * Validate that ACPI/mptables have the same information about the
1160 * effective APIC id and update the package map.
1162 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1165 unsigned int apicid, cpu = smp_processor_id();
1167 apicid = apic->cpu_present_to_apicid(cpu);
1169 if (apicid != c->apicid) {
1170 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1171 cpu, apicid, c->initial_apicid);
1173 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1175 c->logical_proc_id = 0;
1180 * This does the hard work of actually picking apart the CPU stuff...
1182 static void identify_cpu(struct cpuinfo_x86 *c)
1186 c->loops_per_jiffy = loops_per_jiffy;
1187 c->x86_cache_size = 0;
1188 c->x86_vendor = X86_VENDOR_UNKNOWN;
1189 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1190 c->x86_vendor_id[0] = '\0'; /* Unset */
1191 c->x86_model_id[0] = '\0'; /* Unset */
1192 c->x86_max_cores = 1;
1193 c->x86_coreid_bits = 0;
1195 #ifdef CONFIG_X86_64
1196 c->x86_clflush_size = 64;
1197 c->x86_phys_bits = 36;
1198 c->x86_virt_bits = 48;
1200 c->cpuid_level = -1; /* CPUID not detected */
1201 c->x86_clflush_size = 32;
1202 c->x86_phys_bits = 32;
1203 c->x86_virt_bits = 32;
1205 c->x86_cache_alignment = c->x86_clflush_size;
1206 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1208 generic_identify(c);
1210 if (this_cpu->c_identify)
1211 this_cpu->c_identify(c);
1213 /* Clear/Set all flags overridden by options, after probe */
1214 apply_forced_caps(c);
1216 #ifdef CONFIG_X86_64
1217 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1221 * Vendor-specific initialization. In this section we
1222 * canonicalize the feature flags, meaning if there are
1223 * features a certain CPU supports which CPUID doesn't
1224 * tell us, CPUID claiming incorrect flags, or other bugs,
1225 * we handle them here.
1227 * At the end of this section, c->x86_capability better
1228 * indicate the features this CPU genuinely supports!
1230 if (this_cpu->c_init)
1231 this_cpu->c_init(c);
1233 /* Disable the PN if appropriate */
1234 squash_the_stupid_serial_number(c);
1236 /* Set up SMEP/SMAP/UMIP */
1242 * The vendor-specific functions might have changed features.
1243 * Now we do "generic changes."
1246 /* Filter out anything that depends on CPUID levels we don't have */
1247 filter_cpuid_features(c, true);
1249 /* If the model name is still unset, do table lookup. */
1250 if (!c->x86_model_id[0]) {
1252 p = table_lookup_model(c);
1254 strcpy(c->x86_model_id, p);
1256 /* Last resort... */
1257 sprintf(c->x86_model_id, "%02x/%02x",
1258 c->x86, c->x86_model);
1261 #ifdef CONFIG_X86_64
1266 x86_init_cache_qos(c);
1270 * Clear/Set all flags overridden by options, need do it
1271 * before following smp all cpus cap AND.
1273 apply_forced_caps(c);
1276 * On SMP, boot_cpu_data holds the common feature set between
1277 * all CPUs; so make sure that we indicate which features are
1278 * common between the CPUs. The first time this routine gets
1279 * executed, c == &boot_cpu_data.
1281 if (c != &boot_cpu_data) {
1282 /* AND the already accumulated flags with these */
1283 for (i = 0; i < NCAPINTS; i++)
1284 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1286 /* OR, i.e. replicate the bug flags */
1287 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1288 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1291 /* Init Machine Check Exception if available. */
1294 select_idle_routine(c);
1297 numa_add_cpu(smp_processor_id());
1302 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1303 * on 32-bit kernels:
1305 #ifdef CONFIG_X86_32
1306 void enable_sep_cpu(void)
1308 struct tss_struct *tss;
1311 if (!boot_cpu_has(X86_FEATURE_SEP))
1315 tss = &per_cpu(cpu_tss_rw, cpu);
1318 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1319 * see the big comment in struct x86_hw_tss's definition.
1322 tss->x86_tss.ss1 = __KERNEL_CS;
1323 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1324 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1325 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1331 void __init identify_boot_cpu(void)
1333 identify_cpu(&boot_cpu_data);
1334 #ifdef CONFIG_X86_32
1338 cpu_detect_tlb(&boot_cpu_data);
1341 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1343 BUG_ON(c == &boot_cpu_data);
1345 #ifdef CONFIG_X86_32
1349 validate_apic_and_package_id(c);
1352 static __init int setup_noclflush(char *arg)
1354 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1355 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1358 __setup("noclflush", setup_noclflush);
1360 void print_cpu_info(struct cpuinfo_x86 *c)
1362 const char *vendor = NULL;
1364 if (c->x86_vendor < X86_VENDOR_NUM) {
1365 vendor = this_cpu->c_vendor;
1367 if (c->cpuid_level >= 0)
1368 vendor = c->x86_vendor_id;
1371 if (vendor && !strstr(c->x86_model_id, vendor))
1372 pr_cont("%s ", vendor);
1374 if (c->x86_model_id[0])
1375 pr_cont("%s", c->x86_model_id);
1377 pr_cont("%d86", c->x86);
1379 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1381 if (c->x86_stepping || c->cpuid_level >= 0)
1382 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1388 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1389 * But we need to keep a dummy __setup around otherwise it would
1390 * show up as an environment variable for init.
1392 static __init int setup_clearcpuid(char *arg)
1396 __setup("clearcpuid=", setup_clearcpuid);
1398 #ifdef CONFIG_X86_64
1399 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1400 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1403 * The following percpu variables are hot. Align current_task to
1404 * cacheline size such that they fall in the same cacheline.
1406 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1408 EXPORT_PER_CPU_SYMBOL(current_task);
1410 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1411 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1413 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1415 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1416 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1418 /* May not be marked __init: used by software suspend */
1419 void syscall_init(void)
1421 extern char _entry_trampoline[];
1422 extern char entry_SYSCALL_64_trampoline[];
1424 int cpu = smp_processor_id();
1425 unsigned long SYSCALL64_entry_trampoline =
1426 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1427 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1429 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1430 if (static_cpu_has(X86_FEATURE_PTI))
1431 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1433 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1435 #ifdef CONFIG_IA32_EMULATION
1436 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1438 * This only works on Intel CPUs.
1439 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1440 * This does not cause SYSENTER to jump to the wrong location, because
1441 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1443 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1444 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
1445 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1447 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1448 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1449 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1450 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1453 /* Flags to clear on syscall */
1454 wrmsrl(MSR_SYSCALL_MASK,
1455 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1456 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1460 * Copies of the original ist values from the tss are only accessed during
1461 * debugging, no special alignment required.
1463 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1465 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1466 DEFINE_PER_CPU(int, debug_stack_usage);
1468 int is_debug_stack(unsigned long addr)
1470 return __this_cpu_read(debug_stack_usage) ||
1471 (addr <= __this_cpu_read(debug_stack_addr) &&
1472 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1474 NOKPROBE_SYMBOL(is_debug_stack);
1476 DEFINE_PER_CPU(u32, debug_idt_ctr);
1478 void debug_stack_set_zero(void)
1480 this_cpu_inc(debug_idt_ctr);
1483 NOKPROBE_SYMBOL(debug_stack_set_zero);
1485 void debug_stack_reset(void)
1487 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1489 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1492 NOKPROBE_SYMBOL(debug_stack_reset);
1494 #else /* CONFIG_X86_64 */
1496 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1497 EXPORT_PER_CPU_SYMBOL(current_task);
1498 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1499 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1502 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1503 * the top of the kernel stack. Use an extra percpu variable to track the
1504 * top of the kernel stack directly.
1506 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1507 (unsigned long)&init_thread_union + THREAD_SIZE;
1508 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1510 #ifdef CONFIG_CC_STACKPROTECTOR
1511 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1514 #endif /* CONFIG_X86_64 */
1517 * Clear all 6 debug registers:
1519 static void clear_all_debug_regs(void)
1523 for (i = 0; i < 8; i++) {
1524 /* Ignore db4, db5 */
1525 if ((i == 4) || (i == 5))
1534 * Restore debug regs if using kgdbwait and you have a kernel debugger
1535 * connection established.
1537 static void dbg_restore_debug_regs(void)
1539 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1540 arch_kgdb_ops.correct_hw_break();
1542 #else /* ! CONFIG_KGDB */
1543 #define dbg_restore_debug_regs()
1544 #endif /* ! CONFIG_KGDB */
1546 static void wait_for_master_cpu(int cpu)
1550 * wait for ACK from master CPU before continuing
1551 * with AP initialization
1553 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1554 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1560 * cpu_init() initializes state that is per-CPU. Some data is already
1561 * initialized (naturally) in the bootstrap process, such as the GDT
1562 * and IDT. We reload them nevertheless, this function acts as a
1563 * 'CPU state barrier', nothing should get across.
1564 * A lot of state is already set up in PDA init for 64 bit
1566 #ifdef CONFIG_X86_64
1570 struct orig_ist *oist;
1571 struct task_struct *me;
1572 struct tss_struct *t;
1574 int cpu = raw_smp_processor_id();
1577 wait_for_master_cpu(cpu);
1580 * Initialize the CR4 shadow before doing anything that could
1588 t = &per_cpu(cpu_tss_rw, cpu);
1589 oist = &per_cpu(orig_ist, cpu);
1592 if (this_cpu_read(numa_node) == 0 &&
1593 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1594 set_numa_node(early_cpu_to_node(cpu));
1599 pr_debug("Initializing CPU#%d\n", cpu);
1601 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1604 * Initialize the per-CPU GDT with the boot GDT,
1605 * and set up the GDT descriptor:
1608 switch_to_new_gdt(cpu);
1613 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1616 wrmsrl(MSR_FS_BASE, 0);
1617 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1624 * set up and load the per-CPU TSS
1626 if (!oist->ist[0]) {
1627 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1629 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1630 estacks += exception_stack_sizes[v];
1631 oist->ist[v] = t->x86_tss.ist[v] =
1632 (unsigned long)estacks;
1633 if (v == DEBUG_STACK-1)
1634 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1638 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1641 * <= is required because the CPU will access up to
1642 * 8 bits beyond the end of the IO permission bitmap.
1644 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1645 t->io_bitmap[i] = ~0UL;
1648 me->active_mm = &init_mm;
1650 initialize_tlbstate_and_flush();
1651 enter_lazy_tlb(&init_mm, me);
1654 * Initialize the TSS. sp0 points to the entry trampoline stack
1655 * regardless of what task is running.
1657 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1659 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1661 load_mm_ldt(&init_mm);
1663 clear_all_debug_regs();
1664 dbg_restore_debug_regs();
1671 load_fixmap_gdt(cpu);
1678 int cpu = smp_processor_id();
1679 struct task_struct *curr = current;
1680 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1682 wait_for_master_cpu(cpu);
1685 * Initialize the CR4 shadow before doing anything that could
1690 show_ucode_info_early();
1692 pr_info("Initializing CPU#%d\n", cpu);
1694 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1695 boot_cpu_has(X86_FEATURE_TSC) ||
1696 boot_cpu_has(X86_FEATURE_DE))
1697 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1700 switch_to_new_gdt(cpu);
1703 * Set up and load the per-CPU TSS and LDT
1706 curr->active_mm = &init_mm;
1708 initialize_tlbstate_and_flush();
1709 enter_lazy_tlb(&init_mm, curr);
1712 * Initialize the TSS. Don't bother initializing sp0, as the initial
1713 * task never enters user mode.
1715 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1718 load_mm_ldt(&init_mm);
1720 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1722 #ifdef CONFIG_DOUBLEFAULT
1723 /* Set up doublefault TSS pointer in the GDT */
1724 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1727 clear_all_debug_regs();
1728 dbg_restore_debug_regs();
1732 load_fixmap_gdt(cpu);
1736 static void bsp_resume(void)
1738 if (this_cpu->c_bsp_resume)
1739 this_cpu->c_bsp_resume(&boot_cpu_data);
1742 static struct syscore_ops cpu_syscore_ops = {
1743 .resume = bsp_resume,
1746 static int __init init_cpu_syscore(void)
1748 register_syscore_ops(&cpu_syscore_ops);
1751 core_initcall(init_cpu_syscore);
1754 * The microcode loader calls this upon late microcode load to recheck features,
1755 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1758 void microcode_check(void)
1760 struct cpuinfo_x86 info;
1762 perf_check_microcode();
1764 /* Reload CPUID max function as it might've changed. */
1765 info.cpuid_level = cpuid_eax(0);
1768 * Copy all capability leafs to pick up the synthetic ones so that
1769 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1770 * get overwritten in get_cpu_cap().
1772 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1776 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1779 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1780 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");