arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/vmx.h>
  26 #include <asm/paravirt.h>
  27 #include <asm/alternative.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/set_memory.h>
  30 #include <asm/intel-family.h>
  31 #include <asm/e820/api.h>
  32 #include <asm/hypervisor.h>
  33
  34 static void __init spectre_v2_select_mitigation(void);
  35 static void __init ssb_select_mitigation(void);
  36 static void __init l1tf_select_mitigation(void);
  37
  38 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  39 u64 x86_spec_ctrl_base;
  40 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  41 static DEFINE_MUTEX(spec_ctrl_mutex);
  42
  43 /*
  44  * The vendor and possibly platform specific bits which can be modified in
  45  * x86_spec_ctrl_base.
  46  */
  47 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  48
  49 /*
  50  * AMD specific MSR info for Speculative Store Bypass control.
  51  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  52  */
  53 u64 __ro_after_init x86_amd_ls_cfg_base;
  54 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  55
  56 void __init check_bugs(void)
  57 {
  58         identify_boot_cpu();
  59
  60         /*
  61          * identify_boot_cpu() initialized SMT support information, let the
  62          * core code know.
  63          */
  64         cpu_smt_check_topology_early();
  65
  66         if (!IS_ENABLED(CONFIG_SMP)) {
  67                 pr_info("CPU: ");
  68                 print_cpu_info(&boot_cpu_data);
  69         }
  70
  71         /*
  72          * Read the SPEC_CTRL MSR to account for reserved bits which may
  73          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  74          * init code as it is not enumerated and depends on the family.
  75          */
  76         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  77                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  78
  79         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  80         if (boot_cpu_has(X86_FEATURE_STIBP))
  81                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  82
  83         /* Select the proper spectre mitigation before patching alternatives */
  84         spectre_v2_select_mitigation();
  85
  86         /*
  87          * Select proper mitigation for any exposure to the Speculative Store
  88          * Bypass vulnerability.
  89          */
  90         ssb_select_mitigation();
  91
  92         l1tf_select_mitigation();
  93
  94 #ifdef CONFIG_X86_32
  95         /*
  96          * Check whether we are able to run this kernel safely on SMP.
  97          *
  98          * - i386 is no longer supported.
  99          * - In order to run on anything without a TSC, we need to be
 100          *   compiled for a i486.
 101          */
 102         if (boot_cpu_data.x86 < 4)
 103                 panic("Kernel requires i486+ for 'invlpg' and other features");
 104
 105         init_utsname()->machine[1] =
 106                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 107         alternative_instructions();
 108
 109         fpu__init_check_bugs();
 110 #else /* CONFIG_X86_64 */
 111         alternative_instructions();
 112
 113         /*
 114          * Make sure the first 2MB area is not mapped by huge pages
 115          * There are typically fixed size MTRRs in there and overlapping
 116          * MTRRs into large pages causes slow downs.
 117          *
 118          * Right now we don't do that with gbpages because there seems
 119          * very little benefit for that case.
 120          */
 121         if (!direct_gbpages)
 122                 set_memory_4k((unsigned long)__va(0), 1);
 123 #endif
 124 }
 125
 126 /* The kernel command line selection */
 127 enum spectre_v2_mitigation_cmd {
 128         SPECTRE_V2_CMD_NONE,
 129         SPECTRE_V2_CMD_AUTO,
 130         SPECTRE_V2_CMD_FORCE,
 131         SPECTRE_V2_CMD_RETPOLINE,
 132         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 133         SPECTRE_V2_CMD_RETPOLINE_AMD,
 134 };
 135
 136 static const char *spectre_v2_strings[] = {
 137         [SPECTRE_V2_NONE]                       = "Vulnerable",
 138         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 139         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 140         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 141         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 142         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 143 };
 144
 145 #undef pr_fmt
 146 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 147
 148 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 149         SPECTRE_V2_NONE;
 150
 151 void
 152 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 153 {
 154         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 155         struct thread_info *ti = current_thread_info();
 156
 157         /* Is MSR_SPEC_CTRL implemented ? */
 158         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 159                 /*
 160                  * Restrict guest_spec_ctrl to supported values. Clear the
 161                  * modifiable bits in the host base value and or the
 162                  * modifiable bits from the guest value.
 163                  */
 164                 guestval = hostval & ~x86_spec_ctrl_mask;
 165                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 166
 167                 /* SSBD controlled in MSR_SPEC_CTRL */
 168                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 169                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 170                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 171
 172                 if (hostval != guestval) {
 173                         msrval = setguest ? guestval : hostval;
 174                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 175                 }
 176         }
 177
 178         /*
 179          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 180          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 181          */
 182         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 183             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 184                 return;
 185
 186         /*
 187          * If the host has SSBD mitigation enabled, force it in the host's
 188          * virtual MSR value. If its not permanently enabled, evaluate
 189          * current's TIF_SSBD thread flag.
 190          */
 191         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 192                 hostval = SPEC_CTRL_SSBD;
 193         else
 194                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 195
 196         /* Sanitize the guest value */
 197         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 198
 199         if (hostval != guestval) {
 200                 unsigned long tif;
 201
 202                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 203                                  ssbd_spec_ctrl_to_tif(hostval);
 204
 205                 speculative_store_bypass_update(tif);
 206         }
 207 }
 208 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 209
 210 static void x86_amd_ssb_disable(void)
 211 {
 212         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 213
 214         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 215                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 216         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 217                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 218 }
 219
 220 #ifdef RETPOLINE
 221 static bool spectre_v2_bad_module;
 222
 223 bool retpoline_module_ok(bool has_retpoline)
 224 {
 225         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 226                 return true;
 227
 228         pr_err("System may be vulnerable to spectre v2\n");
 229         spectre_v2_bad_module = true;
 230         return false;
 231 }
 232
 233 static inline const char *spectre_v2_module_string(void)
 234 {
 235         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 236 }
 237 #else
 238 static inline const char *spectre_v2_module_string(void) { return ""; }
 239 #endif
 240
 241 static void __init spec2_print_if_insecure(const char *reason)
 242 {
 243         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 244                 pr_info("%s selected on command line.\n", reason);
 245 }
 246
 247 static void __init spec2_print_if_secure(const char *reason)
 248 {
 249         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 250                 pr_info("%s selected on command line.\n", reason);
 251 }
 252
 253 static inline bool retp_compiler(void)
 254 {
 255         return __is_defined(RETPOLINE);
 256 }
 257
 258 static inline bool match_option(const char *arg, int arglen, const char *opt)
 259 {
 260         int len = strlen(opt);
 261
 262         return len == arglen && !strncmp(arg, opt, len);
 263 }
 264
 265 static const struct {
 266         const char *option;
 267         enum spectre_v2_mitigation_cmd cmd;
 268         bool secure;
 269 } mitigation_options[] = {
 270         { "off",               SPECTRE_V2_CMD_NONE,              false },
 271         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 272         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 273         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 274         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 275         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 276 };
 277
 278 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 279 {
 280         char arg[20];
 281         int ret, i;
 282         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 283
 284         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 285                 return SPECTRE_V2_CMD_NONE;
 286         else {
 287                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 288                 if (ret < 0)
 289                         return SPECTRE_V2_CMD_AUTO;
 290
 291                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 292                         if (!match_option(arg, ret, mitigation_options[i].option))
 293                                 continue;
 294                         cmd = mitigation_options[i].cmd;
 295                         break;
 296                 }
 297
 298                 if (i >= ARRAY_SIZE(mitigation_options)) {
 299                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 300                         return SPECTRE_V2_CMD_AUTO;
 301                 }
 302         }
 303
 304         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 305              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 306              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 307             !IS_ENABLED(CONFIG_RETPOLINE)) {
 308                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 309                 return SPECTRE_V2_CMD_AUTO;
 310         }
 311
 312         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 313             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 314                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 315                 return SPECTRE_V2_CMD_AUTO;
 316         }
 317
 318         if (mitigation_options[i].secure)
 319                 spec2_print_if_secure(mitigation_options[i].option);
 320         else
 321                 spec2_print_if_insecure(mitigation_options[i].option);
 322
 323         return cmd;
 324 }
 325
 326 static bool stibp_needed(void)
 327 {
 328         if (spectre_v2_enabled == SPECTRE_V2_NONE)
 329                 return false;
 330
 331         if (!boot_cpu_has(X86_FEATURE_STIBP))
 332                 return false;
 333
 334         return true;
 335 }
 336
 337 static void update_stibp_msr(void *info)
 338 {
 339         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 340 }
 341
 342 void arch_smt_update(void)
 343 {
 344         u64 mask;
 345
 346         if (!stibp_needed())
 347                 return;
 348
 349         mutex_lock(&spec_ctrl_mutex);
 350         mask = x86_spec_ctrl_base;
 351         if (cpu_smt_control == CPU_SMT_ENABLED)
 352                 mask |= SPEC_CTRL_STIBP;
 353         else
 354                 mask &= ~SPEC_CTRL_STIBP;
 355
 356         if (mask != x86_spec_ctrl_base) {
 357                 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
 358                                 cpu_smt_control == CPU_SMT_ENABLED ?
 359                                 "Enabling" : "Disabling");
 360                 x86_spec_ctrl_base = mask;
 361                 on_each_cpu(update_stibp_msr, NULL, 1);
 362         }
 363         mutex_unlock(&spec_ctrl_mutex);
 364 }
 365
 366 static void __init spectre_v2_select_mitigation(void)
 367 {
 368         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 369         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 370
 371         /*
 372          * If the CPU is not affected and the command line mode is NONE or AUTO
 373          * then nothing to do.
 374          */
 375         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 376             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 377                 return;
 378
 379         switch (cmd) {
 380         case SPECTRE_V2_CMD_NONE:
 381                 return;
 382
 383         case SPECTRE_V2_CMD_FORCE:
 384         case SPECTRE_V2_CMD_AUTO:
 385                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 386                         mode = SPECTRE_V2_IBRS_ENHANCED;
 387                         /* Force it so VMEXIT will restore correctly */
 388                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 389                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 390                         goto specv2_set_mode;
 391                 }
 392                 if (IS_ENABLED(CONFIG_RETPOLINE))
 393                         goto retpoline_auto;
 394                 break;
 395         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 396                 if (IS_ENABLED(CONFIG_RETPOLINE))
 397                         goto retpoline_amd;
 398                 break;
 399         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 400                 if (IS_ENABLED(CONFIG_RETPOLINE))
 401                         goto retpoline_generic;
 402                 break;
 403         case SPECTRE_V2_CMD_RETPOLINE:
 404                 if (IS_ENABLED(CONFIG_RETPOLINE))
 405                         goto retpoline_auto;
 406                 break;
 407         }
 408         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 409         return;
 410
 411 retpoline_auto:
 412         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 413         retpoline_amd:
 414                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 415                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 416                         goto retpoline_generic;
 417                 }
 418                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 419                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 420                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 421                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 422         } else {
 423         retpoline_generic:
 424                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 425                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 426                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 427         }
 428
 429 specv2_set_mode:
 430         spectre_v2_enabled = mode;
 431         pr_info("%s\n", spectre_v2_strings[mode]);
 432
 433         /*
 434          * If spectre v2 protection has been enabled, unconditionally fill
 435          * RSB during a context switch; this protects against two independent
 436          * issues:
 437          *
 438          *      - RSB underflow (and switch to BTB) on Skylake+
 439          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 440          */
 441         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 442         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 443
 444         /* Initialize Indirect Branch Prediction Barrier if supported */
 445         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 446                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 447                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 448         }
 449
 450         /*
 451          * Retpoline means the kernel is safe because it has no indirect
 452          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 453          * speculation around firmware calls only when Enhanced IBRS isn't
 454          * supported.
 455          *
 456          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 457          * the user might select retpoline on the kernel command line and if
 458          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 459          * enable IBRS around firmware calls.
 460          */
 461         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 462                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 463                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 464         }
 465
 466         /* Enable STIBP if appropriate */
 467         arch_smt_update();
 468 }
 469
 470 #undef pr_fmt
 471 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 472
 473 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 474
 475 /* The kernel command line selection */
 476 enum ssb_mitigation_cmd {
 477         SPEC_STORE_BYPASS_CMD_NONE,
 478         SPEC_STORE_BYPASS_CMD_AUTO,
 479         SPEC_STORE_BYPASS_CMD_ON,
 480         SPEC_STORE_BYPASS_CMD_PRCTL,
 481         SPEC_STORE_BYPASS_CMD_SECCOMP,
 482 };
 483
 484 static const char *ssb_strings[] = {
 485         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 486         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 487         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 488         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 489 };
 490
 491 static const struct {
 492         const char *option;
 493         enum ssb_mitigation_cmd cmd;
 494 } ssb_mitigation_options[] = {
 495         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 496         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 497         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 498         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 499         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 500 };
 501
 502 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 503 {
 504         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 505         char arg[20];
 506         int ret, i;
 507
 508         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 509                 return SPEC_STORE_BYPASS_CMD_NONE;
 510         } else {
 511                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 512                                           arg, sizeof(arg));
 513                 if (ret < 0)
 514                         return SPEC_STORE_BYPASS_CMD_AUTO;
 515
 516                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 517                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 518                                 continue;
 519
 520                         cmd = ssb_mitigation_options[i].cmd;
 521                         break;
 522                 }
 523
 524                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 525                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 526                         return SPEC_STORE_BYPASS_CMD_AUTO;
 527                 }
 528         }
 529
 530         return cmd;
 531 }
 532
 533 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 534 {
 535         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 536         enum ssb_mitigation_cmd cmd;
 537
 538         if (!boot_cpu_has(X86_FEATURE_SSBD))
 539                 return mode;
 540
 541         cmd = ssb_parse_cmdline();
 542         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 543             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 544              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 545                 return mode;
 546
 547         switch (cmd) {
 548         case SPEC_STORE_BYPASS_CMD_AUTO:
 549         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 550                 /*
 551                  * Choose prctl+seccomp as the default mode if seccomp is
 552                  * enabled.
 553                  */
 554                 if (IS_ENABLED(CONFIG_SECCOMP))
 555                         mode = SPEC_STORE_BYPASS_SECCOMP;
 556                 else
 557                         mode = SPEC_STORE_BYPASS_PRCTL;
 558                 break;
 559         case SPEC_STORE_BYPASS_CMD_ON:
 560                 mode = SPEC_STORE_BYPASS_DISABLE;
 561                 break;
 562         case SPEC_STORE_BYPASS_CMD_PRCTL:
 563                 mode = SPEC_STORE_BYPASS_PRCTL;
 564                 break;
 565         case SPEC_STORE_BYPASS_CMD_NONE:
 566                 break;
 567         }
 568
 569         /*
 570          * We have three CPU feature flags that are in play here:
 571          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 572          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 573          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 574          */
 575         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 576                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 577                 /*
 578                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 579                  * use a completely different MSR and bit dependent on family.
 580                  */
 581                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
 582                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 583                         x86_amd_ssb_disable();
 584                 } else {
 585                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 586                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 587                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 588                 }
 589         }
 590
 591         return mode;
 592 }
 593
 594 static void ssb_select_mitigation(void)
 595 {
 596         ssb_mode = __ssb_select_mitigation();
 597
 598         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 599                 pr_info("%s\n", ssb_strings[ssb_mode]);
 600 }
 601
 602 #undef pr_fmt
 603 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 604
 605 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 606 {
 607         bool update;
 608
 609         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 610             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 611                 return -ENXIO;
 612
 613         switch (ctrl) {
 614         case PR_SPEC_ENABLE:
 615                 /* If speculation is force disabled, enable is not allowed */
 616                 if (task_spec_ssb_force_disable(task))
 617                         return -EPERM;
 618                 task_clear_spec_ssb_disable(task);
 619                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 620                 break;
 621         case PR_SPEC_DISABLE:
 622                 task_set_spec_ssb_disable(task);
 623                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 624                 break;
 625         case PR_SPEC_FORCE_DISABLE:
 626                 task_set_spec_ssb_disable(task);
 627                 task_set_spec_ssb_force_disable(task);
 628                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 629                 break;
 630         default:
 631                 return -ERANGE;
 632         }
 633
 634         /*
 635          * If being set on non-current task, delay setting the CPU
 636          * mitigation until it is next scheduled.
 637          */
 638         if (task == current && update)
 639                 speculative_store_bypass_update_current();
 640
 641         return 0;
 642 }
 643
 644 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 645                              unsigned long ctrl)
 646 {
 647         switch (which) {
 648         case PR_SPEC_STORE_BYPASS:
 649                 return ssb_prctl_set(task, ctrl);
 650         default:
 651                 return -ENODEV;
 652         }
 653 }
 654
 655 #ifdef CONFIG_SECCOMP
 656 void arch_seccomp_spec_mitigate(struct task_struct *task)
 657 {
 658         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 659                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 660 }
 661 #endif
 662
 663 static int ssb_prctl_get(struct task_struct *task)
 664 {
 665         switch (ssb_mode) {
 666         case SPEC_STORE_BYPASS_DISABLE:
 667                 return PR_SPEC_DISABLE;
 668         case SPEC_STORE_BYPASS_SECCOMP:
 669         case SPEC_STORE_BYPASS_PRCTL:
 670                 if (task_spec_ssb_force_disable(task))
 671                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 672                 if (task_spec_ssb_disable(task))
 673                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 674                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 675         default:
 676                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 677                         return PR_SPEC_ENABLE;
 678                 return PR_SPEC_NOT_AFFECTED;
 679         }
 680 }
 681
 682 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 683 {
 684         switch (which) {
 685         case PR_SPEC_STORE_BYPASS:
 686                 return ssb_prctl_get(task);
 687         default:
 688                 return -ENODEV;
 689         }
 690 }
 691
 692 void x86_spec_ctrl_setup_ap(void)
 693 {
 694         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 695                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 696
 697         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 698                 x86_amd_ssb_disable();
 699 }
 700
 701 #undef pr_fmt
 702 #define pr_fmt(fmt)     "L1TF: " fmt
 703
 704 /* Default mitigation for L1TF-affected CPUs */
 705 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
 706 #if IS_ENABLED(CONFIG_KVM_INTEL)
 707 EXPORT_SYMBOL_GPL(l1tf_mitigation);
 708 #endif
 709 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
 710 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
 711
 712 /*
 713  * These CPUs all support 44bits physical address space internally in the
 714  * cache but CPUID can report a smaller number of physical address bits.
 715  *
 716  * The L1TF mitigation uses the top most address bit for the inversion of
 717  * non present PTEs. When the installed memory reaches into the top most
 718  * address bit due to memory holes, which has been observed on machines
 719  * which report 36bits physical address bits and have 32G RAM installed,
 720  * then the mitigation range check in l1tf_select_mitigation() triggers.
 721  * This is a false positive because the mitigation is still possible due to
 722  * the fact that the cache uses 44bit internally. Use the cache bits
 723  * instead of the reported physical bits and adjust them on the affected
 724  * machines to 44bit if the reported bits are less than 44.
 725  */
 726 static void override_cache_bits(struct cpuinfo_x86 *c)
 727 {
 728         if (c->x86 != 6)
 729                 return;
 730
 731         switch (c->x86_model) {
 732         case INTEL_FAM6_NEHALEM:
 733         case INTEL_FAM6_WESTMERE:
 734         case INTEL_FAM6_SANDYBRIDGE:
 735         case INTEL_FAM6_IVYBRIDGE:
 736         case INTEL_FAM6_HASWELL_CORE:
 737         case INTEL_FAM6_HASWELL_ULT:
 738         case INTEL_FAM6_HASWELL_GT3E:
 739         case INTEL_FAM6_BROADWELL_CORE:
 740         case INTEL_FAM6_BROADWELL_GT3E:
 741         case INTEL_FAM6_SKYLAKE_MOBILE:
 742         case INTEL_FAM6_SKYLAKE_DESKTOP:
 743         case INTEL_FAM6_KABYLAKE_MOBILE:
 744         case INTEL_FAM6_KABYLAKE_DESKTOP:
 745                 if (c->x86_cache_bits < 44)
 746                         c->x86_cache_bits = 44;
 747                 break;
 748         }
 749 }
 750
 751 static void __init l1tf_select_mitigation(void)
 752 {
 753         u64 half_pa;
 754
 755         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 756                 return;
 757
 758         override_cache_bits(&boot_cpu_data);
 759
 760         switch (l1tf_mitigation) {
 761         case L1TF_MITIGATION_OFF:
 762         case L1TF_MITIGATION_FLUSH_NOWARN:
 763         case L1TF_MITIGATION_FLUSH:
 764                 break;
 765         case L1TF_MITIGATION_FLUSH_NOSMT:
 766         case L1TF_MITIGATION_FULL:
 767                 cpu_smt_disable(false);
 768                 break;
 769         case L1TF_MITIGATION_FULL_FORCE:
 770                 cpu_smt_disable(true);
 771                 break;
 772         }
 773
 774 #if CONFIG_PGTABLE_LEVELS == 2
 775         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
 776         return;
 777 #endif
 778
 779         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
 780         if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
 781                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
 782                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
 783                                 half_pa);
 784                 pr_info("However, doing so will make a part of your RAM unusable.\n");
 785                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
 786                 return;
 787         }
 788
 789         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
 790 }
 791
 792 static int __init l1tf_cmdline(char *str)
 793 {
 794         if (!boot_cpu_has_bug(X86_BUG_L1TF))
 795                 return 0;
 796
 797         if (!str)
 798                 return -EINVAL;
 799
 800         if (!strcmp(str, "off"))
 801                 l1tf_mitigation = L1TF_MITIGATION_OFF;
 802         else if (!strcmp(str, "flush,nowarn"))
 803                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
 804         else if (!strcmp(str, "flush"))
 805                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
 806         else if (!strcmp(str, "flush,nosmt"))
 807                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
 808         else if (!strcmp(str, "full"))
 809                 l1tf_mitigation = L1TF_MITIGATION_FULL;
 810         else if (!strcmp(str, "full,force"))
 811                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
 812
 813         return 0;
 814 }
 815 early_param("l1tf", l1tf_cmdline);
 816
 817 #undef pr_fmt
 818
 819 #ifdef CONFIG_SYSFS
 820
 821 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
 822
 823 #if IS_ENABLED(CONFIG_KVM_INTEL)
 824 static const char *l1tf_vmx_states[] = {
 825         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
 826         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
 827         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
 828         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
 829         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
 830         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
 831 };
 832
 833 static ssize_t l1tf_show_state(char *buf)
 834 {
 835         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
 836                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 837
 838         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
 839             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
 840              cpu_smt_control == CPU_SMT_ENABLED))
 841                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
 842                                l1tf_vmx_states[l1tf_vmx_mitigation]);
 843
 844         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
 845                        l1tf_vmx_states[l1tf_vmx_mitigation],
 846                        cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled");
 847 }
 848 #else
 849 static ssize_t l1tf_show_state(char *buf)
 850 {
 851         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
 852 }
 853 #endif
 854
 855 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 856                                char *buf, unsigned int bug)
 857 {
 858         int ret;
 859
 860         if (!boot_cpu_has_bug(bug))
 861                 return sprintf(buf, "Not affected\n");
 862
 863         switch (bug) {
 864         case X86_BUG_CPU_MELTDOWN:
 865                 if (boot_cpu_has(X86_FEATURE_PTI))
 866                         return sprintf(buf, "Mitigation: PTI\n");
 867
 868                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
 869                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
 870
 871                 break;
 872
 873         case X86_BUG_SPECTRE_V1:
 874                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 875
 876         case X86_BUG_SPECTRE_V2:
 877                 ret = sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 878                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 879                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 880                                (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "",
 881                                boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
 882                                spectre_v2_module_string());
 883                 return ret;
 884
 885         case X86_BUG_SPEC_STORE_BYPASS:
 886                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 887
 888         case X86_BUG_L1TF:
 889                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
 890                         return l1tf_show_state(buf);
 891                 break;
 892         default:
 893                 break;
 894         }
 895
 896         return sprintf(buf, "Vulnerable\n");
 897 }
 898
 899 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 900 {
 901         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 902 }
 903
 904 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 905 {
 906         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 907 }
 908
 909 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 910 {
 911         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 912 }
 913
 914 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 915 {
 916         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 917 }
 918
 919 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
 920 {
 921         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
 922 }
 923 #endif