arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18 #include <linux/pgtable.h>
  19
  20 #include <asm/spec-ctrl.h>
  21 #include <asm/cmdline.h>
  22 #include <asm/bugs.h>
  23 #include <asm/processor.h>
  24 #include <asm/processor-flags.h>
  25 #include <asm/fpu/internal.h>
  26 #include <asm/msr.h>
  27 #include <asm/vmx.h>
  28 #include <asm/paravirt.h>
  29 #include <asm/alternative.h>
  30 #include <asm/set_memory.h>
  31 #include <asm/intel-family.h>
  32 #include <asm/e820/api.h>
  33 #include <asm/hypervisor.h>
  34
  35 #include "cpu.h"
  36
  37 static void __init spectre_v1_select_mitigation(void);
  38 static void __init spectre_v2_select_mitigation(void);
  39 static void __init ssb_select_mitigation(void);
  40 static void __init l1tf_select_mitigation(void);
  41 static void __init mds_select_mitigation(void);
  42 static void __init mds_print_mitigation(void);
  43 static void __init taa_select_mitigation(void);
  44 static void __init srbds_select_mitigation(void);
  45
  46 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
  47 u64 x86_spec_ctrl_base;
  48 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  49 static DEFINE_MUTEX(spec_ctrl_mutex);
  50
  51 /*
  52  * The vendor and possibly platform specific bits which can be modified in
  53  * x86_spec_ctrl_base.
  54  */
  55 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  56
  57 /*
  58  * AMD specific MSR info for Speculative Store Bypass control.
  59  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  60  */
  61 u64 __ro_after_init x86_amd_ls_cfg_base;
  62 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  63
  64 /* Control conditional STIBP in switch_to() */
  65 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
  66 /* Control conditional IBPB in switch_mm() */
  67 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
  68 /* Control unconditional IBPB in switch_mm() */
  69 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
  70
  71 /* Control MDS CPU buffer clear before returning to user space */
  72 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
  73 EXPORT_SYMBOL_GPL(mds_user_clear);
  74 /* Control MDS CPU buffer clear before idling (halt, mwait) */
  75 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
  76 EXPORT_SYMBOL_GPL(mds_idle_clear);
  77
  78 void __init check_bugs(void)
  79 {
  80         identify_boot_cpu();
  81
  82         /*
  83          * identify_boot_cpu() initialized SMT support information, let the
  84          * core code know.
  85          */
  86         cpu_smt_check_topology();
  87
  88         if (!IS_ENABLED(CONFIG_SMP)) {
  89                 pr_info("CPU: ");
  90                 print_cpu_info(&boot_cpu_data);
  91         }
  92
  93         /*
  94          * Read the SPEC_CTRL MSR to account for reserved bits which may
  95          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  96          * init code as it is not enumerated and depends on the family.
  97          */
  98         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  99                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 100
 101         /* Allow STIBP in MSR_SPEC_CTRL if supported */
 102         if (boot_cpu_has(X86_FEATURE_STIBP))
 103                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
 104
 105         /* Select the proper CPU mitigations before patching alternatives: */
 106         spectre_v1_select_mitigation();
 107         spectre_v2_select_mitigation();
 108         ssb_select_mitigation();
 109         l1tf_select_mitigation();
 110         mds_select_mitigation();
 111         taa_select_mitigation();
 112         srbds_select_mitigation();
 113
 114         /*
 115          * As MDS and TAA mitigations are inter-related, print MDS
 116          * mitigation until after TAA mitigation selection is done.
 117          */
 118         mds_print_mitigation();
 119
 120         arch_smt_update();
 121
 122 #ifdef CONFIG_X86_32
 123         /*
 124          * Check whether we are able to run this kernel safely on SMP.
 125          *
 126          * - i386 is no longer supported.
 127          * - In order to run on anything without a TSC, we need to be
 128          *   compiled for a i486.
 129          */
 130         if (boot_cpu_data.x86 < 4)
 131                 panic("Kernel requires i486+ for 'invlpg' and other features");
 132
 133         init_utsname()->machine[1] =
 134                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 135         alternative_instructions();
 136
 137         fpu__init_check_bugs();
 138 #else /* CONFIG_X86_64 */
 139         alternative_instructions();
 140
 141         /*
 142          * Make sure the first 2MB area is not mapped by huge pages
 143          * There are typically fixed size MTRRs in there and overlapping
 144          * MTRRs into large pages causes slow downs.
 145          *
 146          * Right now we don't do that with gbpages because there seems
 147          * very little benefit for that case.
 148          */
 149         if (!direct_gbpages)
 150                 set_memory_4k((unsigned long)__va(0), 1);
 151 #endif
 152 }
 153
 154 void
 155 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 156 {
 157         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 158         struct thread_info *ti = current_thread_info();
 159
 160         /* Is MSR_SPEC_CTRL implemented ? */
 161         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 162                 /*
 163                  * Restrict guest_spec_ctrl to supported values. Clear the
 164                  * modifiable bits in the host base value and or the
 165                  * modifiable bits from the guest value.
 166                  */
 167                 guestval = hostval & ~x86_spec_ctrl_mask;
 168                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 169
 170                 /* SSBD controlled in MSR_SPEC_CTRL */
 171                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 172                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 173                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 174
 175                 /* Conditional STIBP enabled? */
 176                 if (static_branch_unlikely(&switch_to_cond_stibp))
 177                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 178
 179                 if (hostval != guestval) {
 180                         msrval = setguest ? guestval : hostval;
 181                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 182                 }
 183         }
 184
 185         /*
 186          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 187          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 188          */
 189         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 190             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 191                 return;
 192
 193         /*
 194          * If the host has SSBD mitigation enabled, force it in the host's
 195          * virtual MSR value. If its not permanently enabled, evaluate
 196          * current's TIF_SSBD thread flag.
 197          */
 198         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 199                 hostval = SPEC_CTRL_SSBD;
 200         else
 201                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 202
 203         /* Sanitize the guest value */
 204         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 205
 206         if (hostval != guestval) {
 207                 unsigned long tif;
 208
 209                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 210                                  ssbd_spec_ctrl_to_tif(hostval);
 211
 212                 speculation_ctrl_update(tif);
 213         }
 214 }
 215 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 216
 217 static void x86_amd_ssb_disable(void)
 218 {
 219         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 220
 221         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 222                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 223         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 224                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 225 }
 226
 227 #undef pr_fmt
 228 #define pr_fmt(fmt)     "MDS: " fmt
 229
 230 /* Default mitigation for MDS-affected CPUs */
 231 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 232 static bool mds_nosmt __ro_after_init = false;
 233
 234 static const char * const mds_strings[] = {
 235         [MDS_MITIGATION_OFF]    = "Vulnerable",
 236         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 237         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 238 };
 239
 240 static void __init mds_select_mitigation(void)
 241 {
 242         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 243                 mds_mitigation = MDS_MITIGATION_OFF;
 244                 return;
 245         }
 246
 247         if (mds_mitigation == MDS_MITIGATION_FULL) {
 248                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 249                         mds_mitigation = MDS_MITIGATION_VMWERV;
 250
 251                 static_branch_enable(&mds_user_clear);
 252
 253                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 254                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 255                         cpu_smt_disable(false);
 256         }
 257 }
 258
 259 static void __init mds_print_mitigation(void)
 260 {
 261         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
 262                 return;
 263
 264         pr_info("%s\n", mds_strings[mds_mitigation]);
 265 }
 266
 267 static int __init mds_cmdline(char *str)
 268 {
 269         if (!boot_cpu_has_bug(X86_BUG_MDS))
 270                 return 0;
 271
 272         if (!str)
 273                 return -EINVAL;
 274
 275         if (!strcmp(str, "off"))
 276                 mds_mitigation = MDS_MITIGATION_OFF;
 277         else if (!strcmp(str, "full"))
 278                 mds_mitigation = MDS_MITIGATION_FULL;
 279         else if (!strcmp(str, "full,nosmt")) {
 280                 mds_mitigation = MDS_MITIGATION_FULL;
 281                 mds_nosmt = true;
 282         }
 283
 284         return 0;
 285 }
 286 early_param("mds", mds_cmdline);
 287
 288 #undef pr_fmt
 289 #define pr_fmt(fmt)     "TAA: " fmt
 290
 291 enum taa_mitigations {
 292         TAA_MITIGATION_OFF,
 293         TAA_MITIGATION_UCODE_NEEDED,
 294         TAA_MITIGATION_VERW,
 295         TAA_MITIGATION_TSX_DISABLED,
 296 };
 297
 298 /* Default mitigation for TAA-affected CPUs */
 299 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 300 static bool taa_nosmt __ro_after_init;
 301
 302 static const char * const taa_strings[] = {
 303         [TAA_MITIGATION_OFF]            = "Vulnerable",
 304         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 305         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 306         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 307 };
 308
 309 static void __init taa_select_mitigation(void)
 310 {
 311         u64 ia32_cap;
 312
 313         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 314                 taa_mitigation = TAA_MITIGATION_OFF;
 315                 return;
 316         }
 317
 318         /* TSX previously disabled by tsx=off */
 319         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 320                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 321                 goto out;
 322         }
 323
 324         if (cpu_mitigations_off()) {
 325                 taa_mitigation = TAA_MITIGATION_OFF;
 326                 return;
 327         }
 328
 329         /*
 330          * TAA mitigation via VERW is turned off if both
 331          * tsx_async_abort=off and mds=off are specified.
 332          */
 333         if (taa_mitigation == TAA_MITIGATION_OFF &&
 334             mds_mitigation == MDS_MITIGATION_OFF)
 335                 goto out;
 336
 337         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 338                 taa_mitigation = TAA_MITIGATION_VERW;
 339         else
 340                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 341
 342         /*
 343          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 344          * A microcode update fixes this behavior to clear CPU buffers. It also
 345          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 346          * ARCH_CAP_TSX_CTRL_MSR bit.
 347          *
 348          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 349          * update is required.
 350          */
 351         ia32_cap = x86_read_arch_cap_msr();
 352         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 353             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 354                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 355
 356         /*
 357          * TSX is enabled, select alternate mitigation for TAA which is
 358          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 359          *
 360          * For guests that can't determine whether the correct microcode is
 361          * present on host, enable the mitigation for UCODE_NEEDED as well.
 362          */
 363         static_branch_enable(&mds_user_clear);
 364
 365         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 366                 cpu_smt_disable(false);
 367
 368         /*
 369          * Update MDS mitigation, if necessary, as the mds_user_clear is
 370          * now enabled for TAA mitigation.
 371          */
 372         if (mds_mitigation == MDS_MITIGATION_OFF &&
 373             boot_cpu_has_bug(X86_BUG_MDS)) {
 374                 mds_mitigation = MDS_MITIGATION_FULL;
 375                 mds_select_mitigation();
 376         }
 377 out:
 378         pr_info("%s\n", taa_strings[taa_mitigation]);
 379 }
 380
 381 static int __init tsx_async_abort_parse_cmdline(char *str)
 382 {
 383         if (!boot_cpu_has_bug(X86_BUG_TAA))
 384                 return 0;
 385
 386         if (!str)
 387                 return -EINVAL;
 388
 389         if (!strcmp(str, "off")) {
 390                 taa_mitigation = TAA_MITIGATION_OFF;
 391         } else if (!strcmp(str, "full")) {
 392                 taa_mitigation = TAA_MITIGATION_VERW;
 393         } else if (!strcmp(str, "full,nosmt")) {
 394                 taa_mitigation = TAA_MITIGATION_VERW;
 395                 taa_nosmt = true;
 396         }
 397
 398         return 0;
 399 }
 400 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 401
 402 #undef pr_fmt
 403 #define pr_fmt(fmt)     "SRBDS: " fmt
 404
 405 enum srbds_mitigations {
 406         SRBDS_MITIGATION_OFF,
 407         SRBDS_MITIGATION_UCODE_NEEDED,
 408         SRBDS_MITIGATION_FULL,
 409         SRBDS_MITIGATION_TSX_OFF,
 410         SRBDS_MITIGATION_HYPERVISOR,
 411 };
 412
 413 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 414
 415 static const char * const srbds_strings[] = {
 416         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 417         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 418         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 419         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 420         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 421 };
 422
 423 static bool srbds_off;
 424
 425 void update_srbds_msr(void)
 426 {
 427         u64 mcu_ctrl;
 428
 429         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 430                 return;
 431
 432         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 433                 return;
 434
 435         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 436                 return;
 437
 438         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 439
 440         switch (srbds_mitigation) {
 441         case SRBDS_MITIGATION_OFF:
 442         case SRBDS_MITIGATION_TSX_OFF:
 443                 mcu_ctrl |= RNGDS_MITG_DIS;
 444                 break;
 445         case SRBDS_MITIGATION_FULL:
 446                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 447                 break;
 448         default:
 449                 break;
 450         }
 451
 452         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 453 }
 454
 455 static void __init srbds_select_mitigation(void)
 456 {
 457         u64 ia32_cap;
 458
 459         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 460                 return;
 461
 462         /*
 463          * Check to see if this is one of the MDS_NO systems supporting
 464          * TSX that are only exposed to SRBDS when TSX is enabled.
 465          */
 466         ia32_cap = x86_read_arch_cap_msr();
 467         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
 468                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 469         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 470                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 471         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 472                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 473         else if (cpu_mitigations_off() || srbds_off)
 474                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 475
 476         update_srbds_msr();
 477         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 478 }
 479
 480 static int __init srbds_parse_cmdline(char *str)
 481 {
 482         if (!str)
 483                 return -EINVAL;
 484
 485         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 486                 return 0;
 487
 488         srbds_off = !strcmp(str, "off");
 489         return 0;
 490 }
 491 early_param("srbds", srbds_parse_cmdline);
 492
 493 #undef pr_fmt
 494 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 495
 496 enum spectre_v1_mitigation {
 497         SPECTRE_V1_MITIGATION_NONE,
 498         SPECTRE_V1_MITIGATION_AUTO,
 499 };
 500
 501 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 502         SPECTRE_V1_MITIGATION_AUTO;
 503
 504 static const char * const spectre_v1_strings[] = {
 505         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 506         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 507 };
 508
 509 /*
 510  * Does SMAP provide full mitigation against speculative kernel access to
 511  * userspace?
 512  */
 513 static bool smap_works_speculatively(void)
 514 {
 515         if (!boot_cpu_has(X86_FEATURE_SMAP))
 516                 return false;
 517
 518         /*
 519          * On CPUs which are vulnerable to Meltdown, SMAP does not
 520          * prevent speculative access to user data in the L1 cache.
 521          * Consider SMAP to be non-functional as a mitigation on these
 522          * CPUs.
 523          */
 524         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 525                 return false;
 526
 527         return true;
 528 }
 529
 530 static void __init spectre_v1_select_mitigation(void)
 531 {
 532         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 533                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 534                 return;
 535         }
 536
 537         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 538                 /*
 539                  * With Spectre v1, a user can speculatively control either
 540                  * path of a conditional swapgs with a user-controlled GS
 541                  * value.  The mitigation is to add lfences to both code paths.
 542                  *
 543                  * If FSGSBASE is enabled, the user can put a kernel address in
 544                  * GS, in which case SMAP provides no protection.
 545                  *
 546                  * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the
 547                  *         FSGSBASE enablement patches have been merged. ]
 548                  *
 549                  * If FSGSBASE is disabled, the user can only put a user space
 550                  * address in GS.  That makes an attack harder, but still
 551                  * possible if there's no SMAP protection.
 552                  */
 553                 if (!smap_works_speculatively()) {
 554                         /*
 555                          * Mitigation can be provided from SWAPGS itself or
 556                          * PTI as the CR3 write in the Meltdown mitigation
 557                          * is serializing.
 558                          *
 559                          * If neither is there, mitigate with an LFENCE to
 560                          * stop speculation through swapgs.
 561                          */
 562                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 563                             !boot_cpu_has(X86_FEATURE_PTI))
 564                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 565
 566                         /*
 567                          * Enable lfences in the kernel entry (non-swapgs)
 568                          * paths, to prevent user entry from speculatively
 569                          * skipping swapgs.
 570                          */
 571                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 572                 }
 573         }
 574
 575         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 576 }
 577
 578 static int __init nospectre_v1_cmdline(char *str)
 579 {
 580         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 581         return 0;
 582 }
 583 early_param("nospectre_v1", nospectre_v1_cmdline);
 584
 585 #undef pr_fmt
 586 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 587
 588 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 589         SPECTRE_V2_NONE;
 590
 591 static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init =
 592         SPECTRE_V2_USER_NONE;
 593
 594 #ifdef CONFIG_RETPOLINE
 595 static bool spectre_v2_bad_module;
 596
 597 bool retpoline_module_ok(bool has_retpoline)
 598 {
 599         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 600                 return true;
 601
 602         pr_err("System may be vulnerable to spectre v2\n");
 603         spectre_v2_bad_module = true;
 604         return false;
 605 }
 606
 607 static inline const char *spectre_v2_module_string(void)
 608 {
 609         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 610 }
 611 #else
 612 static inline const char *spectre_v2_module_string(void) { return ""; }
 613 #endif
 614
 615 static inline bool match_option(const char *arg, int arglen, const char *opt)
 616 {
 617         int len = strlen(opt);
 618
 619         return len == arglen && !strncmp(arg, opt, len);
 620 }
 621
 622 /* The kernel command line selection for spectre v2 */
 623 enum spectre_v2_mitigation_cmd {
 624         SPECTRE_V2_CMD_NONE,
 625         SPECTRE_V2_CMD_AUTO,
 626         SPECTRE_V2_CMD_FORCE,
 627         SPECTRE_V2_CMD_RETPOLINE,
 628         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 629         SPECTRE_V2_CMD_RETPOLINE_AMD,
 630 };
 631
 632 enum spectre_v2_user_cmd {
 633         SPECTRE_V2_USER_CMD_NONE,
 634         SPECTRE_V2_USER_CMD_AUTO,
 635         SPECTRE_V2_USER_CMD_FORCE,
 636         SPECTRE_V2_USER_CMD_PRCTL,
 637         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
 638         SPECTRE_V2_USER_CMD_SECCOMP,
 639         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
 640 };
 641
 642 static const char * const spectre_v2_user_strings[] = {
 643         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
 644         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
 645         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
 646         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
 647         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
 648 };
 649
 650 static const struct {
 651         const char                      *option;
 652         enum spectre_v2_user_cmd        cmd;
 653         bool                            secure;
 654 } v2_user_options[] __initconst = {
 655         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
 656         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
 657         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
 658         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
 659         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
 660         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
 661         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
 662 };
 663
 664 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
 665 {
 666         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 667                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
 668 }
 669
 670 static enum spectre_v2_user_cmd __init
 671 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
 672 {
 673         char arg[20];
 674         int ret, i;
 675
 676         switch (v2_cmd) {
 677         case SPECTRE_V2_CMD_NONE:
 678                 return SPECTRE_V2_USER_CMD_NONE;
 679         case SPECTRE_V2_CMD_FORCE:
 680                 return SPECTRE_V2_USER_CMD_FORCE;
 681         default:
 682                 break;
 683         }
 684
 685         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
 686                                   arg, sizeof(arg));
 687         if (ret < 0)
 688                 return SPECTRE_V2_USER_CMD_AUTO;
 689
 690         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
 691                 if (match_option(arg, ret, v2_user_options[i].option)) {
 692                         spec_v2_user_print_cond(v2_user_options[i].option,
 693                                                 v2_user_options[i].secure);
 694                         return v2_user_options[i].cmd;
 695                 }
 696         }
 697
 698         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
 699         return SPECTRE_V2_USER_CMD_AUTO;
 700 }
 701
 702 static void __init
 703 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
 704 {
 705         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
 706         bool smt_possible = IS_ENABLED(CONFIG_SMP);
 707         enum spectre_v2_user_cmd cmd;
 708
 709         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
 710                 return;
 711
 712         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
 713             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
 714                 smt_possible = false;
 715
 716         cmd = spectre_v2_parse_user_cmdline(v2_cmd);
 717         switch (cmd) {
 718         case SPECTRE_V2_USER_CMD_NONE:
 719                 goto set_mode;
 720         case SPECTRE_V2_USER_CMD_FORCE:
 721                 mode = SPECTRE_V2_USER_STRICT;
 722                 break;
 723         case SPECTRE_V2_USER_CMD_PRCTL:
 724         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 725                 mode = SPECTRE_V2_USER_PRCTL;
 726                 break;
 727         case SPECTRE_V2_USER_CMD_AUTO:
 728         case SPECTRE_V2_USER_CMD_SECCOMP:
 729         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 730                 if (IS_ENABLED(CONFIG_SECCOMP))
 731                         mode = SPECTRE_V2_USER_SECCOMP;
 732                 else
 733                         mode = SPECTRE_V2_USER_PRCTL;
 734                 break;
 735         }
 736
 737         /*
 738          * At this point, an STIBP mode other than "off" has been set.
 739          * If STIBP support is not being forced, check if STIBP always-on
 740          * is preferred.
 741          */
 742         if (mode != SPECTRE_V2_USER_STRICT &&
 743             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
 744                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
 745
 746         /* Initialize Indirect Branch Prediction Barrier */
 747         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 748                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 749
 750                 switch (cmd) {
 751                 case SPECTRE_V2_USER_CMD_FORCE:
 752                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
 753                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
 754                         static_branch_enable(&switch_mm_always_ibpb);
 755                         break;
 756                 case SPECTRE_V2_USER_CMD_PRCTL:
 757                 case SPECTRE_V2_USER_CMD_AUTO:
 758                 case SPECTRE_V2_USER_CMD_SECCOMP:
 759                         static_branch_enable(&switch_mm_cond_ibpb);
 760                         break;
 761                 default:
 762                         break;
 763                 }
 764
 765                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
 766                         static_key_enabled(&switch_mm_always_ibpb) ?
 767                         "always-on" : "conditional");
 768         }
 769
 770         /* If enhanced IBRS is enabled no STIBP required */
 771         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
 772                 return;
 773
 774         /*
 775          * If SMT is not possible or STIBP is not available clear the STIBP
 776          * mode.
 777          */
 778         if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP))
 779                 mode = SPECTRE_V2_USER_NONE;
 780 set_mode:
 781         spectre_v2_user = mode;
 782         /* Only print the STIBP mode when SMT possible */
 783         if (smt_possible)
 784                 pr_info("%s\n", spectre_v2_user_strings[mode]);
 785 }
 786
 787 static const char * const spectre_v2_strings[] = {
 788         [SPECTRE_V2_NONE]                       = "Vulnerable",
 789         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 790         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 791         [SPECTRE_V2_IBRS_ENHANCED]              = "Mitigation: Enhanced IBRS",
 792 };
 793
 794 static const struct {
 795         const char *option;
 796         enum spectre_v2_mitigation_cmd cmd;
 797         bool secure;
 798 } mitigation_options[] __initconst = {
 799         { "off",                SPECTRE_V2_CMD_NONE,              false },
 800         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
 801         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
 802         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 803         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 804         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
 805 };
 806
 807 static void __init spec_v2_print_cond(const char *reason, bool secure)
 808 {
 809         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
 810                 pr_info("%s selected on command line.\n", reason);
 811 }
 812
 813 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 814 {
 815         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 816         char arg[20];
 817         int ret, i;
 818
 819         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
 820             cpu_mitigations_off())
 821                 return SPECTRE_V2_CMD_NONE;
 822
 823         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 824         if (ret < 0)
 825                 return SPECTRE_V2_CMD_AUTO;
 826
 827         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 828                 if (!match_option(arg, ret, mitigation_options[i].option))
 829                         continue;
 830                 cmd = mitigation_options[i].cmd;
 831                 break;
 832         }
 833
 834         if (i >= ARRAY_SIZE(mitigation_options)) {
 835                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 836                 return SPECTRE_V2_CMD_AUTO;
 837         }
 838
 839         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 840              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 841              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 842             !IS_ENABLED(CONFIG_RETPOLINE)) {
 843                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 844                 return SPECTRE_V2_CMD_AUTO;
 845         }
 846
 847         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 848             boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
 849             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 850                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 851                 return SPECTRE_V2_CMD_AUTO;
 852         }
 853
 854         spec_v2_print_cond(mitigation_options[i].option,
 855                            mitigation_options[i].secure);
 856         return cmd;
 857 }
 858
 859 static void __init spectre_v2_select_mitigation(void)
 860 {
 861         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 862         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 863
 864         /*
 865          * If the CPU is not affected and the command line mode is NONE or AUTO
 866          * then nothing to do.
 867          */
 868         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 869             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 870                 return;
 871
 872         switch (cmd) {
 873         case SPECTRE_V2_CMD_NONE:
 874                 return;
 875
 876         case SPECTRE_V2_CMD_FORCE:
 877         case SPECTRE_V2_CMD_AUTO:
 878                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
 879                         mode = SPECTRE_V2_IBRS_ENHANCED;
 880                         /* Force it so VMEXIT will restore correctly */
 881                         x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
 882                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 883                         goto specv2_set_mode;
 884                 }
 885                 if (IS_ENABLED(CONFIG_RETPOLINE))
 886                         goto retpoline_auto;
 887                 break;
 888         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 889                 if (IS_ENABLED(CONFIG_RETPOLINE))
 890                         goto retpoline_amd;
 891                 break;
 892         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 893                 if (IS_ENABLED(CONFIG_RETPOLINE))
 894                         goto retpoline_generic;
 895                 break;
 896         case SPECTRE_V2_CMD_RETPOLINE:
 897                 if (IS_ENABLED(CONFIG_RETPOLINE))
 898                         goto retpoline_auto;
 899                 break;
 900         }
 901         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 902         return;
 903
 904 retpoline_auto:
 905         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
 906             boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
 907         retpoline_amd:
 908                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 909                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 910                         goto retpoline_generic;
 911                 }
 912                 mode = SPECTRE_V2_RETPOLINE_AMD;
 913                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 914                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 915         } else {
 916         retpoline_generic:
 917                 mode = SPECTRE_V2_RETPOLINE_GENERIC;
 918                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 919         }
 920
 921 specv2_set_mode:
 922         spectre_v2_enabled = mode;
 923         pr_info("%s\n", spectre_v2_strings[mode]);
 924
 925         /*
 926          * If spectre v2 protection has been enabled, unconditionally fill
 927          * RSB during a context switch; this protects against two independent
 928          * issues:
 929          *
 930          *      - RSB underflow (and switch to BTB) on Skylake+
 931          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
 932          */
 933         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 934         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 935
 936         /*
 937          * Retpoline means the kernel is safe because it has no indirect
 938          * branches. Enhanced IBRS protects firmware too, so, enable restricted
 939          * speculation around firmware calls only when Enhanced IBRS isn't
 940          * supported.
 941          *
 942          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
 943          * the user might select retpoline on the kernel command line and if
 944          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
 945          * enable IBRS around firmware calls.
 946          */
 947         if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
 948                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 949                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 950         }
 951
 952         /* Set up IBPB and STIBP depending on the general spectre V2 command */
 953         spectre_v2_user_select_mitigation(cmd);
 954 }
 955
 956 static void update_stibp_msr(void * __unused)
 957 {
 958         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 959 }
 960
 961 /* Update x86_spec_ctrl_base in case SMT state changed. */
 962 static void update_stibp_strict(void)
 963 {
 964         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
 965
 966         if (sched_smt_active())
 967                 mask |= SPEC_CTRL_STIBP;
 968
 969         if (mask == x86_spec_ctrl_base)
 970                 return;
 971
 972         pr_info("Update user space SMT mitigation: STIBP %s\n",
 973                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
 974         x86_spec_ctrl_base = mask;
 975         on_each_cpu(update_stibp_msr, NULL, 1);
 976 }
 977
 978 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
 979 static void update_indir_branch_cond(void)
 980 {
 981         if (sched_smt_active())
 982                 static_branch_enable(&switch_to_cond_stibp);
 983         else
 984                 static_branch_disable(&switch_to_cond_stibp);
 985 }
 986
 987 #undef pr_fmt
 988 #define pr_fmt(fmt) fmt
 989
 990 /* Update the static key controlling the MDS CPU buffer clear in idle */
 991 static void update_mds_branch_idle(void)
 992 {
 993         /*
 994          * Enable the idle clearing if SMT is active on CPUs which are
 995          * affected only by MSBDS and not any other MDS variant.
 996          *
 997          * The other variants cannot be mitigated when SMT is enabled, so
 998          * clearing the buffers on idle just to prevent the Store Buffer
 999          * repartitioning leak would be a window dressing exercise.
1000          */
1001         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1002                 return;
1003
1004         if (sched_smt_active())
1005                 static_branch_enable(&mds_idle_clear);
1006         else
1007                 static_branch_disable(&mds_idle_clear);
1008 }
1009
1010 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1011 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1012
1013 void cpu_bugs_smt_update(void)
1014 {
1015         mutex_lock(&spec_ctrl_mutex);
1016
1017         switch (spectre_v2_user) {
1018         case SPECTRE_V2_USER_NONE:
1019                 break;
1020         case SPECTRE_V2_USER_STRICT:
1021         case SPECTRE_V2_USER_STRICT_PREFERRED:
1022                 update_stibp_strict();
1023                 break;
1024         case SPECTRE_V2_USER_PRCTL:
1025         case SPECTRE_V2_USER_SECCOMP:
1026                 update_indir_branch_cond();
1027                 break;
1028         }
1029
1030         switch (mds_mitigation) {
1031         case MDS_MITIGATION_FULL:
1032         case MDS_MITIGATION_VMWERV:
1033                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1034                         pr_warn_once(MDS_MSG_SMT);
1035                 update_mds_branch_idle();
1036                 break;
1037         case MDS_MITIGATION_OFF:
1038                 break;
1039         }
1040
1041         switch (taa_mitigation) {
1042         case TAA_MITIGATION_VERW:
1043         case TAA_MITIGATION_UCODE_NEEDED:
1044                 if (sched_smt_active())
1045                         pr_warn_once(TAA_MSG_SMT);
1046                 break;
1047         case TAA_MITIGATION_TSX_DISABLED:
1048         case TAA_MITIGATION_OFF:
1049                 break;
1050         }
1051
1052         mutex_unlock(&spec_ctrl_mutex);
1053 }
1054
1055 #undef pr_fmt
1056 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1057
1058 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1059
1060 /* The kernel command line selection */
1061 enum ssb_mitigation_cmd {
1062         SPEC_STORE_BYPASS_CMD_NONE,
1063         SPEC_STORE_BYPASS_CMD_AUTO,
1064         SPEC_STORE_BYPASS_CMD_ON,
1065         SPEC_STORE_BYPASS_CMD_PRCTL,
1066         SPEC_STORE_BYPASS_CMD_SECCOMP,
1067 };
1068
1069 static const char * const ssb_strings[] = {
1070         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1071         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1072         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1073         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1074 };
1075
1076 static const struct {
1077         const char *option;
1078         enum ssb_mitigation_cmd cmd;
1079 } ssb_mitigation_options[]  __initconst = {
1080         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1081         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1082         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1083         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1084         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1085 };
1086
1087 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1088 {
1089         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1090         char arg[20];
1091         int ret, i;
1092
1093         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1094             cpu_mitigations_off()) {
1095                 return SPEC_STORE_BYPASS_CMD_NONE;
1096         } else {
1097                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1098                                           arg, sizeof(arg));
1099                 if (ret < 0)
1100                         return SPEC_STORE_BYPASS_CMD_AUTO;
1101
1102                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1103                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1104                                 continue;
1105
1106                         cmd = ssb_mitigation_options[i].cmd;
1107                         break;
1108                 }
1109
1110                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1111                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1112                         return SPEC_STORE_BYPASS_CMD_AUTO;
1113                 }
1114         }
1115
1116         return cmd;
1117 }
1118
1119 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1120 {
1121         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1122         enum ssb_mitigation_cmd cmd;
1123
1124         if (!boot_cpu_has(X86_FEATURE_SSBD))
1125                 return mode;
1126
1127         cmd = ssb_parse_cmdline();
1128         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1129             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1130              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1131                 return mode;
1132
1133         switch (cmd) {
1134         case SPEC_STORE_BYPASS_CMD_AUTO:
1135         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1136                 /*
1137                  * Choose prctl+seccomp as the default mode if seccomp is
1138                  * enabled.
1139                  */
1140                 if (IS_ENABLED(CONFIG_SECCOMP))
1141                         mode = SPEC_STORE_BYPASS_SECCOMP;
1142                 else
1143                         mode = SPEC_STORE_BYPASS_PRCTL;
1144                 break;
1145         case SPEC_STORE_BYPASS_CMD_ON:
1146                 mode = SPEC_STORE_BYPASS_DISABLE;
1147                 break;
1148         case SPEC_STORE_BYPASS_CMD_PRCTL:
1149                 mode = SPEC_STORE_BYPASS_PRCTL;
1150                 break;
1151         case SPEC_STORE_BYPASS_CMD_NONE:
1152                 break;
1153         }
1154
1155         /*
1156          * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1157          * bit in the mask to allow guests to use the mitigation even in the
1158          * case where the host does not enable it.
1159          */
1160         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1161             static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1162                 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1163         }
1164
1165         /*
1166          * We have three CPU feature flags that are in play here:
1167          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1168          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1169          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1170          */
1171         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1172                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1173                 /*
1174                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1175                  * use a completely different MSR and bit dependent on family.
1176                  */
1177                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1178                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1179                         x86_amd_ssb_disable();
1180                 } else {
1181                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1182                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1183                 }
1184         }
1185
1186         return mode;
1187 }
1188
1189 static void ssb_select_mitigation(void)
1190 {
1191         ssb_mode = __ssb_select_mitigation();
1192
1193         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1194                 pr_info("%s\n", ssb_strings[ssb_mode]);
1195 }
1196
1197 #undef pr_fmt
1198 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1199
1200 static void task_update_spec_tif(struct task_struct *tsk)
1201 {
1202         /* Force the update of the real TIF bits */
1203         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1204
1205         /*
1206          * Immediately update the speculation control MSRs for the current
1207          * task, but for a non-current task delay setting the CPU
1208          * mitigation until it is scheduled next.
1209          *
1210          * This can only happen for SECCOMP mitigation. For PRCTL it's
1211          * always the current task.
1212          */
1213         if (tsk == current)
1214                 speculation_ctrl_update_current();
1215 }
1216
1217 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1218 {
1219         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1220             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1221                 return -ENXIO;
1222
1223         switch (ctrl) {
1224         case PR_SPEC_ENABLE:
1225                 /* If speculation is force disabled, enable is not allowed */
1226                 if (task_spec_ssb_force_disable(task))
1227                         return -EPERM;
1228                 task_clear_spec_ssb_disable(task);
1229                 task_clear_spec_ssb_noexec(task);
1230                 task_update_spec_tif(task);
1231                 break;
1232         case PR_SPEC_DISABLE:
1233                 task_set_spec_ssb_disable(task);
1234                 task_clear_spec_ssb_noexec(task);
1235                 task_update_spec_tif(task);
1236                 break;
1237         case PR_SPEC_FORCE_DISABLE:
1238                 task_set_spec_ssb_disable(task);
1239                 task_set_spec_ssb_force_disable(task);
1240                 task_clear_spec_ssb_noexec(task);
1241                 task_update_spec_tif(task);
1242                 break;
1243         case PR_SPEC_DISABLE_NOEXEC:
1244                 if (task_spec_ssb_force_disable(task))
1245                         return -EPERM;
1246                 task_set_spec_ssb_disable(task);
1247                 task_set_spec_ssb_noexec(task);
1248                 task_update_spec_tif(task);
1249                 break;
1250         default:
1251                 return -ERANGE;
1252         }
1253         return 0;
1254 }
1255
1256 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1257 {
1258         switch (ctrl) {
1259         case PR_SPEC_ENABLE:
1260                 if (spectre_v2_user == SPECTRE_V2_USER_NONE)
1261                         return 0;
1262                 /*
1263                  * Indirect branch speculation is always disabled in strict
1264                  * mode.
1265                  */
1266                 if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||
1267                     spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)
1268                         return -EPERM;
1269                 task_clear_spec_ib_disable(task);
1270                 task_update_spec_tif(task);
1271                 break;
1272         case PR_SPEC_DISABLE:
1273         case PR_SPEC_FORCE_DISABLE:
1274                 /*
1275                  * Indirect branch speculation is always allowed when
1276                  * mitigation is force disabled.
1277                  */
1278                 if (spectre_v2_user == SPECTRE_V2_USER_NONE)
1279                         return -EPERM;
1280                 if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||
1281                     spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)
1282                         return 0;
1283                 task_set_spec_ib_disable(task);
1284                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1285                         task_set_spec_ib_force_disable(task);
1286                 task_update_spec_tif(task);
1287                 break;
1288         default:
1289                 return -ERANGE;
1290         }
1291         return 0;
1292 }
1293
1294 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1295                              unsigned long ctrl)
1296 {
1297         switch (which) {
1298         case PR_SPEC_STORE_BYPASS:
1299                 return ssb_prctl_set(task, ctrl);
1300         case PR_SPEC_INDIRECT_BRANCH:
1301                 return ib_prctl_set(task, ctrl);
1302         default:
1303                 return -ENODEV;
1304         }
1305 }
1306
1307 #ifdef CONFIG_SECCOMP
1308 void arch_seccomp_spec_mitigate(struct task_struct *task)
1309 {
1310         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1311                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1312         if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP)
1313                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1314 }
1315 #endif
1316
1317 static int ssb_prctl_get(struct task_struct *task)
1318 {
1319         switch (ssb_mode) {
1320         case SPEC_STORE_BYPASS_DISABLE:
1321                 return PR_SPEC_DISABLE;
1322         case SPEC_STORE_BYPASS_SECCOMP:
1323         case SPEC_STORE_BYPASS_PRCTL:
1324                 if (task_spec_ssb_force_disable(task))
1325                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1326                 if (task_spec_ssb_noexec(task))
1327                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1328                 if (task_spec_ssb_disable(task))
1329                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1330                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1331         default:
1332                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1333                         return PR_SPEC_ENABLE;
1334                 return PR_SPEC_NOT_AFFECTED;
1335         }
1336 }
1337
1338 static int ib_prctl_get(struct task_struct *task)
1339 {
1340         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1341                 return PR_SPEC_NOT_AFFECTED;
1342
1343         switch (spectre_v2_user) {
1344         case SPECTRE_V2_USER_NONE:
1345                 return PR_SPEC_ENABLE;
1346         case SPECTRE_V2_USER_PRCTL:
1347         case SPECTRE_V2_USER_SECCOMP:
1348                 if (task_spec_ib_force_disable(task))
1349                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1350                 if (task_spec_ib_disable(task))
1351                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1352                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1353         case SPECTRE_V2_USER_STRICT:
1354         case SPECTRE_V2_USER_STRICT_PREFERRED:
1355                 return PR_SPEC_DISABLE;
1356         default:
1357                 return PR_SPEC_NOT_AFFECTED;
1358         }
1359 }
1360
1361 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1362 {
1363         switch (which) {
1364         case PR_SPEC_STORE_BYPASS:
1365                 return ssb_prctl_get(task);
1366         case PR_SPEC_INDIRECT_BRANCH:
1367                 return ib_prctl_get(task);
1368         default:
1369                 return -ENODEV;
1370         }
1371 }
1372
1373 void x86_spec_ctrl_setup_ap(void)
1374 {
1375         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1376                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1377
1378         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1379                 x86_amd_ssb_disable();
1380 }
1381
1382 bool itlb_multihit_kvm_mitigation;
1383 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1384
1385 #undef pr_fmt
1386 #define pr_fmt(fmt)     "L1TF: " fmt
1387
1388 /* Default mitigation for L1TF-affected CPUs */
1389 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1390 #if IS_ENABLED(CONFIG_KVM_INTEL)
1391 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1392 #endif
1393 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1394 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1395
1396 /*
1397  * These CPUs all support 44bits physical address space internally in the
1398  * cache but CPUID can report a smaller number of physical address bits.
1399  *
1400  * The L1TF mitigation uses the top most address bit for the inversion of
1401  * non present PTEs. When the installed memory reaches into the top most
1402  * address bit due to memory holes, which has been observed on machines
1403  * which report 36bits physical address bits and have 32G RAM installed,
1404  * then the mitigation range check in l1tf_select_mitigation() triggers.
1405  * This is a false positive because the mitigation is still possible due to
1406  * the fact that the cache uses 44bit internally. Use the cache bits
1407  * instead of the reported physical bits and adjust them on the affected
1408  * machines to 44bit if the reported bits are less than 44.
1409  */
1410 static void override_cache_bits(struct cpuinfo_x86 *c)
1411 {
1412         if (c->x86 != 6)
1413                 return;
1414
1415         switch (c->x86_model) {
1416         case INTEL_FAM6_NEHALEM:
1417         case INTEL_FAM6_WESTMERE:
1418         case INTEL_FAM6_SANDYBRIDGE:
1419         case INTEL_FAM6_IVYBRIDGE:
1420         case INTEL_FAM6_HASWELL:
1421         case INTEL_FAM6_HASWELL_L:
1422         case INTEL_FAM6_HASWELL_G:
1423         case INTEL_FAM6_BROADWELL:
1424         case INTEL_FAM6_BROADWELL_G:
1425         case INTEL_FAM6_SKYLAKE_L:
1426         case INTEL_FAM6_SKYLAKE:
1427         case INTEL_FAM6_KABYLAKE_L:
1428         case INTEL_FAM6_KABYLAKE:
1429                 if (c->x86_cache_bits < 44)
1430                         c->x86_cache_bits = 44;
1431                 break;
1432         }
1433 }
1434
1435 static void __init l1tf_select_mitigation(void)
1436 {
1437         u64 half_pa;
1438
1439         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1440                 return;
1441
1442         if (cpu_mitigations_off())
1443                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1444         else if (cpu_mitigations_auto_nosmt())
1445                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1446
1447         override_cache_bits(&boot_cpu_data);
1448
1449         switch (l1tf_mitigation) {
1450         case L1TF_MITIGATION_OFF:
1451         case L1TF_MITIGATION_FLUSH_NOWARN:
1452         case L1TF_MITIGATION_FLUSH:
1453                 break;
1454         case L1TF_MITIGATION_FLUSH_NOSMT:
1455         case L1TF_MITIGATION_FULL:
1456                 cpu_smt_disable(false);
1457                 break;
1458         case L1TF_MITIGATION_FULL_FORCE:
1459                 cpu_smt_disable(true);
1460                 break;
1461         }
1462
1463 #if CONFIG_PGTABLE_LEVELS == 2
1464         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1465         return;
1466 #endif
1467
1468         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1469         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1470                         e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1471                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1472                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1473                                 half_pa);
1474                 pr_info("However, doing so will make a part of your RAM unusable.\n");
1475                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1476                 return;
1477         }
1478
1479         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1480 }
1481
1482 static int __init l1tf_cmdline(char *str)
1483 {
1484         if (!boot_cpu_has_bug(X86_BUG_L1TF))
1485                 return 0;
1486
1487         if (!str)
1488                 return -EINVAL;
1489
1490         if (!strcmp(str, "off"))
1491                 l1tf_mitigation = L1TF_MITIGATION_OFF;
1492         else if (!strcmp(str, "flush,nowarn"))
1493                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1494         else if (!strcmp(str, "flush"))
1495                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1496         else if (!strcmp(str, "flush,nosmt"))
1497                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1498         else if (!strcmp(str, "full"))
1499                 l1tf_mitigation = L1TF_MITIGATION_FULL;
1500         else if (!strcmp(str, "full,force"))
1501                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1502
1503         return 0;
1504 }
1505 early_param("l1tf", l1tf_cmdline);
1506
1507 #undef pr_fmt
1508 #define pr_fmt(fmt) fmt
1509
1510 #ifdef CONFIG_SYSFS
1511
1512 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1513
1514 #if IS_ENABLED(CONFIG_KVM_INTEL)
1515 static const char * const l1tf_vmx_states[] = {
1516         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
1517         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
1518         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
1519         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
1520         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
1521         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
1522 };
1523
1524 static ssize_t l1tf_show_state(char *buf)
1525 {
1526         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1527                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1528
1529         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1530             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1531              sched_smt_active())) {
1532                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1533                                l1tf_vmx_states[l1tf_vmx_mitigation]);
1534         }
1535
1536         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1537                        l1tf_vmx_states[l1tf_vmx_mitigation],
1538                        sched_smt_active() ? "vulnerable" : "disabled");
1539 }
1540
1541 static ssize_t itlb_multihit_show_state(char *buf)
1542 {
1543         if (itlb_multihit_kvm_mitigation)
1544                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1545         else
1546                 return sprintf(buf, "KVM: Vulnerable\n");
1547 }
1548 #else
1549 static ssize_t l1tf_show_state(char *buf)
1550 {
1551         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1552 }
1553
1554 static ssize_t itlb_multihit_show_state(char *buf)
1555 {
1556         return sprintf(buf, "Processor vulnerable\n");
1557 }
1558 #endif
1559
1560 static ssize_t mds_show_state(char *buf)
1561 {
1562         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1563                 return sprintf(buf, "%s; SMT Host state unknown\n",
1564                                mds_strings[mds_mitigation]);
1565         }
1566
1567         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1568                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1569                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1570                                 sched_smt_active() ? "mitigated" : "disabled"));
1571         }
1572
1573         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1574                        sched_smt_active() ? "vulnerable" : "disabled");
1575 }
1576
1577 static ssize_t tsx_async_abort_show_state(char *buf)
1578 {
1579         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1580             (taa_mitigation == TAA_MITIGATION_OFF))
1581                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1582
1583         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1584                 return sprintf(buf, "%s; SMT Host state unknown\n",
1585                                taa_strings[taa_mitigation]);
1586         }
1587
1588         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1589                        sched_smt_active() ? "vulnerable" : "disabled");
1590 }
1591
1592 static char *stibp_state(void)
1593 {
1594         if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1595                 return "";
1596
1597         switch (spectre_v2_user) {
1598         case SPECTRE_V2_USER_NONE:
1599                 return ", STIBP: disabled";
1600         case SPECTRE_V2_USER_STRICT:
1601                 return ", STIBP: forced";
1602         case SPECTRE_V2_USER_STRICT_PREFERRED:
1603                 return ", STIBP: always-on";
1604         case SPECTRE_V2_USER_PRCTL:
1605         case SPECTRE_V2_USER_SECCOMP:
1606                 if (static_key_enabled(&switch_to_cond_stibp))
1607                         return ", STIBP: conditional";
1608         }
1609         return "";
1610 }
1611
1612 static char *ibpb_state(void)
1613 {
1614         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1615                 if (static_key_enabled(&switch_mm_always_ibpb))
1616                         return ", IBPB: always-on";
1617                 if (static_key_enabled(&switch_mm_cond_ibpb))
1618                         return ", IBPB: conditional";
1619                 return ", IBPB: disabled";
1620         }
1621         return "";
1622 }
1623
1624 static ssize_t srbds_show_state(char *buf)
1625 {
1626         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1627 }
1628
1629 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1630                                char *buf, unsigned int bug)
1631 {
1632         if (!boot_cpu_has_bug(bug))
1633                 return sprintf(buf, "Not affected\n");
1634
1635         switch (bug) {
1636         case X86_BUG_CPU_MELTDOWN:
1637                 if (boot_cpu_has(X86_FEATURE_PTI))
1638                         return sprintf(buf, "Mitigation: PTI\n");
1639
1640                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
1641                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1642
1643                 break;
1644
1645         case X86_BUG_SPECTRE_V1:
1646                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1647
1648         case X86_BUG_SPECTRE_V2:
1649                 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1650                                ibpb_state(),
1651                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1652                                stibp_state(),
1653                                boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1654                                spectre_v2_module_string());
1655
1656         case X86_BUG_SPEC_STORE_BYPASS:
1657                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1658
1659         case X86_BUG_L1TF:
1660                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1661                         return l1tf_show_state(buf);
1662                 break;
1663
1664         case X86_BUG_MDS:
1665                 return mds_show_state(buf);
1666
1667         case X86_BUG_TAA:
1668                 return tsx_async_abort_show_state(buf);
1669
1670         case X86_BUG_ITLB_MULTIHIT:
1671                 return itlb_multihit_show_state(buf);
1672
1673         case X86_BUG_SRBDS:
1674                 return srbds_show_state(buf);
1675
1676         default:
1677                 break;
1678         }
1679
1680         return sprintf(buf, "Vulnerable\n");
1681 }
1682
1683 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1684 {
1685         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1686 }
1687
1688 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1689 {
1690         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1691 }
1692
1693 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1694 {
1695         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1696 }
1697
1698 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1699 {
1700         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1701 }
1702
1703 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1704 {
1705         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1706 }
1707
1708 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1709 {
1710         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1711 }
1712
1713 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1714 {
1715         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1716 }
1717
1718 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1719 {
1720         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1721 }
1722
1723 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1724 {
1725         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
1726 }
1727 #endif