2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
34 #include <linux/smp.h>
35 #include <linux/nmi.h>
36 #include <linux/timex.h>
38 #include <asm/perf_counter.h>
39 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
43 #include <asm/arch_hooks.h>
45 #include <asm/pgalloc.h>
46 #include <asm/i8253.h>
48 #include <asm/proto.h>
50 #include <asm/i8259.h>
53 #include <mach_apic.h>
54 #include <mach_apicdef.h>
60 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
61 # error SPURIOUS_APIC_VECTOR definition error
66 * Knob to control our willingness to enable the local APIC.
70 static int force_enable_local_apic;
72 * APIC command line parameters
74 static int __init parse_lapic(char *arg)
76 force_enable_local_apic = 1;
79 early_param("lapic", parse_lapic);
80 /* Local APIC was disabled by the BIOS and enabled by the kernel */
81 static int enabled_via_apicbase;
86 static int apic_calibrate_pmtmr __initdata;
87 static __init int setup_apicpmtimer(char *s)
89 apic_calibrate_pmtmr = 1;
93 __setup("apicpmtimer", setup_apicpmtimer);
102 /* x2apic enabled before OS handover */
103 static int x2apic_preenabled;
104 static int disable_x2apic;
105 static __init int setup_nox2apic(char *str)
108 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
111 early_param("nox2apic", setup_nox2apic);
114 unsigned long mp_lapic_addr;
116 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
117 static int disable_apic_timer __cpuinitdata;
118 /* Local APIC timer works in C2 */
119 int local_apic_timer_c2_ok;
120 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
122 int first_system_vector = 0xfe;
125 * Debug level, exported for io_apic.c
127 unsigned int apic_verbosity;
131 /* Have we found an MP table */
132 int smp_found_config;
134 static struct resource lapic_resource = {
135 .name = "Local APIC",
136 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
139 static unsigned int calibration_result;
141 static int lapic_next_event(unsigned long delta,
142 struct clock_event_device *evt);
143 static void lapic_timer_setup(enum clock_event_mode mode,
144 struct clock_event_device *evt);
145 static void lapic_timer_broadcast(const struct cpumask *mask);
146 static void apic_pm_activate(void);
149 * The local apic timer can be used for any function which is CPU local.
151 static struct clock_event_device lapic_clockevent = {
153 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
154 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
156 .set_mode = lapic_timer_setup,
157 .set_next_event = lapic_next_event,
158 .broadcast = lapic_timer_broadcast,
162 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
164 static unsigned long apic_phys;
167 * Get the LAPIC version
169 static inline int lapic_get_version(void)
171 return GET_APIC_VERSION(apic_read(APIC_LVR));
175 * Check, if the APIC is integrated or a separate chip
177 static inline int lapic_is_integrated(void)
182 return APIC_INTEGRATED(lapic_get_version());
187 * Check, whether this is a modern or a first generation APIC
189 static int modern_apic(void)
191 /* AMD systems use old APIC versions, so check the CPU */
192 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
193 boot_cpu_data.x86 >= 0xf)
195 return lapic_get_version() >= 0x14;
199 * Paravirt kernels also might be using these below ops. So we still
200 * use generic apic_read()/apic_write(), which might be pointing to different
201 * ops in PARAVIRT case.
203 void xapic_wait_icr_idle(void)
205 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
209 u32 safe_xapic_wait_icr_idle(void)
216 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
220 } while (timeout++ < 1000);
225 void xapic_icr_write(u32 low, u32 id)
227 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
228 apic_write(APIC_ICR, low);
231 static u64 xapic_icr_read(void)
235 icr2 = apic_read(APIC_ICR2);
236 icr1 = apic_read(APIC_ICR);
238 return icr1 | ((u64)icr2 << 32);
241 static struct apic_ops xapic_ops = {
242 .read = native_apic_mem_read,
243 .write = native_apic_mem_write,
244 .icr_read = xapic_icr_read,
245 .icr_write = xapic_icr_write,
246 .wait_icr_idle = xapic_wait_icr_idle,
247 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
250 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
251 EXPORT_SYMBOL_GPL(apic_ops);
254 static void x2apic_wait_icr_idle(void)
256 /* no need to wait for icr idle in x2apic */
260 static u32 safe_x2apic_wait_icr_idle(void)
262 /* no need to wait for icr idle in x2apic */
266 void x2apic_icr_write(u32 low, u32 id)
268 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
271 static u64 x2apic_icr_read(void)
275 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
279 static struct apic_ops x2apic_ops = {
280 .read = native_apic_msr_read,
281 .write = native_apic_msr_write,
282 .icr_read = x2apic_icr_read,
283 .icr_write = x2apic_icr_write,
284 .wait_icr_idle = x2apic_wait_icr_idle,
285 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
290 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
292 void __cpuinit enable_NMI_through_LVT0(void)
296 /* unmask and set to NMI */
299 /* Level triggered for 82489DX (32bit mode) */
300 if (!lapic_is_integrated())
301 v |= APIC_LVT_LEVEL_TRIGGER;
303 apic_write(APIC_LVT0, v);
308 * get_physical_broadcast - Get number of physical broadcast IDs
310 int get_physical_broadcast(void)
312 return modern_apic() ? 0xff : 0xf;
317 * lapic_get_maxlvt - get the maximum number of local vector table entries
319 int lapic_get_maxlvt(void)
323 v = apic_read(APIC_LVR);
325 * - we always have APIC integrated on 64bit mode
326 * - 82489DXs do not report # of LVT entries
328 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
336 #define APIC_DIVISOR 16
339 * This function sets up the local APIC timer, with a timeout of
340 * 'clocks' APIC bus clock. During calibration we actually call
341 * this function twice on the boot CPU, once with a bogus timeout
342 * value, second time for real. The other (noncalibrating) CPUs
343 * call this function only once, with the real, calibrated value.
345 * We do reads before writes even if unnecessary, to get around the
346 * P5 APIC double write bug.
348 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
350 unsigned int lvtt_value, tmp_value;
352 lvtt_value = LOCAL_TIMER_VECTOR;
354 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
355 if (!lapic_is_integrated())
356 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
359 lvtt_value |= APIC_LVT_MASKED;
361 apic_write(APIC_LVTT, lvtt_value);
366 tmp_value = apic_read(APIC_TDCR);
367 apic_write(APIC_TDCR,
368 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
372 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
376 * Setup extended LVT, AMD specific (K8, family 10h)
378 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
379 * MCE interrupts are supported. Thus MCE offset must be set to 0.
381 * If mask=1, the LVT entry does not generate interrupts while mask=0
382 * enables the vector. See also the BKDGs.
385 #define APIC_EILVT_LVTOFF_MCE 0
386 #define APIC_EILVT_LVTOFF_IBS 1
388 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
390 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
391 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
396 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
398 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
399 return APIC_EILVT_LVTOFF_MCE;
402 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
404 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
405 return APIC_EILVT_LVTOFF_IBS;
407 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
410 * Program the next event, relative to now
412 static int lapic_next_event(unsigned long delta,
413 struct clock_event_device *evt)
415 apic_write(APIC_TMICT, delta);
420 * Setup the lapic timer in periodic or oneshot mode
422 static void lapic_timer_setup(enum clock_event_mode mode,
423 struct clock_event_device *evt)
428 /* Lapic used as dummy for broadcast ? */
429 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
432 local_irq_save(flags);
435 case CLOCK_EVT_MODE_PERIODIC:
436 case CLOCK_EVT_MODE_ONESHOT:
437 __setup_APIC_LVTT(calibration_result,
438 mode != CLOCK_EVT_MODE_PERIODIC, 1);
440 case CLOCK_EVT_MODE_UNUSED:
441 case CLOCK_EVT_MODE_SHUTDOWN:
442 v = apic_read(APIC_LVTT);
443 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
444 apic_write(APIC_LVTT, v);
445 apic_write(APIC_TMICT, 0xffffffff);
447 case CLOCK_EVT_MODE_RESUME:
448 /* Nothing to do here */
452 local_irq_restore(flags);
456 * Local APIC timer broadcast function
458 static void lapic_timer_broadcast(const struct cpumask *mask)
461 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
466 * Setup the local APIC timer for this CPU. Copy the initilized values
467 * of the boot CPU and register the clock event in the framework.
469 static void __cpuinit setup_APIC_timer(void)
471 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
473 memcpy(levt, &lapic_clockevent, sizeof(*levt));
474 levt->cpumask = cpumask_of(smp_processor_id());
476 clockevents_register_device(levt);
480 * In this functions we calibrate APIC bus clocks to the external timer.
482 * We want to do the calibration only once since we want to have local timer
483 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
486 * This was previously done by reading the PIT/HPET and waiting for a wrap
487 * around to find out, that a tick has elapsed. I have a box, where the PIT
488 * readout is broken, so it never gets out of the wait loop again. This was
489 * also reported by others.
491 * Monitoring the jiffies value is inaccurate and the clockevents
492 * infrastructure allows us to do a simple substitution of the interrupt
495 * The calibration routine also uses the pm_timer when possible, as the PIT
496 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
497 * back to normal later in the boot process).
500 #define LAPIC_CAL_LOOPS (HZ/10)
502 static __initdata int lapic_cal_loops = -1;
503 static __initdata long lapic_cal_t1, lapic_cal_t2;
504 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
505 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
506 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
509 * Temporary interrupt handler.
511 static void __init lapic_cal_handler(struct clock_event_device *dev)
513 unsigned long long tsc = 0;
514 long tapic = apic_read(APIC_TMCCT);
515 unsigned long pm = acpi_pm_read_early();
520 switch (lapic_cal_loops++) {
522 lapic_cal_t1 = tapic;
523 lapic_cal_tsc1 = tsc;
525 lapic_cal_j1 = jiffies;
528 case LAPIC_CAL_LOOPS:
529 lapic_cal_t2 = tapic;
530 lapic_cal_tsc2 = tsc;
531 if (pm < lapic_cal_pm1)
532 pm += ACPI_PM_OVRRUN;
534 lapic_cal_j2 = jiffies;
539 static int __init calibrate_by_pmtimer(long deltapm, long *delta)
541 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
542 const long pm_thresh = pm_100ms / 100;
546 #ifndef CONFIG_X86_PM_TIMER
550 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
552 /* Check, if the PM timer is available */
556 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
558 if (deltapm > (pm_100ms - pm_thresh) &&
559 deltapm < (pm_100ms + pm_thresh)) {
560 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
562 res = (((u64)deltapm) * mult) >> 22;
563 do_div(res, 1000000);
564 pr_warning("APIC calibration not consistent "
565 "with PM Timer: %ldms instead of 100ms\n",
567 /* Correct the lapic counter value */
568 res = (((u64)(*delta)) * pm_100ms);
569 do_div(res, deltapm);
570 pr_info("APIC delta adjusted to PM-Timer: "
571 "%lu (%ld)\n", (unsigned long)res, *delta);
578 static int __init calibrate_APIC_clock(void)
580 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
581 void (*real_handler)(struct clock_event_device *dev);
582 unsigned long deltaj;
584 int pm_referenced = 0;
588 /* Replace the global interrupt handler */
589 real_handler = global_clock_event->event_handler;
590 global_clock_event->event_handler = lapic_cal_handler;
593 * Setup the APIC counter to maximum. There is no way the lapic
594 * can underflow in the 100ms detection time frame
596 __setup_APIC_LVTT(0xffffffff, 0, 0);
598 /* Let the interrupts run */
601 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
606 /* Restore the real event handler */
607 global_clock_event->event_handler = real_handler;
609 /* Build delta t1-t2 as apic timer counts down */
610 delta = lapic_cal_t1 - lapic_cal_t2;
611 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
613 /* we trust the PM based calibration if possible */
614 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
617 /* Calculate the scaled math multiplication factor */
618 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
619 lapic_clockevent.shift);
620 lapic_clockevent.max_delta_ns =
621 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
622 lapic_clockevent.min_delta_ns =
623 clockevent_delta2ns(0xF, &lapic_clockevent);
625 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
627 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
628 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
629 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
633 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
634 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
636 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
637 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
640 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
642 calibration_result / (1000000 / HZ),
643 calibration_result % (1000000 / HZ));
646 * Do a sanity check on the APIC calibration result
648 if (calibration_result < (1000000 / HZ)) {
650 pr_warning("APIC frequency too slow, disabling apic timer\n");
654 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
657 * PM timer calibration failed or not turned on
658 * so lets try APIC timer based calibration
660 if (!pm_referenced) {
661 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
664 * Setup the apic timer manually
666 levt->event_handler = lapic_cal_handler;
667 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
668 lapic_cal_loops = -1;
670 /* Let the interrupts run */
673 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
676 /* Stop the lapic timer */
677 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
680 deltaj = lapic_cal_j2 - lapic_cal_j1;
681 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
683 /* Check, if the jiffies result is consistent */
684 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
685 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
687 levt->features |= CLOCK_EVT_FEAT_DUMMY;
691 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
692 pr_warning("APIC timer disabled due to verification failure\n");
700 * Setup the boot APIC
702 * Calibrate and verify the result.
704 void __init setup_boot_APIC_clock(void)
707 * The local apic timer can be disabled via the kernel
708 * commandline or from the CPU detection code. Register the lapic
709 * timer as a dummy clock event source on SMP systems, so the
710 * broadcast mechanism is used. On UP systems simply ignore it.
712 if (disable_apic_timer) {
713 pr_info("Disabling APIC timer\n");
714 /* No broadcast on UP ! */
715 if (num_possible_cpus() > 1) {
716 lapic_clockevent.mult = 1;
722 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
723 "calibrating APIC timer ...\n");
725 if (calibrate_APIC_clock()) {
726 /* No broadcast on UP ! */
727 if (num_possible_cpus() > 1)
733 * If nmi_watchdog is set to IO_APIC, we need the
734 * PIT/HPET going. Otherwise register lapic as a dummy
737 if (nmi_watchdog != NMI_IO_APIC)
738 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
740 pr_warning("APIC timer registered as dummy,"
741 " due to nmi_watchdog=%d!\n", nmi_watchdog);
743 /* Setup the lapic or request the broadcast */
747 void __cpuinit setup_secondary_APIC_clock(void)
753 * The guts of the apic timer interrupt
755 static void local_apic_timer_interrupt(void)
757 int cpu = smp_processor_id();
758 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
761 * Normally we should not be here till LAPIC has been initialized but
762 * in some cases like kdump, its possible that there is a pending LAPIC
763 * timer interrupt from previous kernel's context and is delivered in
764 * new kernel the moment interrupts are enabled.
766 * Interrupts are enabled early and LAPIC is setup much later, hence
767 * its possible that when we get here evt->event_handler is NULL.
768 * Check for event_handler being NULL and discard the interrupt as
771 if (!evt->event_handler) {
772 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
774 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
779 * the NMI deadlock-detector uses this.
781 inc_irq_stat(apic_timer_irqs);
783 evt->event_handler(evt);
787 * Local APIC timer interrupt. This is the most natural way for doing
788 * local interrupts, but local timer interrupts can be emulated by
789 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
791 * [ if a single-CPU system runs an SMP kernel then we call the local
792 * interrupt as well. Thus we cannot inline the local irq ... ]
794 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
796 struct pt_regs *old_regs = set_irq_regs(regs);
799 * NOTE! We'd better ACK the irq immediately,
800 * because timer handling can be slow.
804 * update_process_times() expects us to have done irq_enter().
805 * Besides, if we don't timer interrupts ignore the global
806 * interrupt lock, which is the WrongThing (tm) to do.
810 local_apic_timer_interrupt();
813 set_irq_regs(old_regs);
816 int setup_profiling_timer(unsigned int multiplier)
822 * Local APIC start and shutdown
826 * clear_local_APIC - shutdown the local APIC
828 * This is called, when a CPU is disabled and before rebooting, so the state of
829 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
830 * leftovers during boot.
832 void clear_local_APIC(void)
837 /* APIC hasn't been mapped yet */
841 maxlvt = lapic_get_maxlvt();
843 * Masking an LVT entry can trigger a local APIC error
844 * if the vector is zero. Mask LVTERR first to prevent this.
847 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
848 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
851 * Careful: we have to set masks only first to deassert
852 * any level-triggered sources.
854 v = apic_read(APIC_LVTT);
855 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
856 v = apic_read(APIC_LVT0);
857 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
858 v = apic_read(APIC_LVT1);
859 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
861 v = apic_read(APIC_LVTPC);
862 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
865 /* lets not touch this if we didn't frob it */
866 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
868 v = apic_read(APIC_LVTTHMR);
869 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
873 * Clean APIC state for other OSs:
875 apic_write(APIC_LVTT, APIC_LVT_MASKED);
876 apic_write(APIC_LVT0, APIC_LVT_MASKED);
877 apic_write(APIC_LVT1, APIC_LVT_MASKED);
879 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
881 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
883 /* Integrated APIC (!82489DX) ? */
884 if (lapic_is_integrated()) {
886 /* Clear ESR due to Pentium errata 3AP and 11AP */
887 apic_write(APIC_ESR, 0);
893 * disable_local_APIC - clear and disable the local APIC
895 void disable_local_APIC(void)
899 /* APIC hasn't been mapped yet */
906 * Disable APIC (implies clearing of registers
909 value = apic_read(APIC_SPIV);
910 value &= ~APIC_SPIV_APIC_ENABLED;
911 apic_write(APIC_SPIV, value);
915 * When LAPIC was disabled by the BIOS and enabled by the kernel,
916 * restore the disabled state.
918 if (enabled_via_apicbase) {
921 rdmsr(MSR_IA32_APICBASE, l, h);
922 l &= ~MSR_IA32_APICBASE_ENABLE;
923 wrmsr(MSR_IA32_APICBASE, l, h);
929 * If Linux enabled the LAPIC against the BIOS default disable it down before
930 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
931 * not power-off. Additionally clear all LVT entries before disable_local_APIC
932 * for the case where Linux didn't enable the LAPIC.
934 void lapic_shutdown(void)
941 local_irq_save(flags);
944 if (!enabled_via_apicbase)
948 disable_local_APIC();
951 local_irq_restore(flags);
955 * This is to verify that we're looking at a real local APIC.
956 * Check these against your board if the CPUs aren't getting
957 * started for no apparent reason.
959 int __init verify_local_APIC(void)
961 unsigned int reg0, reg1;
964 * The version register is read-only in a real APIC.
966 reg0 = apic_read(APIC_LVR);
967 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
968 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
969 reg1 = apic_read(APIC_LVR);
970 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
973 * The two version reads above should print the same
974 * numbers. If the second one is different, then we
975 * poke at a non-APIC.
981 * Check if the version looks reasonably.
983 reg1 = GET_APIC_VERSION(reg0);
984 if (reg1 == 0x00 || reg1 == 0xff)
986 reg1 = lapic_get_maxlvt();
987 if (reg1 < 0x02 || reg1 == 0xff)
991 * The ID register is read/write in a real APIC.
993 reg0 = apic_read(APIC_ID);
994 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
995 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
996 reg1 = apic_read(APIC_ID);
997 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
998 apic_write(APIC_ID, reg0);
999 if (reg1 != (reg0 ^ APIC_ID_MASK))
1003 * The next two are just to see if we have sane values.
1004 * They're only really relevant if we're in Virtual Wire
1005 * compatibility mode, but most boxes are anymore.
1007 reg0 = apic_read(APIC_LVT0);
1008 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1009 reg1 = apic_read(APIC_LVT1);
1010 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1016 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1018 void __init sync_Arb_IDs(void)
1021 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1024 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1030 apic_wait_icr_idle();
1032 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1033 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1034 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1038 * An initial setup of the virtual wire mode.
1040 void __init init_bsp_APIC(void)
1045 * Don't do the setup now if we have a SMP BIOS as the
1046 * through-I/O-APIC virtual wire mode might be active.
1048 if (smp_found_config || !cpu_has_apic)
1052 * Do not trust the local APIC being empty at bootup.
1059 value = apic_read(APIC_SPIV);
1060 value &= ~APIC_VECTOR_MASK;
1061 value |= APIC_SPIV_APIC_ENABLED;
1063 #ifdef CONFIG_X86_32
1064 /* This bit is reserved on P4/Xeon and should be cleared */
1065 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1066 (boot_cpu_data.x86 == 15))
1067 value &= ~APIC_SPIV_FOCUS_DISABLED;
1070 value |= APIC_SPIV_FOCUS_DISABLED;
1071 value |= SPURIOUS_APIC_VECTOR;
1072 apic_write(APIC_SPIV, value);
1075 * Set up the virtual wire mode.
1077 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1078 value = APIC_DM_NMI;
1079 if (!lapic_is_integrated()) /* 82489DX */
1080 value |= APIC_LVT_LEVEL_TRIGGER;
1081 apic_write(APIC_LVT1, value);
1084 static void __cpuinit lapic_setup_esr(void)
1086 unsigned int oldvalue, value, maxlvt;
1088 if (!lapic_is_integrated()) {
1089 pr_info("No ESR for 82489DX.\n");
1095 * Something untraceable is creating bad interrupts on
1096 * secondary quads ... for the moment, just leave the
1097 * ESR disabled - we can't do anything useful with the
1098 * errors anyway - mbligh
1100 pr_info("Leaving ESR disabled.\n");
1104 maxlvt = lapic_get_maxlvt();
1105 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1106 apic_write(APIC_ESR, 0);
1107 oldvalue = apic_read(APIC_ESR);
1109 /* enables sending errors */
1110 value = ERROR_APIC_VECTOR;
1111 apic_write(APIC_LVTERR, value);
1114 * spec says clear errors after enabling vector.
1117 apic_write(APIC_ESR, 0);
1118 value = apic_read(APIC_ESR);
1119 if (value != oldvalue)
1120 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1121 "vector: 0x%08x after: 0x%08x\n",
1127 * setup_local_APIC - setup the local APIC
1129 void __cpuinit setup_local_APIC(void)
1135 #ifdef CONFIG_X86_IO_APIC
1136 disable_ioapic_setup();
1141 #ifdef CONFIG_X86_32
1142 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1143 if (lapic_is_integrated() && esr_disable) {
1144 apic_write(APIC_ESR, 0);
1145 apic_write(APIC_ESR, 0);
1146 apic_write(APIC_ESR, 0);
1147 apic_write(APIC_ESR, 0);
1150 perf_counters_lapic_init(0);
1155 * Double-check whether this APIC is really registered.
1156 * This is meaningless in clustered apic mode, so we skip it.
1158 if (!apic_id_registered())
1162 * Intel recommends to set DFR, LDR and TPR before enabling
1163 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1164 * document number 292116). So here it goes...
1169 * Set Task Priority to 'accept all'. We never change this
1172 value = apic_read(APIC_TASKPRI);
1173 value &= ~APIC_TPRI_MASK;
1174 apic_write(APIC_TASKPRI, value);
1177 * After a crash, we no longer service the interrupts and a pending
1178 * interrupt from previous kernel might still have ISR bit set.
1180 * Most probably by now CPU has serviced that pending interrupt and
1181 * it might not have done the ack_APIC_irq() because it thought,
1182 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1183 * does not clear the ISR bit and cpu thinks it has already serivced
1184 * the interrupt. Hence a vector might get locked. It was noticed
1185 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1187 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1188 value = apic_read(APIC_ISR + i*0x10);
1189 for (j = 31; j >= 0; j--) {
1196 * Now that we are all set up, enable the APIC
1198 value = apic_read(APIC_SPIV);
1199 value &= ~APIC_VECTOR_MASK;
1203 value |= APIC_SPIV_APIC_ENABLED;
1205 #ifdef CONFIG_X86_32
1207 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1208 * certain networking cards. If high frequency interrupts are
1209 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1210 * entry is masked/unmasked at a high rate as well then sooner or
1211 * later IOAPIC line gets 'stuck', no more interrupts are received
1212 * from the device. If focus CPU is disabled then the hang goes
1215 * [ This bug can be reproduced easily with a level-triggered
1216 * PCI Ne2000 networking cards and PII/PIII processors, dual
1220 * Actually disabling the focus CPU check just makes the hang less
1221 * frequent as it makes the interrupt distributon model be more
1222 * like LRU than MRU (the short-term load is more even across CPUs).
1223 * See also the comment in end_level_ioapic_irq(). --macro
1227 * - enable focus processor (bit==0)
1228 * - 64bit mode always use processor focus
1229 * so no need to set it
1231 value &= ~APIC_SPIV_FOCUS_DISABLED;
1235 * Set spurious IRQ vector
1237 value |= SPURIOUS_APIC_VECTOR;
1238 apic_write(APIC_SPIV, value);
1241 * Set up LVT0, LVT1:
1243 * set up through-local-APIC on the BP's LINT0. This is not
1244 * strictly necessary in pure symmetric-IO mode, but sometimes
1245 * we delegate interrupts to the 8259A.
1248 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1250 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1251 if (!smp_processor_id() && (pic_mode || !value)) {
1252 value = APIC_DM_EXTINT;
1253 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1254 smp_processor_id());
1256 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1257 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1258 smp_processor_id());
1260 apic_write(APIC_LVT0, value);
1263 * only the BP should see the LINT1 NMI signal, obviously.
1265 if (!smp_processor_id())
1266 value = APIC_DM_NMI;
1268 value = APIC_DM_NMI | APIC_LVT_MASKED;
1269 if (!lapic_is_integrated()) /* 82489DX */
1270 value |= APIC_LVT_LEVEL_TRIGGER;
1271 apic_write(APIC_LVT1, value);
1276 void __cpuinit end_local_APIC_setup(void)
1280 #ifdef CONFIG_X86_32
1283 /* Disable the local apic timer */
1284 value = apic_read(APIC_LVTT);
1285 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1286 apic_write(APIC_LVTT, value);
1290 setup_apic_nmi_watchdog(NULL);
1295 void check_x2apic(void)
1299 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1301 if (msr & X2APIC_ENABLE) {
1302 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1303 x2apic_preenabled = x2apic = 1;
1304 apic_ops = &x2apic_ops;
1308 void enable_x2apic(void)
1312 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1313 if (!(msr & X2APIC_ENABLE)) {
1314 pr_info("Enabling x2apic\n");
1315 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1319 void __init enable_IR_x2apic(void)
1321 #ifdef CONFIG_INTR_REMAP
1323 unsigned long flags;
1325 if (!cpu_has_x2apic)
1328 if (!x2apic_preenabled && disable_x2apic) {
1329 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1330 "because of nox2apic\n");
1334 if (x2apic_preenabled && disable_x2apic)
1335 panic("Bios already enabled x2apic, can't enforce nox2apic");
1337 if (!x2apic_preenabled && skip_ioapic_setup) {
1338 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1339 "because of skipping io-apic setup\n");
1343 ret = dmar_table_init();
1345 pr_info("dmar_table_init() failed with %d:\n", ret);
1347 if (x2apic_preenabled)
1348 panic("x2apic enabled by bios. But IR enabling failed");
1350 pr_info("Not enabling x2apic,Intr-remapping\n");
1354 local_irq_save(flags);
1357 ret = save_mask_IO_APIC_setup();
1359 pr_info("Saving IO-APIC state failed: %d\n", ret);
1363 ret = enable_intr_remapping(1);
1365 if (ret && x2apic_preenabled) {
1366 local_irq_restore(flags);
1367 panic("x2apic enabled by bios. But IR enabling failed");
1375 apic_ops = &x2apic_ops;
1382 * IR enabling failed
1384 restore_IO_APIC_setup();
1386 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1390 local_irq_restore(flags);
1393 if (!x2apic_preenabled)
1394 pr_info("Enabled x2apic and interrupt-remapping\n");
1396 pr_info("Enabled Interrupt-remapping\n");
1398 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1400 if (!cpu_has_x2apic)
1403 if (x2apic_preenabled)
1404 panic("x2apic enabled prior OS handover,"
1405 " enable CONFIG_INTR_REMAP");
1407 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1413 #endif /* HAVE_X2APIC */
1415 #ifdef CONFIG_X86_64
1417 * Detect and enable local APICs on non-SMP boards.
1418 * Original code written by Keir Fraser.
1419 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1420 * not correctly set up (usually the APIC timer won't work etc.)
1422 static int __init detect_init_APIC(void)
1424 if (!cpu_has_apic) {
1425 pr_info("No local APIC present\n");
1429 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1430 boot_cpu_physical_apicid = 0;
1435 * Detect and initialize APIC
1437 static int __init detect_init_APIC(void)
1441 /* Disabled by kernel option? */
1445 switch (boot_cpu_data.x86_vendor) {
1446 case X86_VENDOR_AMD:
1447 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1448 (boot_cpu_data.x86 == 15))
1451 case X86_VENDOR_INTEL:
1452 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1453 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1460 if (!cpu_has_apic) {
1462 * Over-ride BIOS and try to enable the local APIC only if
1463 * "lapic" specified.
1465 if (!force_enable_local_apic) {
1466 pr_info("Local APIC disabled by BIOS -- "
1467 "you can enable it with \"lapic\"\n");
1471 * Some BIOSes disable the local APIC in the APIC_BASE
1472 * MSR. This can only be done in software for Intel P6 or later
1473 * and AMD K7 (Model > 1) or later.
1475 rdmsr(MSR_IA32_APICBASE, l, h);
1476 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1477 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1478 l &= ~MSR_IA32_APICBASE_BASE;
1479 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1480 wrmsr(MSR_IA32_APICBASE, l, h);
1481 enabled_via_apicbase = 1;
1485 * The APIC feature bit should now be enabled
1488 features = cpuid_edx(1);
1489 if (!(features & (1 << X86_FEATURE_APIC))) {
1490 pr_warning("Could not enable APIC!\n");
1493 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1494 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1496 /* The BIOS may have set up the APIC at some other address */
1497 rdmsr(MSR_IA32_APICBASE, l, h);
1498 if (l & MSR_IA32_APICBASE_ENABLE)
1499 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1501 pr_info("Found and enabled local APIC!\n");
1508 pr_info("No local APIC present or hardware disabled\n");
1513 #ifdef CONFIG_X86_64
1514 void __init early_init_lapic_mapping(void)
1516 unsigned long phys_addr;
1519 * If no local APIC can be found then go out
1520 * : it means there is no mpatable and MADT
1522 if (!smp_found_config)
1525 phys_addr = mp_lapic_addr;
1527 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1528 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1529 APIC_BASE, phys_addr);
1532 * Fetch the APIC ID of the BSP in case we have a
1533 * default configuration (or the MP table is broken).
1535 boot_cpu_physical_apicid = read_apic_id();
1540 * init_apic_mappings - initialize APIC mappings
1542 void __init init_apic_mappings(void)
1546 boot_cpu_physical_apicid = read_apic_id();
1552 * If no local APIC can be found then set up a fake all
1553 * zeroes page to simulate the local APIC and another
1554 * one for the IO-APIC.
1556 if (!smp_found_config && detect_init_APIC()) {
1557 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1558 apic_phys = __pa(apic_phys);
1560 apic_phys = mp_lapic_addr;
1562 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1563 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1564 APIC_BASE, apic_phys);
1567 * Fetch the APIC ID of the BSP in case we have a
1568 * default configuration (or the MP table is broken).
1570 if (boot_cpu_physical_apicid == -1U)
1571 boot_cpu_physical_apicid = read_apic_id();
1575 * This initializes the IO-APIC and APIC hardware if this is
1578 int apic_version[MAX_APICS];
1580 int __init APIC_init_uniprocessor(void)
1583 pr_info("Apic disabled\n");
1586 #ifdef CONFIG_X86_64
1587 if (!cpu_has_apic) {
1589 pr_info("Apic disabled by BIOS\n");
1593 if (!smp_found_config && !cpu_has_apic)
1597 * Complain if the BIOS pretends there is one.
1599 if (!cpu_has_apic &&
1600 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1601 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1602 boot_cpu_physical_apicid);
1603 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1611 #ifdef CONFIG_X86_64
1612 setup_apic_routing();
1615 verify_local_APIC();
1618 #ifdef CONFIG_X86_64
1619 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1622 * Hack: In case of kdump, after a crash, kernel might be booting
1623 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1624 * might be zero if read from MP tables. Get it from LAPIC.
1626 # ifdef CONFIG_CRASH_DUMP
1627 boot_cpu_physical_apicid = read_apic_id();
1630 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1633 #ifdef CONFIG_X86_64
1635 * Now enable IO-APICs, actually call clear_IO_APIC
1636 * We need clear_IO_APIC before enabling vector on BP
1638 if (!skip_ioapic_setup && nr_ioapics)
1642 #ifdef CONFIG_X86_IO_APIC
1643 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1645 localise_nmi_watchdog();
1646 end_local_APIC_setup();
1648 #ifdef CONFIG_X86_IO_APIC
1649 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1651 # ifdef CONFIG_X86_64
1657 #ifdef CONFIG_X86_64
1658 setup_boot_APIC_clock();
1659 check_nmi_watchdog();
1668 * Local APIC interrupts
1672 * This interrupt should _never_ happen with our APIC/SMP architecture
1674 void smp_spurious_interrupt(struct pt_regs *regs)
1681 * Check if this really is a spurious interrupt and ACK it
1682 * if it is a vectored one. Just in case...
1683 * Spurious interrupts should not be ACKed.
1685 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1686 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1689 inc_irq_stat(irq_spurious_count);
1691 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1692 pr_info("spurious APIC interrupt on CPU#%d, "
1693 "should never happen.\n", smp_processor_id());
1698 * This interrupt should never happen with our APIC/SMP architecture
1700 void smp_error_interrupt(struct pt_regs *regs)
1706 /* First tickle the hardware, only then report what went on. -- REW */
1707 v = apic_read(APIC_ESR);
1708 apic_write(APIC_ESR, 0);
1709 v1 = apic_read(APIC_ESR);
1711 atomic_inc(&irq_err_count);
1714 * Here is what the APIC error bits mean:
1716 * 1: Receive CS error
1717 * 2: Send accept error
1718 * 3: Receive accept error
1720 * 5: Send illegal vector
1721 * 6: Received illegal vector
1722 * 7: Illegal register address
1724 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1725 smp_processor_id(), v , v1);
1730 * connect_bsp_APIC - attach the APIC to the interrupt system
1732 void __init connect_bsp_APIC(void)
1734 #ifdef CONFIG_X86_32
1737 * Do not trust the local APIC being empty at bootup.
1741 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1742 * local APIC to INT and NMI lines.
1744 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1745 "enabling APIC mode.\n");
1754 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1755 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1757 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1760 void disconnect_bsp_APIC(int virt_wire_setup)
1764 #ifdef CONFIG_X86_32
1767 * Put the board back into PIC mode (has an effect only on
1768 * certain older boards). Note that APIC interrupts, including
1769 * IPIs, won't work beyond this point! The only exception are
1772 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1773 "entering PIC mode.\n");
1780 /* Go back to Virtual Wire compatibility mode */
1782 /* For the spurious interrupt use vector F, and enable it */
1783 value = apic_read(APIC_SPIV);
1784 value &= ~APIC_VECTOR_MASK;
1785 value |= APIC_SPIV_APIC_ENABLED;
1787 apic_write(APIC_SPIV, value);
1789 if (!virt_wire_setup) {
1791 * For LVT0 make it edge triggered, active high,
1792 * external and enabled
1794 value = apic_read(APIC_LVT0);
1795 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1796 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1797 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1798 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1799 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1800 apic_write(APIC_LVT0, value);
1803 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1807 * For LVT1 make it edge triggered, active high,
1810 value = apic_read(APIC_LVT1);
1811 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1812 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1813 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1814 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1815 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1816 apic_write(APIC_LVT1, value);
1819 void __cpuinit generic_processor_info(int apicid, int version)
1826 if (version == 0x0) {
1827 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1828 "fixing up to 0x10. (tell your hw vendor)\n",
1832 apic_version[apicid] = version;
1834 if (num_processors >= nr_cpu_ids) {
1835 int max = nr_cpu_ids;
1836 int thiscpu = max + disabled_cpus;
1839 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1840 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1847 cpu = cpumask_next_zero(-1, cpu_present_mask);
1849 if (version != apic_version[boot_cpu_physical_apicid])
1851 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1852 apic_version[boot_cpu_physical_apicid], cpu, version);
1854 physid_set(apicid, phys_cpu_present_map);
1855 if (apicid == boot_cpu_physical_apicid) {
1857 * x86_bios_cpu_apicid is required to have processors listed
1858 * in same order as logical cpu numbers. Hence the first
1859 * entry is BSP, and so on.
1863 if (apicid > max_physical_apicid)
1864 max_physical_apicid = apicid;
1866 #ifdef CONFIG_X86_32
1868 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1869 * but we need to work other dependencies like SMP_SUSPEND etc
1870 * before this can be done without some confusion.
1871 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1872 * - Ashok Raj <ashok.raj@intel.com>
1874 if (max_physical_apicid >= 8) {
1875 switch (boot_cpu_data.x86_vendor) {
1876 case X86_VENDOR_INTEL:
1877 if (!APIC_XAPIC(version)) {
1881 /* If P4 and above fall through */
1882 case X86_VENDOR_AMD:
1888 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1889 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1890 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1893 set_cpu_possible(cpu, true);
1894 set_cpu_present(cpu, true);
1897 #ifdef CONFIG_X86_64
1898 int hard_smp_processor_id(void)
1900 return read_apic_id();
1911 * 'active' is true if the local APIC was enabled by us and
1912 * not the BIOS; this signifies that we are also responsible
1913 * for disabling it before entering apm/acpi suspend
1916 /* r/w apic fields */
1917 unsigned int apic_id;
1918 unsigned int apic_taskpri;
1919 unsigned int apic_ldr;
1920 unsigned int apic_dfr;
1921 unsigned int apic_spiv;
1922 unsigned int apic_lvtt;
1923 unsigned int apic_lvtpc;
1924 unsigned int apic_lvt0;
1925 unsigned int apic_lvt1;
1926 unsigned int apic_lvterr;
1927 unsigned int apic_tmict;
1928 unsigned int apic_tdcr;
1929 unsigned int apic_thmr;
1932 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1934 unsigned long flags;
1937 if (!apic_pm_state.active)
1940 maxlvt = lapic_get_maxlvt();
1942 apic_pm_state.apic_id = apic_read(APIC_ID);
1943 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1944 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1945 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1946 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1947 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1949 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1950 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1951 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1952 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1953 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1954 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1955 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1957 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1960 local_irq_save(flags);
1961 disable_local_APIC();
1962 local_irq_restore(flags);
1966 static int lapic_resume(struct sys_device *dev)
1969 unsigned long flags;
1972 if (!apic_pm_state.active)
1975 maxlvt = lapic_get_maxlvt();
1977 local_irq_save(flags);
1986 * Make sure the APICBASE points to the right address
1988 * FIXME! This will be wrong if we ever support suspend on
1989 * SMP! We'll need to do this as part of the CPU restore!
1991 rdmsr(MSR_IA32_APICBASE, l, h);
1992 l &= ~MSR_IA32_APICBASE_BASE;
1993 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1994 wrmsr(MSR_IA32_APICBASE, l, h);
1997 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1998 apic_write(APIC_ID, apic_pm_state.apic_id);
1999 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2000 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2001 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2002 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2003 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2004 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2005 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2007 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2010 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2011 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2012 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2013 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2014 apic_write(APIC_ESR, 0);
2015 apic_read(APIC_ESR);
2016 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2017 apic_write(APIC_ESR, 0);
2018 apic_read(APIC_ESR);
2020 local_irq_restore(flags);
2026 * This device has no shutdown method - fully functioning local APICs
2027 * are needed on every CPU up until machine_halt/restart/poweroff.
2030 static struct sysdev_class lapic_sysclass = {
2032 .resume = lapic_resume,
2033 .suspend = lapic_suspend,
2036 static struct sys_device device_lapic = {
2038 .cls = &lapic_sysclass,
2041 static void __cpuinit apic_pm_activate(void)
2043 apic_pm_state.active = 1;
2046 static int __init init_lapic_sysfs(void)
2052 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2054 error = sysdev_class_register(&lapic_sysclass);
2056 error = sysdev_register(&device_lapic);
2059 device_initcall(init_lapic_sysfs);
2061 #else /* CONFIG_PM */
2063 static void apic_pm_activate(void) { }
2065 #endif /* CONFIG_PM */
2067 #ifdef CONFIG_X86_64
2069 * apic_is_clustered_box() -- Check if we can expect good TSC
2071 * Thus far, the major user of this is IBM's Summit2 series:
2073 * Clustered boxes may have unsynced TSC problems if they are
2074 * multi-chassis. Use available data to take a good guess.
2075 * If in doubt, go HPET.
2077 __cpuinit int apic_is_clustered_box(void)
2079 int i, clusters, zeros;
2081 u16 *bios_cpu_apicid;
2082 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2085 * there is not this kind of box with AMD CPU yet.
2086 * Some AMD box with quadcore cpu and 8 sockets apicid
2087 * will be [4, 0x23] or [8, 0x27] could be thought to
2088 * vsmp box still need checking...
2090 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2093 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2094 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2096 for (i = 0; i < nr_cpu_ids; i++) {
2097 /* are we being called early in kernel startup? */
2098 if (bios_cpu_apicid) {
2099 id = bios_cpu_apicid[i];
2100 } else if (i < nr_cpu_ids) {
2102 id = per_cpu(x86_bios_cpu_apicid, i);
2108 if (id != BAD_APICID)
2109 __set_bit(APIC_CLUSTERID(id), clustermap);
2112 /* Problem: Partially populated chassis may not have CPUs in some of
2113 * the APIC clusters they have been allocated. Only present CPUs have
2114 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2115 * Since clusters are allocated sequentially, count zeros only if
2116 * they are bounded by ones.
2120 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2121 if (test_bit(i, clustermap)) {
2122 clusters += 1 + zeros;
2128 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2129 * not guaranteed to be synced between boards
2131 if (is_vsmp_box() && clusters > 1)
2135 * If clusters > 2, then should be multi-chassis.
2136 * May have to revisit this when multi-core + hyperthreaded CPUs come
2137 * out, but AFAIK this will work even for them.
2139 return (clusters > 2);
2144 * APIC command line parameters
2146 static int __init setup_disableapic(char *arg)
2149 setup_clear_cpu_cap(X86_FEATURE_APIC);
2152 early_param("disableapic", setup_disableapic);
2154 /* same as disableapic, for compatibility */
2155 static int __init setup_nolapic(char *arg)
2157 return setup_disableapic(arg);
2159 early_param("nolapic", setup_nolapic);
2161 static int __init parse_lapic_timer_c2_ok(char *arg)
2163 local_apic_timer_c2_ok = 1;
2166 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2168 static int __init parse_disable_apic_timer(char *arg)
2170 disable_apic_timer = 1;
2173 early_param("noapictimer", parse_disable_apic_timer);
2175 static int __init parse_nolapic_timer(char *arg)
2177 disable_apic_timer = 1;
2180 early_param("nolapic_timer", parse_nolapic_timer);
2182 static int __init apic_set_verbosity(char *arg)
2185 #ifdef CONFIG_X86_64
2186 skip_ioapic_setup = 0;
2192 if (strcmp("debug", arg) == 0)
2193 apic_verbosity = APIC_DEBUG;
2194 else if (strcmp("verbose", arg) == 0)
2195 apic_verbosity = APIC_VERBOSE;
2197 pr_warning("APIC Verbosity level %s not recognised"
2198 " use apic=verbose or apic=debug\n", arg);
2204 early_param("apic", apic_set_verbosity);
2206 static int __init lapic_insert_resource(void)
2211 /* Put local APIC into the resource map. */
2212 lapic_resource.start = apic_phys;
2213 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2214 insert_resource(&iomem_resource, &lapic_resource);
2220 * need call insert after e820_reserve_resources()
2221 * that is using request_resource
2223 late_initcall(lapic_insert_resource);