arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/current.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/bios.h>
  29 #include <asm/uv/uv.h>
  30 #include <asm/apic.h>
  31 #include <asm/ipi.h>
  32 #include <asm/smp.h>
  33 #include <asm/x86_init.h>
  34
  35 DEFINE_PER_CPU(int, x2apic_extra_bits);
  36
  37 static enum uv_system_type uv_system_type;
  38 static u64 gru_start_paddr, gru_end_paddr;
  39
  40 static inline bool is_GRU_range(u64 start, u64 end)
  41 {
  42         return start >= gru_start_paddr && end <= gru_end_paddr;
  43 }
  44
  45 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  46 {
  47         return is_ISA_range(start, end) || is_GRU_range(start, end);
  48 }
  49
  50 static int early_get_nodeid(void)
  51 {
  52         union uvh_node_id_u node_id;
  53         unsigned long *mmr;
  54
  55         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  56         node_id.v = *mmr;
  57         early_iounmap(mmr, sizeof(*mmr));
  58         return node_id.s.node_id;
  59 }
  60
  61 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  62 {
  63         if (!strcmp(oem_id, "SGI")) {
  64                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  65                 if (!strcmp(oem_table_id, "UVL"))
  66                         uv_system_type = UV_LEGACY_APIC;
  67                 else if (!strcmp(oem_table_id, "UVX"))
  68                         uv_system_type = UV_X2APIC;
  69                 else if (!strcmp(oem_table_id, "UVH")) {
  70                         __get_cpu_var(x2apic_extra_bits) =
  71                                 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1);
  72                         uv_system_type = UV_NON_UNIQUE_APIC;
  73                         return 1;
  74                 }
  75         }
  76         return 0;
  77 }
  78
  79 enum uv_system_type get_uv_system_type(void)
  80 {
  81         return uv_system_type;
  82 }
  83
  84 int is_uv_system(void)
  85 {
  86         return uv_system_type != UV_NONE;
  87 }
  88 EXPORT_SYMBOL_GPL(is_uv_system);
  89
  90 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  91 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  92
  93 struct uv_blade_info *uv_blade_info;
  94 EXPORT_SYMBOL_GPL(uv_blade_info);
  95
  96 short *uv_node_to_blade;
  97 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  98
  99 short *uv_cpu_to_blade;
 100 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 101
 102 short uv_possible_blades;
 103 EXPORT_SYMBOL_GPL(uv_possible_blades);
 104
 105 unsigned long sn_rtc_cycles_per_second;
 106 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 107
 108 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
 109
 110 static const struct cpumask *uv_target_cpus(void)
 111 {
 112         return cpumask_of(0);
 113 }
 114
 115 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 116 {
 117         cpumask_clear(retmask);
 118         cpumask_set_cpu(cpu, retmask);
 119 }
 120
 121 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 122 {
 123 #ifdef CONFIG_SMP
 124         unsigned long val;
 125         int pnode;
 126
 127         pnode = uv_apicid_to_pnode(phys_apicid);
 128         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 129             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 130             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 131             APIC_DM_INIT;
 132         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 133         mdelay(10);
 134
 135         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 136             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 137             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 138             APIC_DM_STARTUP;
 139         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 140
 141         atomic_set(&init_deasserted, 1);
 142 #endif
 143         return 0;
 144 }
 145
 146 static void uv_send_IPI_one(int cpu, int vector)
 147 {
 148         unsigned long apicid;
 149         int pnode;
 150
 151         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 152         pnode = uv_apicid_to_pnode(apicid);
 153         uv_hub_send_ipi(pnode, apicid, vector);
 154 }
 155
 156 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 157 {
 158         unsigned int cpu;
 159
 160         for_each_cpu(cpu, mask)
 161                 uv_send_IPI_one(cpu, vector);
 162 }
 163
 164 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 165 {
 166         unsigned int this_cpu = smp_processor_id();
 167         unsigned int cpu;
 168
 169         for_each_cpu(cpu, mask) {
 170                 if (cpu != this_cpu)
 171                         uv_send_IPI_one(cpu, vector);
 172         }
 173 }
 174
 175 static void uv_send_IPI_allbutself(int vector)
 176 {
 177         unsigned int this_cpu = smp_processor_id();
 178         unsigned int cpu;
 179
 180         for_each_online_cpu(cpu) {
 181                 if (cpu != this_cpu)
 182                         uv_send_IPI_one(cpu, vector);
 183         }
 184 }
 185
 186 static void uv_send_IPI_all(int vector)
 187 {
 188         uv_send_IPI_mask(cpu_online_mask, vector);
 189 }
 190
 191 static int uv_apic_id_registered(void)
 192 {
 193         return 1;
 194 }
 195
 196 static void uv_init_apic_ldr(void)
 197 {
 198 }
 199
 200 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 201 {
 202         /*
 203          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 204          * May as well be the first.
 205          */
 206         int cpu = cpumask_first(cpumask);
 207
 208         if ((unsigned)cpu < nr_cpu_ids)
 209                 return per_cpu(x86_cpu_to_apicid, cpu);
 210         else
 211                 return BAD_APICID;
 212 }
 213
 214 static unsigned int
 215 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 216                           const struct cpumask *andmask)
 217 {
 218         int cpu;
 219
 220         /*
 221          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 222          * May as well be the first.
 223          */
 224         for_each_cpu_and(cpu, cpumask, andmask) {
 225                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 226                         break;
 227         }
 228         return per_cpu(x86_cpu_to_apicid, cpu);
 229 }
 230
 231 static unsigned int x2apic_get_apic_id(unsigned long x)
 232 {
 233         unsigned int id;
 234
 235         WARN_ON(preemptible() && num_online_cpus() > 1);
 236         id = x | __get_cpu_var(x2apic_extra_bits);
 237
 238         return id;
 239 }
 240
 241 static unsigned long set_apic_id(unsigned int id)
 242 {
 243         unsigned long x;
 244
 245         /* maskout x2apic_extra_bits ? */
 246         x = id;
 247         return x;
 248 }
 249
 250 static unsigned int uv_read_apic_id(void)
 251 {
 252
 253         return x2apic_get_apic_id(apic_read(APIC_ID));
 254 }
 255
 256 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 257 {
 258         return uv_read_apic_id() >> index_msb;
 259 }
 260
 261 static void uv_send_IPI_self(int vector)
 262 {
 263         apic_write(APIC_SELF_IPI, vector);
 264 }
 265
 266 struct apic __refdata apic_x2apic_uv_x = {
 267
 268         .name                           = "UV large system",
 269         .probe                          = NULL,
 270         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 271         .apic_id_registered             = uv_apic_id_registered,
 272
 273         .irq_delivery_mode              = dest_Fixed,
 274         .irq_dest_mode                  = 0, /* physical */
 275
 276         .target_cpus                    = uv_target_cpus,
 277         .disable_esr                    = 0,
 278         .dest_logical                   = APIC_DEST_LOGICAL,
 279         .check_apicid_used              = NULL,
 280         .check_apicid_present           = NULL,
 281
 282         .vector_allocation_domain       = uv_vector_allocation_domain,
 283         .init_apic_ldr                  = uv_init_apic_ldr,
 284
 285         .ioapic_phys_id_map             = NULL,
 286         .setup_apic_routing             = NULL,
 287         .multi_timer_check              = NULL,
 288         .apicid_to_node                 = NULL,
 289         .cpu_to_logical_apicid          = NULL,
 290         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 291         .apicid_to_cpu_present          = NULL,
 292         .setup_portio_remap             = NULL,
 293         .check_phys_apicid_present      = default_check_phys_apicid_present,
 294         .enable_apic_mode               = NULL,
 295         .phys_pkg_id                    = uv_phys_pkg_id,
 296         .mps_oem_check                  = NULL,
 297
 298         .get_apic_id                    = x2apic_get_apic_id,
 299         .set_apic_id                    = set_apic_id,
 300         .apic_id_mask                   = 0xFFFFFFFFu,
 301
 302         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 303         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 304
 305         .send_IPI_mask                  = uv_send_IPI_mask,
 306         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 307         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 308         .send_IPI_all                   = uv_send_IPI_all,
 309         .send_IPI_self                  = uv_send_IPI_self,
 310
 311         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 312         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 313         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 314         .wait_for_init_deassert         = NULL,
 315         .smp_callin_clear_local_apic    = NULL,
 316         .inquire_remote_apic            = NULL,
 317
 318         .read                           = native_apic_msr_read,
 319         .write                          = native_apic_msr_write,
 320         .icr_read                       = native_x2apic_icr_read,
 321         .icr_write                      = native_x2apic_icr_write,
 322         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 323         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 324 };
 325
 326 static __cpuinit void set_x2apic_extra_bits(int pnode)
 327 {
 328         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 329 }
 330
 331 /*
 332  * Called on boot cpu.
 333  */
 334 static __init int boot_pnode_to_blade(int pnode)
 335 {
 336         int blade;
 337
 338         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 339                 if (pnode == uv_blade_info[blade].pnode)
 340                         return blade;
 341         BUG();
 342 }
 343
 344 struct redir_addr {
 345         unsigned long redirect;
 346         unsigned long alias;
 347 };
 348
 349 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 350
 351 static __initdata struct redir_addr redir_addrs[] = {
 352         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 353         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 354         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 355 };
 356
 357 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 358 {
 359         union uvh_si_alias0_overlay_config_u alias;
 360         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 361         int i;
 362
 363         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 364                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 365                 if (alias.s.enable && alias.s.base == 0) {
 366                         *size = (1UL << alias.s.m_alias);
 367                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 368                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 369                         return;
 370                 }
 371         }
 372         *base = *size = 0;
 373 }
 374
 375 enum map_type {map_wb, map_uc};
 376
 377 static __init void map_high(char *id, unsigned long base, int pshift,
 378                         int bshift, int max_pnode, enum map_type map_type)
 379 {
 380         unsigned long bytes, paddr;
 381
 382         paddr = base << pshift;
 383         bytes = (1UL << bshift) * (max_pnode + 1);
 384         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 385                                                 paddr + bytes);
 386         if (map_type == map_uc)
 387                 init_extra_mapping_uc(paddr, bytes);
 388         else
 389                 init_extra_mapping_wb(paddr, bytes);
 390
 391 }
 392 static __init void map_gru_high(int max_pnode)
 393 {
 394         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 395         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 396
 397         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 398         if (gru.s.enable) {
 399                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 400                 gru_start_paddr = ((u64)gru.s.base << shift);
 401                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 402
 403         }
 404 }
 405
 406 static __init void map_mmr_high(int max_pnode)
 407 {
 408         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 409         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 410
 411         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 412         if (mmr.s.enable)
 413                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 414 }
 415
 416 static __init void map_mmioh_high(int max_pnode)
 417 {
 418         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 419         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 420
 421         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 422         if (mmioh.s.enable)
 423                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 424                         max_pnode, map_uc);
 425 }
 426
 427 static __init void map_low_mmrs(void)
 428 {
 429         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 430         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 431 }
 432
 433 static __init void uv_rtc_init(void)
 434 {
 435         long status;
 436         u64 ticks_per_sec;
 437
 438         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 439                                         &ticks_per_sec);
 440         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 441                 printk(KERN_WARNING
 442                         "unable to determine platform RTC clock frequency, "
 443                         "guessing.\n");
 444                 /* BIOS gives wrong value for clock freq. so guess */
 445                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 446         } else
 447                 sn_rtc_cycles_per_second = ticks_per_sec;
 448 }
 449
 450 /*
 451  * percpu heartbeat timer
 452  */
 453 static void uv_heartbeat(unsigned long ignored)
 454 {
 455         struct timer_list *timer = &uv_hub_info->scir.timer;
 456         unsigned char bits = uv_hub_info->scir.state;
 457
 458         /* flip heartbeat bit */
 459         bits ^= SCIR_CPU_HEARTBEAT;
 460
 461         /* is this cpu idle? */
 462         if (idle_cpu(raw_smp_processor_id()))
 463                 bits &= ~SCIR_CPU_ACTIVITY;
 464         else
 465                 bits |= SCIR_CPU_ACTIVITY;
 466
 467         /* update system controller interface reg */
 468         uv_set_scir_bits(bits);
 469
 470         /* enable next timer period */
 471         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 472 }
 473
 474 static void __cpuinit uv_heartbeat_enable(int cpu)
 475 {
 476         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 477                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 478
 479                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 480                 setup_timer(timer, uv_heartbeat, cpu);
 481                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 482                 add_timer_on(timer, cpu);
 483                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 484         }
 485
 486         /* check boot cpu */
 487         if (!uv_cpu_hub_info(0)->scir.enabled)
 488                 uv_heartbeat_enable(0);
 489 }
 490
 491 #ifdef CONFIG_HOTPLUG_CPU
 492 static void __cpuinit uv_heartbeat_disable(int cpu)
 493 {
 494         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 495                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 496                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 497         }
 498         uv_set_cpu_scir_bits(cpu, 0xff);
 499 }
 500
 501 /*
 502  * cpu hotplug notifier
 503  */
 504 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 505                                        unsigned long action, void *hcpu)
 506 {
 507         long cpu = (long)hcpu;
 508
 509         switch (action) {
 510         case CPU_ONLINE:
 511                 uv_heartbeat_enable(cpu);
 512                 break;
 513         case CPU_DOWN_PREPARE:
 514                 uv_heartbeat_disable(cpu);
 515                 break;
 516         default:
 517                 break;
 518         }
 519         return NOTIFY_OK;
 520 }
 521
 522 static __init void uv_scir_register_cpu_notifier(void)
 523 {
 524         hotcpu_notifier(uv_scir_cpu_notify, 0);
 525 }
 526
 527 #else /* !CONFIG_HOTPLUG_CPU */
 528
 529 static __init void uv_scir_register_cpu_notifier(void)
 530 {
 531 }
 532
 533 static __init int uv_init_heartbeat(void)
 534 {
 535         int cpu;
 536
 537         if (is_uv_system())
 538                 for_each_online_cpu(cpu)
 539                         uv_heartbeat_enable(cpu);
 540         return 0;
 541 }
 542
 543 late_initcall(uv_init_heartbeat);
 544
 545 #endif /* !CONFIG_HOTPLUG_CPU */
 546
 547 /*
 548  * Called on each cpu to initialize the per_cpu UV data area.
 549  * FIXME: hotplug not supported yet
 550  */
 551 void __cpuinit uv_cpu_init(void)
 552 {
 553         /* CPU 0 initilization will be done via uv_system_init. */
 554         if (!uv_blade_info)
 555                 return;
 556
 557         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 558
 559         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 560                 set_x2apic_extra_bits(uv_hub_info->pnode);
 561 }
 562
 563
 564 void __init uv_system_init(void)
 565 {
 566         union uvh_si_addr_map_config_u m_n_config;
 567         union uvh_node_id_u node_id;
 568         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 569         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 570         int gnode_extra, max_pnode = 0;
 571         unsigned long mmr_base, present, paddr;
 572         unsigned short pnode_mask;
 573
 574         map_low_mmrs();
 575
 576         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 577         m_val = m_n_config.s.m_skt;
 578         n_val = m_n_config.s.n_skt;
 579         mmr_base =
 580             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 581             ~UV_MMR_ENABLE;
 582         pnode_mask = (1 << n_val) - 1;
 583         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 584         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 585         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 586         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 587                         n_val, m_val, gnode_upper, gnode_extra);
 588
 589         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 590
 591         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 592                 uv_possible_blades +=
 593                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 594         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 595
 596         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 597         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 598         BUG_ON(!uv_blade_info);
 599         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 600                 uv_blade_info[blade].memory_nid = -1;
 601
 602         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 603
 604         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 605         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 606         BUG_ON(!uv_node_to_blade);
 607         memset(uv_node_to_blade, 255, bytes);
 608
 609         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 610         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 611         BUG_ON(!uv_cpu_to_blade);
 612         memset(uv_cpu_to_blade, 255, bytes);
 613
 614         blade = 0;
 615         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 616                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 617                 for (j = 0; j < 64; j++) {
 618                         if (!test_bit(j, &present))
 619                                 continue;
 620                         uv_blade_info[blade].pnode = (i * 64 + j);
 621                         uv_blade_info[blade].nr_possible_cpus = 0;
 622                         uv_blade_info[blade].nr_online_cpus = 0;
 623                         blade++;
 624                 }
 625         }
 626
 627         uv_bios_init();
 628         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 629                             &sn_coherency_id, &sn_region_size);
 630         uv_rtc_init();
 631
 632         for_each_present_cpu(cpu) {
 633                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 634
 635                 nid = cpu_to_node(cpu);
 636                 pnode = uv_apicid_to_pnode(apicid);
 637                 blade = boot_pnode_to_blade(pnode);
 638                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 639                 uv_blade_info[blade].nr_possible_cpus++;
 640
 641                 /* Any node on the blade, else will contain -1. */
 642                 uv_blade_info[blade].memory_nid = nid;
 643
 644                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 645                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 646                 uv_cpu_hub_info(cpu)->m_val = m_val;
 647                 uv_cpu_hub_info(cpu)->n_val = n_val;
 648                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 649                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 650                 uv_cpu_hub_info(cpu)->pnode = pnode;
 651                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 652                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 653                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 654                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 655                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 656                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 657                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 658                 uv_node_to_blade[nid] = blade;
 659                 uv_cpu_to_blade[cpu] = blade;
 660                 max_pnode = max(pnode, max_pnode);
 661
 662                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
 663                         cpu, apicid, pnode, nid, lcpu, blade);
 664         }
 665
 666         /* Add blade/pnode info for nodes without cpus */
 667         for_each_online_node(nid) {
 668                 if (uv_node_to_blade[nid] >= 0)
 669                         continue;
 670                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 671                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 672                 pnode = (paddr >> m_val) & pnode_mask;
 673                 blade = boot_pnode_to_blade(pnode);
 674                 uv_node_to_blade[nid] = blade;
 675                 max_pnode = max(pnode, max_pnode);
 676         }
 677
 678         map_gru_high(max_pnode);
 679         map_mmr_high(max_pnode);
 680         map_mmioh_high(max_pnode);
 681
 682         uv_cpu_init();
 683         uv_scir_register_cpu_notifier();
 684         proc_mkdir("sgi_uv", NULL);
 685 }