2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug = -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock);
78 static DEFINE_RAW_SPINLOCK(vector_lock);
81 * # of IRQ routing registers
83 int nr_ioapic_registers[MAX_IO_APICS];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
136 struct irq_pin_list *pin;
138 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
147 static struct irq_cfg irq_cfgx[NR_IRQS];
150 int __init arch_early_irq_init(void)
153 struct irq_desc *desc;
158 if (!legacy_pic->nr_legacy_irqs) {
164 count = ARRAY_SIZE(irq_cfgx);
165 node = cpu_to_node(0);
167 for (i = 0; i < count; i++) {
168 desc = irq_to_desc(i);
169 desc->chip_data = &cfg[i];
170 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
171 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i < legacy_pic->nr_legacy_irqs) {
177 cfg[i].vector = IRQ0_VECTOR + i;
178 cpumask_set_cpu(0, cfg[i].domain);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg *irq_cfg(unsigned int irq)
188 struct irq_cfg *cfg = NULL;
189 struct irq_desc *desc;
191 desc = irq_to_desc(irq);
193 cfg = desc->chip_data;
198 static struct irq_cfg *get_one_free_irq_cfg(int node)
202 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
204 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
207 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
209 free_cpumask_var(cfg->domain);
218 int arch_init_chip_data(struct irq_desc *desc, int node)
222 cfg = desc->chip_data;
224 desc->chip_data = get_one_free_irq_cfg(node);
225 if (!desc->chip_data) {
226 printk(KERN_ERR "can not alloc irq_cfg\n");
234 /* for move_irq_desc */
236 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
238 struct irq_pin_list *old_entry, *head, *tail, *entry;
240 cfg->irq_2_pin = NULL;
241 old_entry = old_cfg->irq_2_pin;
245 entry = get_one_free_irq_2_pin(node);
249 entry->apic = old_entry->apic;
250 entry->pin = old_entry->pin;
253 old_entry = old_entry->next;
255 entry = get_one_free_irq_2_pin(node);
263 /* still use the old one */
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
270 old_entry = old_entry->next;
274 cfg->irq_2_pin = head;
277 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
279 struct irq_pin_list *entry, *next;
281 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
284 entry = old_cfg->irq_2_pin;
291 old_cfg->irq_2_pin = NULL;
294 void arch_init_copy_chip_data(struct irq_desc *old_desc,
295 struct irq_desc *desc, int node)
298 struct irq_cfg *old_cfg;
300 cfg = get_one_free_irq_cfg(node);
305 desc->chip_data = cfg;
307 old_cfg = old_desc->chip_data;
309 cfg->vector = old_cfg->vector;
310 cfg->move_in_progress = old_cfg->move_in_progress;
311 cpumask_copy(cfg->domain, old_cfg->domain);
312 cpumask_copy(cfg->old_domain, old_cfg->old_domain);
314 init_copy_irq_2_pin(old_cfg, cfg, node);
317 static void free_irq_cfg(struct irq_cfg *cfg)
319 free_cpumask_var(cfg->domain);
320 free_cpumask_var(cfg->old_domain);
324 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
326 struct irq_cfg *old_cfg, *cfg;
328 old_cfg = old_desc->chip_data;
329 cfg = desc->chip_data;
335 free_irq_2_pin(old_cfg, cfg);
336 free_irq_cfg(old_cfg);
337 old_desc->chip_data = NULL;
340 /* end for move_irq_desc */
343 struct irq_cfg *irq_cfg(unsigned int irq)
345 return irq < nr_irqs ? irq_cfgx + irq : NULL;
352 unsigned int unused[3];
354 unsigned int unused2[11];
358 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
360 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
361 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
364 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
366 struct io_apic __iomem *io_apic = io_apic_base(apic);
367 writel(vector, &io_apic->eoi);
370 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
372 struct io_apic __iomem *io_apic = io_apic_base(apic);
373 writel(reg, &io_apic->index);
374 return readl(&io_apic->data);
377 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
380 writel(reg, &io_apic->index);
381 writel(value, &io_apic->data);
385 * Re-write a value: to be used for read-modify-write
386 * cycles where the read already set up the index register.
388 * Older SiS APIC requires we rewrite the index register
390 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
392 struct io_apic __iomem *io_apic = io_apic_base(apic);
395 writel(reg, &io_apic->index);
396 writel(value, &io_apic->data);
399 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
401 struct irq_pin_list *entry;
404 raw_spin_lock_irqsave(&ioapic_lock, flags);
405 for_each_irq_pin(entry, cfg->irq_2_pin) {
410 reg = io_apic_read(entry->apic, 0x10 + pin*2);
411 /* Is the remote IRR bit set? */
412 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
413 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
417 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
423 struct { u32 w1, w2; };
424 struct IO_APIC_route_entry entry;
427 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
429 union entry_union eu;
431 raw_spin_lock_irqsave(&ioapic_lock, flags);
432 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
433 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
434 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
439 * When we write a new IO APIC routing entry, we need to write the high
440 * word first! If the mask bit in the low word is clear, we will enable
441 * the interrupt, and we need to make sure the entry is fully populated
442 * before that happens.
445 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
447 union entry_union eu = {{0, 0}};
450 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
451 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
454 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
457 raw_spin_lock_irqsave(&ioapic_lock, flags);
458 __ioapic_write_entry(apic, pin, e);
459 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
463 * When we mask an IO APIC routing entry, we need to write the low
464 * word first, in order to set the mask bit before we change the
467 static void ioapic_mask_entry(int apic, int pin)
470 union entry_union eu = { .entry.mask = 1 };
472 raw_spin_lock_irqsave(&ioapic_lock, flags);
473 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
474 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
475 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
479 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
480 * shared ISA-space IRQs, so we have to support them. We are super
481 * fast in the common case, and fast for shared ISA-space IRQs.
484 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
486 struct irq_pin_list **last, *entry;
488 /* don't allow duplicates */
489 last = &cfg->irq_2_pin;
490 for_each_irq_pin(entry, cfg->irq_2_pin) {
491 if (entry->apic == apic && entry->pin == pin)
496 entry = get_one_free_irq_2_pin(node);
498 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
509 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
511 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
512 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
516 * Reroute an IRQ to a different pin.
518 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
519 int oldapic, int oldpin,
520 int newapic, int newpin)
522 struct irq_pin_list *entry;
524 for_each_irq_pin(entry, cfg->irq_2_pin) {
525 if (entry->apic == oldapic && entry->pin == oldpin) {
526 entry->apic = newapic;
528 /* every one is different, right? */
533 /* old apic/pin didn't exist, so just add new ones */
534 add_pin_to_irq_node(cfg, node, newapic, newpin);
537 static void __io_apic_modify_irq(struct irq_pin_list *entry,
538 int mask_and, int mask_or,
539 void (*final)(struct irq_pin_list *entry))
541 unsigned int reg, pin;
544 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
547 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
552 static void io_apic_modify_irq(struct irq_cfg *cfg,
553 int mask_and, int mask_or,
554 void (*final)(struct irq_pin_list *entry))
556 struct irq_pin_list *entry;
558 for_each_irq_pin(entry, cfg->irq_2_pin)
559 __io_apic_modify_irq(entry, mask_and, mask_or, final);
562 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
564 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
565 IO_APIC_REDIR_MASKED, NULL);
568 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
570 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
571 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
574 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
576 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
579 static void io_apic_sync(struct irq_pin_list *entry)
582 * Synchronize the IO-APIC and the CPU by doing
583 * a dummy read from the IO-APIC
585 struct io_apic __iomem *io_apic;
586 io_apic = io_apic_base(entry->apic);
587 readl(&io_apic->data);
590 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
592 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
595 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
597 struct irq_cfg *cfg = desc->chip_data;
602 raw_spin_lock_irqsave(&ioapic_lock, flags);
603 __mask_IO_APIC_irq(cfg);
604 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
607 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
609 struct irq_cfg *cfg = desc->chip_data;
612 raw_spin_lock_irqsave(&ioapic_lock, flags);
613 __unmask_IO_APIC_irq(cfg);
614 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
617 static void mask_IO_APIC_irq(unsigned int irq)
619 struct irq_desc *desc = irq_to_desc(irq);
621 mask_IO_APIC_irq_desc(desc);
623 static void unmask_IO_APIC_irq(unsigned int irq)
625 struct irq_desc *desc = irq_to_desc(irq);
627 unmask_IO_APIC_irq_desc(desc);
630 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
632 struct IO_APIC_route_entry entry;
634 /* Check delivery_mode to be sure we're not clearing an SMI pin */
635 entry = ioapic_read_entry(apic, pin);
636 if (entry.delivery_mode == dest_SMI)
639 * Disable it in the IO-APIC irq-routing table:
641 ioapic_mask_entry(apic, pin);
644 static void clear_IO_APIC (void)
648 for (apic = 0; apic < nr_ioapics; apic++)
649 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
650 clear_IO_APIC_pin(apic, pin);
655 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
656 * specific CPU-side IRQs.
660 static int pirq_entries[MAX_PIRQS] = {
661 [0 ... MAX_PIRQS - 1] = -1
664 static int __init ioapic_pirq_setup(char *str)
667 int ints[MAX_PIRQS+1];
669 get_options(str, ARRAY_SIZE(ints), ints);
671 apic_printk(APIC_VERBOSE, KERN_INFO
672 "PIRQ redirection, working around broken MP-BIOS.\n");
674 if (ints[0] < MAX_PIRQS)
677 for (i = 0; i < max; i++) {
678 apic_printk(APIC_VERBOSE, KERN_DEBUG
679 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
681 * PIRQs are mapped upside down, usually.
683 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
688 __setup("pirq=", ioapic_pirq_setup);
689 #endif /* CONFIG_X86_32 */
691 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
694 struct IO_APIC_route_entry **ioapic_entries;
696 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 ioapic_entries[apic] =
703 kzalloc(sizeof(struct IO_APIC_route_entry) *
704 nr_ioapic_registers[apic], GFP_ATOMIC);
705 if (!ioapic_entries[apic])
709 return ioapic_entries;
713 kfree(ioapic_entries[apic]);
714 kfree(ioapic_entries);
720 * Saves all the IO-APIC RTE's
722 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
729 for (apic = 0; apic < nr_ioapics; apic++) {
730 if (!ioapic_entries[apic])
733 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
734 ioapic_entries[apic][pin] =
735 ioapic_read_entry(apic, pin);
742 * Mask all IO APIC entries.
744 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
751 for (apic = 0; apic < nr_ioapics; apic++) {
752 if (!ioapic_entries[apic])
755 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
756 struct IO_APIC_route_entry entry;
758 entry = ioapic_entries[apic][pin];
761 ioapic_write_entry(apic, pin, entry);
768 * Restore IO APIC entries which was saved in ioapic_entries.
770 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
777 for (apic = 0; apic < nr_ioapics; apic++) {
778 if (!ioapic_entries[apic])
781 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
782 ioapic_write_entry(apic, pin,
783 ioapic_entries[apic][pin]);
788 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
792 for (apic = 0; apic < nr_ioapics; apic++)
793 kfree(ioapic_entries[apic]);
795 kfree(ioapic_entries);
799 * Find the IRQ entry number of a certain pin.
801 static int find_irq_entry(int apic, int pin, int type)
805 for (i = 0; i < mp_irq_entries; i++)
806 if (mp_irqs[i].irqtype == type &&
807 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
808 mp_irqs[i].dstapic == MP_APIC_ALL) &&
809 mp_irqs[i].dstirq == pin)
816 * Find the pin to which IRQ[irq] (ISA) is connected
818 static int __init find_isa_irq_pin(int irq, int type)
822 for (i = 0; i < mp_irq_entries; i++) {
823 int lbus = mp_irqs[i].srcbus;
825 if (test_bit(lbus, mp_bus_not_pci) &&
826 (mp_irqs[i].irqtype == type) &&
827 (mp_irqs[i].srcbusirq == irq))
829 return mp_irqs[i].dstirq;
834 static int __init find_isa_irq_apic(int irq, int type)
838 for (i = 0; i < mp_irq_entries; i++) {
839 int lbus = mp_irqs[i].srcbus;
841 if (test_bit(lbus, mp_bus_not_pci) &&
842 (mp_irqs[i].irqtype == type) &&
843 (mp_irqs[i].srcbusirq == irq))
846 if (i < mp_irq_entries) {
848 for(apic = 0; apic < nr_ioapics; apic++) {
849 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
857 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
859 * EISA Edge/Level control register, ELCR
861 static int EISA_ELCR(unsigned int irq)
863 if (irq < legacy_pic->nr_legacy_irqs) {
864 unsigned int port = 0x4d0 + (irq >> 3);
865 return (inb(port) >> (irq & 7)) & 1;
867 apic_printk(APIC_VERBOSE, KERN_INFO
868 "Broken MPtable reports ISA irq %d\n", irq);
874 /* ISA interrupts are always polarity zero edge triggered,
875 * when listed as conforming in the MP table. */
877 #define default_ISA_trigger(idx) (0)
878 #define default_ISA_polarity(idx) (0)
880 /* EISA interrupts are always polarity zero and can be edge or level
881 * trigger depending on the ELCR value. If an interrupt is listed as
882 * EISA conforming in the MP table, that means its trigger type must
883 * be read in from the ELCR */
885 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
886 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
888 /* PCI interrupts are always polarity one level triggered,
889 * when listed as conforming in the MP table. */
891 #define default_PCI_trigger(idx) (1)
892 #define default_PCI_polarity(idx) (1)
894 /* MCA interrupts are always polarity zero level triggered,
895 * when listed as conforming in the MP table. */
897 #define default_MCA_trigger(idx) (1)
898 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
900 static int MPBIOS_polarity(int idx)
902 int bus = mp_irqs[idx].srcbus;
906 * Determine IRQ line polarity (high active or low active):
908 switch (mp_irqs[idx].irqflag & 3)
910 case 0: /* conforms, ie. bus-type dependent polarity */
911 if (test_bit(bus, mp_bus_not_pci))
912 polarity = default_ISA_polarity(idx);
914 polarity = default_PCI_polarity(idx);
916 case 1: /* high active */
921 case 2: /* reserved */
923 printk(KERN_WARNING "broken BIOS!!\n");
927 case 3: /* low active */
932 default: /* invalid */
934 printk(KERN_WARNING "broken BIOS!!\n");
942 static int MPBIOS_trigger(int idx)
944 int bus = mp_irqs[idx].srcbus;
948 * Determine IRQ trigger mode (edge or level sensitive):
950 switch ((mp_irqs[idx].irqflag>>2) & 3)
952 case 0: /* conforms, ie. bus-type dependent */
953 if (test_bit(bus, mp_bus_not_pci))
954 trigger = default_ISA_trigger(idx);
956 trigger = default_PCI_trigger(idx);
957 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
958 switch (mp_bus_id_to_type[bus]) {
959 case MP_BUS_ISA: /* ISA pin */
961 /* set before the switch */
964 case MP_BUS_EISA: /* EISA pin */
966 trigger = default_EISA_trigger(idx);
969 case MP_BUS_PCI: /* PCI pin */
971 /* set before the switch */
974 case MP_BUS_MCA: /* MCA pin */
976 trigger = default_MCA_trigger(idx);
981 printk(KERN_WARNING "broken BIOS!!\n");
993 case 2: /* reserved */
995 printk(KERN_WARNING "broken BIOS!!\n");
1004 default: /* invalid */
1006 printk(KERN_WARNING "broken BIOS!!\n");
1014 static inline int irq_polarity(int idx)
1016 return MPBIOS_polarity(idx);
1019 static inline int irq_trigger(int idx)
1021 return MPBIOS_trigger(idx);
1024 static int pin_2_irq(int idx, int apic, int pin)
1027 int bus = mp_irqs[idx].srcbus;
1030 * Debugging check, we are in big trouble if this message pops up!
1032 if (mp_irqs[idx].dstirq != pin)
1033 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1035 if (test_bit(bus, mp_bus_not_pci)) {
1036 irq = mp_irqs[idx].srcbusirq;
1038 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
1040 if (gsi >= NR_IRQS_LEGACY)
1043 irq = gsi_top + gsi;
1046 #ifdef CONFIG_X86_32
1048 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1050 if ((pin >= 16) && (pin <= 23)) {
1051 if (pirq_entries[pin-16] != -1) {
1052 if (!pirq_entries[pin-16]) {
1053 apic_printk(APIC_VERBOSE, KERN_DEBUG
1054 "disabling PIRQ%d\n", pin-16);
1056 irq = pirq_entries[pin-16];
1057 apic_printk(APIC_VERBOSE, KERN_DEBUG
1058 "using PIRQ%d -> IRQ %d\n",
1069 * Find a specific PCI IRQ entry.
1070 * Not an __init, possibly needed by modules
1072 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1073 struct io_apic_irq_attr *irq_attr)
1075 int apic, i, best_guess = -1;
1077 apic_printk(APIC_DEBUG,
1078 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1080 if (test_bit(bus, mp_bus_not_pci)) {
1081 apic_printk(APIC_VERBOSE,
1082 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1085 for (i = 0; i < mp_irq_entries; i++) {
1086 int lbus = mp_irqs[i].srcbus;
1088 for (apic = 0; apic < nr_ioapics; apic++)
1089 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1090 mp_irqs[i].dstapic == MP_APIC_ALL)
1093 if (!test_bit(lbus, mp_bus_not_pci) &&
1094 !mp_irqs[i].irqtype &&
1096 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1097 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1099 if (!(apic || IO_APIC_IRQ(irq)))
1102 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1103 set_io_apic_irq_attr(irq_attr, apic,
1110 * Use the first all-but-pin matching entry as a
1111 * best-guess fuzzy result for broken mptables.
1113 if (best_guess < 0) {
1114 set_io_apic_irq_attr(irq_attr, apic,
1124 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1126 void lock_vector_lock(void)
1128 /* Used to the online set of cpus does not change
1129 * during assign_irq_vector.
1131 raw_spin_lock(&vector_lock);
1134 void unlock_vector_lock(void)
1136 raw_spin_unlock(&vector_lock);
1140 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1143 * NOTE! The local APIC isn't very good at handling
1144 * multiple interrupts at the same interrupt level.
1145 * As the interrupt level is determined by taking the
1146 * vector number and shifting that right by 4, we
1147 * want to spread these out a bit so that they don't
1148 * all fall in the same interrupt level.
1150 * Also, we've got to be careful not to trash gate
1151 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1153 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1154 static int current_offset = VECTOR_OFFSET_START % 8;
1155 unsigned int old_vector;
1157 cpumask_var_t tmp_mask;
1159 if (cfg->move_in_progress)
1162 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1165 old_vector = cfg->vector;
1167 cpumask_and(tmp_mask, mask, cpu_online_mask);
1168 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1169 if (!cpumask_empty(tmp_mask)) {
1170 free_cpumask_var(tmp_mask);
1175 /* Only try and allocate irqs on cpus that are present */
1177 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1181 apic->vector_allocation_domain(cpu, tmp_mask);
1183 vector = current_vector;
1184 offset = current_offset;
1187 if (vector >= first_system_vector) {
1188 /* If out of vectors on large boxen, must share them. */
1189 offset = (offset + 1) % 8;
1190 vector = FIRST_EXTERNAL_VECTOR + offset;
1192 if (unlikely(current_vector == vector))
1195 if (test_bit(vector, used_vectors))
1198 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1199 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1202 current_vector = vector;
1203 current_offset = offset;
1205 cfg->move_in_progress = 1;
1206 cpumask_copy(cfg->old_domain, cfg->domain);
1208 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1209 per_cpu(vector_irq, new_cpu)[vector] = irq;
1210 cfg->vector = vector;
1211 cpumask_copy(cfg->domain, tmp_mask);
1215 free_cpumask_var(tmp_mask);
1219 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1222 unsigned long flags;
1224 raw_spin_lock_irqsave(&vector_lock, flags);
1225 err = __assign_irq_vector(irq, cfg, mask);
1226 raw_spin_unlock_irqrestore(&vector_lock, flags);
1230 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1234 BUG_ON(!cfg->vector);
1236 vector = cfg->vector;
1237 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1238 per_cpu(vector_irq, cpu)[vector] = -1;
1241 cpumask_clear(cfg->domain);
1243 if (likely(!cfg->move_in_progress))
1245 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1246 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1248 if (per_cpu(vector_irq, cpu)[vector] != irq)
1250 per_cpu(vector_irq, cpu)[vector] = -1;
1254 cfg->move_in_progress = 0;
1257 void __setup_vector_irq(int cpu)
1259 /* Initialize vector_irq on a new cpu */
1261 struct irq_cfg *cfg;
1262 struct irq_desc *desc;
1265 * vector_lock will make sure that we don't run into irq vector
1266 * assignments that might be happening on another cpu in parallel,
1267 * while we setup our initial vector to irq mappings.
1269 raw_spin_lock(&vector_lock);
1270 /* Mark the inuse vectors */
1271 for_each_irq_desc(irq, desc) {
1272 cfg = desc->chip_data;
1275 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1276 * will be part of the irq_cfg's domain.
1278 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1279 cpumask_set_cpu(cpu, cfg->domain);
1281 if (!cpumask_test_cpu(cpu, cfg->domain))
1283 vector = cfg->vector;
1284 per_cpu(vector_irq, cpu)[vector] = irq;
1286 /* Mark the free vectors */
1287 for (vector = 0; vector < NR_VECTORS; ++vector) {
1288 irq = per_cpu(vector_irq, cpu)[vector];
1293 if (!cpumask_test_cpu(cpu, cfg->domain))
1294 per_cpu(vector_irq, cpu)[vector] = -1;
1296 raw_spin_unlock(&vector_lock);
1299 static struct irq_chip ioapic_chip;
1300 static struct irq_chip ir_ioapic_chip;
1302 #define IOAPIC_AUTO -1
1303 #define IOAPIC_EDGE 0
1304 #define IOAPIC_LEVEL 1
1306 #ifdef CONFIG_X86_32
1307 static inline int IO_APIC_irq_trigger(int irq)
1311 for (apic = 0; apic < nr_ioapics; apic++) {
1312 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1313 idx = find_irq_entry(apic, pin, mp_INT);
1314 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1315 return irq_trigger(idx);
1319 * nonexistent IRQs are edge default
1324 static inline int IO_APIC_irq_trigger(int irq)
1330 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1333 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1334 trigger == IOAPIC_LEVEL)
1335 desc->status |= IRQ_LEVEL;
1337 desc->status &= ~IRQ_LEVEL;
1339 if (irq_remapped(irq)) {
1340 desc->status |= IRQ_MOVE_PCNTXT;
1342 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1346 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1347 handle_edge_irq, "edge");
1351 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1352 trigger == IOAPIC_LEVEL)
1353 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1357 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1358 handle_edge_irq, "edge");
1361 int setup_ioapic_entry(int apic_id, int irq,
1362 struct IO_APIC_route_entry *entry,
1363 unsigned int destination, int trigger,
1364 int polarity, int vector, int pin)
1367 * add it to the IO-APIC irq-routing table:
1369 memset(entry,0,sizeof(*entry));
1371 if (intr_remapping_enabled) {
1372 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1374 struct IR_IO_APIC_route_entry *ir_entry =
1375 (struct IR_IO_APIC_route_entry *) entry;
1379 panic("No mapping iommu for ioapic %d\n", apic_id);
1381 index = alloc_irte(iommu, irq, 1);
1383 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1385 memset(&irte, 0, sizeof(irte));
1388 irte.dst_mode = apic->irq_dest_mode;
1390 * Trigger mode in the IRTE will always be edge, and the
1391 * actual level or edge trigger will be setup in the IO-APIC
1392 * RTE. This will help simplify level triggered irq migration.
1393 * For more details, see the comments above explainig IO-APIC
1394 * irq migration in the presence of interrupt-remapping.
1396 irte.trigger_mode = 0;
1397 irte.dlvry_mode = apic->irq_delivery_mode;
1398 irte.vector = vector;
1399 irte.dest_id = IRTE_DEST(destination);
1401 /* Set source-id of interrupt request */
1402 set_ioapic_sid(&irte, apic_id);
1404 modify_irte(irq, &irte);
1406 ir_entry->index2 = (index >> 15) & 0x1;
1408 ir_entry->format = 1;
1409 ir_entry->index = (index & 0x7fff);
1411 * IO-APIC RTE will be configured with virtual vector.
1412 * irq handler will do the explicit EOI to the io-apic.
1414 ir_entry->vector = pin;
1416 entry->delivery_mode = apic->irq_delivery_mode;
1417 entry->dest_mode = apic->irq_dest_mode;
1418 entry->dest = destination;
1419 entry->vector = vector;
1422 entry->mask = 0; /* enable IRQ */
1423 entry->trigger = trigger;
1424 entry->polarity = polarity;
1426 /* Mask level triggered irqs.
1427 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1434 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1435 int trigger, int polarity)
1437 struct irq_cfg *cfg;
1438 struct IO_APIC_route_entry entry;
1441 if (!IO_APIC_IRQ(irq))
1444 cfg = desc->chip_data;
1447 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1448 * controllers like 8259. Now that IO-APIC can handle this irq, update
1451 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1452 apic->vector_allocation_domain(0, cfg->domain);
1454 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1457 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1459 apic_printk(APIC_VERBOSE,KERN_DEBUG
1460 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1461 "IRQ %d Mode:%i Active:%i)\n",
1462 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1463 irq, trigger, polarity);
1466 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1467 dest, trigger, polarity, cfg->vector, pin)) {
1468 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1469 mp_ioapics[apic_id].apicid, pin);
1470 __clear_irq_vector(irq, cfg);
1474 ioapic_register_intr(irq, desc, trigger);
1475 if (irq < legacy_pic->nr_legacy_irqs)
1476 legacy_pic->chip->mask(irq);
1478 ioapic_write_entry(apic_id, pin, entry);
1482 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1483 } mp_ioapic_routing[MAX_IO_APICS];
1485 static void __init setup_IO_APIC_irqs(void)
1487 int apic_id, pin, idx, irq;
1489 struct irq_desc *desc;
1490 struct irq_cfg *cfg;
1491 int node = cpu_to_node(0);
1493 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1495 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1496 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1497 idx = find_irq_entry(apic_id, pin, mp_INT);
1501 apic_printk(APIC_VERBOSE,
1502 KERN_DEBUG " %d-%d",
1503 mp_ioapics[apic_id].apicid, pin);
1505 apic_printk(APIC_VERBOSE, " %d-%d",
1506 mp_ioapics[apic_id].apicid, pin);
1510 apic_printk(APIC_VERBOSE,
1511 " (apicid-pin) not connected\n");
1515 irq = pin_2_irq(idx, apic_id, pin);
1517 if ((apic_id > 0) && (irq > 16))
1521 * Skip the timer IRQ if there's a quirk handler
1522 * installed and if it returns 1:
1524 if (apic->multi_timer_check &&
1525 apic->multi_timer_check(apic_id, irq))
1528 desc = irq_to_desc_alloc_node(irq, node);
1530 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1533 cfg = desc->chip_data;
1534 add_pin_to_irq_node(cfg, node, apic_id, pin);
1536 * don't mark it in pin_programmed, so later acpi could
1537 * set it correctly when irq < 16
1539 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1540 irq_trigger(idx), irq_polarity(idx));
1544 apic_printk(APIC_VERBOSE,
1545 " (apicid-pin) not connected\n");
1549 * for the gsit that is not in first ioapic
1550 * but could not use acpi_register_gsi()
1551 * like some special sci in IBM x3330
1553 void setup_IO_APIC_irq_extra(u32 gsi)
1555 int apic_id = 0, pin, idx, irq;
1556 int node = cpu_to_node(0);
1557 struct irq_desc *desc;
1558 struct irq_cfg *cfg;
1561 * Convert 'gsi' to 'ioapic.pin'.
1563 apic_id = mp_find_ioapic(gsi);
1567 pin = mp_find_ioapic_pin(apic_id, gsi);
1568 idx = find_irq_entry(apic_id, pin, mp_INT);
1572 irq = pin_2_irq(idx, apic_id, pin);
1573 #ifdef CONFIG_SPARSE_IRQ
1574 desc = irq_to_desc(irq);
1578 desc = irq_to_desc_alloc_node(irq, node);
1580 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1584 cfg = desc->chip_data;
1585 add_pin_to_irq_node(cfg, node, apic_id, pin);
1587 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1588 pr_debug("Pin %d-%d already programmed\n",
1589 mp_ioapics[apic_id].apicid, pin);
1592 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1594 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1595 irq_trigger(idx), irq_polarity(idx));
1599 * Set up the timer pin, possibly with the 8259A-master behind.
1601 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1604 struct IO_APIC_route_entry entry;
1606 if (intr_remapping_enabled)
1609 memset(&entry, 0, sizeof(entry));
1612 * We use logical delivery to get the timer IRQ
1615 entry.dest_mode = apic->irq_dest_mode;
1616 entry.mask = 0; /* don't mask IRQ for edge */
1617 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1618 entry.delivery_mode = apic->irq_delivery_mode;
1621 entry.vector = vector;
1624 * The timer IRQ doesn't have to know that behind the
1625 * scene we may have a 8259A-master in AEOI mode ...
1627 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1630 * Add it to the IO-APIC irq-routing table:
1632 ioapic_write_entry(apic_id, pin, entry);
1636 __apicdebuginit(void) print_IO_APIC(void)
1639 union IO_APIC_reg_00 reg_00;
1640 union IO_APIC_reg_01 reg_01;
1641 union IO_APIC_reg_02 reg_02;
1642 union IO_APIC_reg_03 reg_03;
1643 unsigned long flags;
1644 struct irq_cfg *cfg;
1645 struct irq_desc *desc;
1648 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1649 for (i = 0; i < nr_ioapics; i++)
1650 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1651 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1654 * We are a bit conservative about what we expect. We have to
1655 * know about every hardware change ASAP.
1657 printk(KERN_INFO "testing the IO APIC.......................\n");
1659 for (apic = 0; apic < nr_ioapics; apic++) {
1661 raw_spin_lock_irqsave(&ioapic_lock, flags);
1662 reg_00.raw = io_apic_read(apic, 0);
1663 reg_01.raw = io_apic_read(apic, 1);
1664 if (reg_01.bits.version >= 0x10)
1665 reg_02.raw = io_apic_read(apic, 2);
1666 if (reg_01.bits.version >= 0x20)
1667 reg_03.raw = io_apic_read(apic, 3);
1668 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1671 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1672 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1673 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1674 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1675 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1677 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1678 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1680 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1681 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1684 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1685 * but the value of reg_02 is read as the previous read register
1686 * value, so ignore it if reg_02 == reg_01.
1688 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1689 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1690 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1694 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1695 * or reg_03, but the value of reg_0[23] is read as the previous read
1696 * register value, so ignore it if reg_03 == reg_0[12].
1698 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1699 reg_03.raw != reg_01.raw) {
1700 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1701 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1704 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1706 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1707 " Stat Dmod Deli Vect:\n");
1709 for (i = 0; i <= reg_01.bits.entries; i++) {
1710 struct IO_APIC_route_entry entry;
1712 entry = ioapic_read_entry(apic, i);
1714 printk(KERN_DEBUG " %02x %03X ",
1719 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1724 entry.delivery_status,
1726 entry.delivery_mode,
1731 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1732 for_each_irq_desc(irq, desc) {
1733 struct irq_pin_list *entry;
1735 cfg = desc->chip_data;
1738 entry = cfg->irq_2_pin;
1741 printk(KERN_DEBUG "IRQ%d ", irq);
1742 for_each_irq_pin(entry, cfg->irq_2_pin)
1743 printk("-> %d:%d", entry->apic, entry->pin);
1747 printk(KERN_INFO ".................................... done.\n");
1752 __apicdebuginit(void) print_APIC_field(int base)
1758 for (i = 0; i < 8; i++)
1759 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1761 printk(KERN_CONT "\n");
1764 __apicdebuginit(void) print_local_APIC(void *dummy)
1766 unsigned int i, v, ver, maxlvt;
1769 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1770 smp_processor_id(), hard_smp_processor_id());
1771 v = apic_read(APIC_ID);
1772 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1773 v = apic_read(APIC_LVR);
1774 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1775 ver = GET_APIC_VERSION(v);
1776 maxlvt = lapic_get_maxlvt();
1778 v = apic_read(APIC_TASKPRI);
1779 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1781 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1782 if (!APIC_XAPIC(ver)) {
1783 v = apic_read(APIC_ARBPRI);
1784 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1785 v & APIC_ARBPRI_MASK);
1787 v = apic_read(APIC_PROCPRI);
1788 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1792 * Remote read supported only in the 82489DX and local APIC for
1793 * Pentium processors.
1795 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1796 v = apic_read(APIC_RRR);
1797 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1800 v = apic_read(APIC_LDR);
1801 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1802 if (!x2apic_enabled()) {
1803 v = apic_read(APIC_DFR);
1804 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1806 v = apic_read(APIC_SPIV);
1807 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1809 printk(KERN_DEBUG "... APIC ISR field:\n");
1810 print_APIC_field(APIC_ISR);
1811 printk(KERN_DEBUG "... APIC TMR field:\n");
1812 print_APIC_field(APIC_TMR);
1813 printk(KERN_DEBUG "... APIC IRR field:\n");
1814 print_APIC_field(APIC_IRR);
1816 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1817 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1818 apic_write(APIC_ESR, 0);
1820 v = apic_read(APIC_ESR);
1821 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1824 icr = apic_icr_read();
1825 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1826 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1828 v = apic_read(APIC_LVTT);
1829 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1831 if (maxlvt > 3) { /* PC is LVT#4. */
1832 v = apic_read(APIC_LVTPC);
1833 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1835 v = apic_read(APIC_LVT0);
1836 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1837 v = apic_read(APIC_LVT1);
1838 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1840 if (maxlvt > 2) { /* ERR is LVT#3. */
1841 v = apic_read(APIC_LVTERR);
1842 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1845 v = apic_read(APIC_TMICT);
1846 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1847 v = apic_read(APIC_TMCCT);
1848 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1849 v = apic_read(APIC_TDCR);
1850 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1852 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1853 v = apic_read(APIC_EFEAT);
1854 maxlvt = (v >> 16) & 0xff;
1855 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1856 v = apic_read(APIC_ECTRL);
1857 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1858 for (i = 0; i < maxlvt; i++) {
1859 v = apic_read(APIC_EILVTn(i));
1860 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1866 __apicdebuginit(void) print_local_APICs(int maxcpu)
1874 for_each_online_cpu(cpu) {
1877 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1882 __apicdebuginit(void) print_PIC(void)
1885 unsigned long flags;
1887 if (!legacy_pic->nr_legacy_irqs)
1890 printk(KERN_DEBUG "\nprinting PIC contents\n");
1892 raw_spin_lock_irqsave(&i8259A_lock, flags);
1894 v = inb(0xa1) << 8 | inb(0x21);
1895 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1897 v = inb(0xa0) << 8 | inb(0x20);
1898 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1902 v = inb(0xa0) << 8 | inb(0x20);
1906 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1908 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1910 v = inb(0x4d1) << 8 | inb(0x4d0);
1911 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1914 static int __initdata show_lapic = 1;
1915 static __init int setup_show_lapic(char *arg)
1919 if (strcmp(arg, "all") == 0) {
1920 show_lapic = CONFIG_NR_CPUS;
1922 get_option(&arg, &num);
1929 __setup("show_lapic=", setup_show_lapic);
1931 __apicdebuginit(int) print_ICs(void)
1933 if (apic_verbosity == APIC_QUIET)
1938 /* don't print out if apic is not there */
1939 if (!cpu_has_apic && !apic_from_smp_config())
1942 print_local_APICs(show_lapic);
1948 fs_initcall(print_ICs);
1951 /* Where if anywhere is the i8259 connect in external int mode */
1952 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1954 void __init enable_IO_APIC(void)
1956 int i8259_apic, i8259_pin;
1959 if (!legacy_pic->nr_legacy_irqs)
1962 for(apic = 0; apic < nr_ioapics; apic++) {
1964 /* See if any of the pins is in ExtINT mode */
1965 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1966 struct IO_APIC_route_entry entry;
1967 entry = ioapic_read_entry(apic, pin);
1969 /* If the interrupt line is enabled and in ExtInt mode
1970 * I have found the pin where the i8259 is connected.
1972 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1973 ioapic_i8259.apic = apic;
1974 ioapic_i8259.pin = pin;
1980 /* Look to see what if the MP table has reported the ExtINT */
1981 /* If we could not find the appropriate pin by looking at the ioapic
1982 * the i8259 probably is not connected the ioapic but give the
1983 * mptable a chance anyway.
1985 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1986 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1987 /* Trust the MP table if nothing is setup in the hardware */
1988 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1989 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1990 ioapic_i8259.pin = i8259_pin;
1991 ioapic_i8259.apic = i8259_apic;
1993 /* Complain if the MP table and the hardware disagree */
1994 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1995 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1997 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2001 * Do not trust the IO-APIC being empty at bootup
2007 * Not an __init, needed by the reboot code
2009 void disable_IO_APIC(void)
2012 * Clear the IO-APIC before rebooting:
2016 if (!legacy_pic->nr_legacy_irqs)
2020 * If the i8259 is routed through an IOAPIC
2021 * Put that IOAPIC in virtual wire mode
2022 * so legacy interrupts can be delivered.
2024 * With interrupt-remapping, for now we will use virtual wire A mode,
2025 * as virtual wire B is little complex (need to configure both
2026 * IOAPIC RTE aswell as interrupt-remapping table entry).
2027 * As this gets called during crash dump, keep this simple for now.
2029 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2030 struct IO_APIC_route_entry entry;
2032 memset(&entry, 0, sizeof(entry));
2033 entry.mask = 0; /* Enabled */
2034 entry.trigger = 0; /* Edge */
2036 entry.polarity = 0; /* High */
2037 entry.delivery_status = 0;
2038 entry.dest_mode = 0; /* Physical */
2039 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2041 entry.dest = read_apic_id();
2044 * Add it to the IO-APIC irq-routing table:
2046 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2050 * Use virtual wire A mode when interrupt remapping is enabled.
2052 if (cpu_has_apic || apic_from_smp_config())
2053 disconnect_bsp_APIC(!intr_remapping_enabled &&
2054 ioapic_i8259.pin != -1);
2057 #ifdef CONFIG_X86_32
2059 * function to set the IO-APIC physical IDs based on the
2060 * values stored in the MPC table.
2062 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2065 void __init setup_ioapic_ids_from_mpc(void)
2067 union IO_APIC_reg_00 reg_00;
2068 physid_mask_t phys_id_present_map;
2071 unsigned char old_id;
2072 unsigned long flags;
2077 * Don't check I/O APIC IDs for xAPIC systems. They have
2078 * no meaning without the serial APIC bus.
2080 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2081 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2084 * This is broken; anything with a real cpu count has to
2085 * circumvent this idiocy regardless.
2087 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2090 * Set the IOAPIC ID to the value stored in the MPC table.
2092 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2094 /* Read the register 0 value */
2095 raw_spin_lock_irqsave(&ioapic_lock, flags);
2096 reg_00.raw = io_apic_read(apic_id, 0);
2097 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2099 old_id = mp_ioapics[apic_id].apicid;
2101 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2102 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2103 apic_id, mp_ioapics[apic_id].apicid);
2104 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2106 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2110 * Sanity check, is the ID really free? Every APIC in a
2111 * system must have a unique ID or we get lots of nice
2112 * 'stuck on smp_invalidate_needed IPI wait' messages.
2114 if (apic->check_apicid_used(&phys_id_present_map,
2115 mp_ioapics[apic_id].apicid)) {
2116 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2117 apic_id, mp_ioapics[apic_id].apicid);
2118 for (i = 0; i < get_physical_broadcast(); i++)
2119 if (!physid_isset(i, phys_id_present_map))
2121 if (i >= get_physical_broadcast())
2122 panic("Max APIC ID exceeded!\n");
2123 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2125 physid_set(i, phys_id_present_map);
2126 mp_ioapics[apic_id].apicid = i;
2129 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2130 apic_printk(APIC_VERBOSE, "Setting %d in the "
2131 "phys_id_present_map\n",
2132 mp_ioapics[apic_id].apicid);
2133 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2138 * We need to adjust the IRQ routing table
2139 * if the ID changed.
2141 if (old_id != mp_ioapics[apic_id].apicid)
2142 for (i = 0; i < mp_irq_entries; i++)
2143 if (mp_irqs[i].dstapic == old_id)
2145 = mp_ioapics[apic_id].apicid;
2148 * Read the right value from the MPC table and
2149 * write it into the ID register.
2151 apic_printk(APIC_VERBOSE, KERN_INFO
2152 "...changing IO-APIC physical APIC ID to %d ...",
2153 mp_ioapics[apic_id].apicid);
2155 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2156 raw_spin_lock_irqsave(&ioapic_lock, flags);
2157 io_apic_write(apic_id, 0, reg_00.raw);
2158 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2163 raw_spin_lock_irqsave(&ioapic_lock, flags);
2164 reg_00.raw = io_apic_read(apic_id, 0);
2165 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2166 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2167 printk("could not set ID!\n");
2169 apic_printk(APIC_VERBOSE, " ok.\n");
2174 int no_timer_check __initdata;
2176 static int __init notimercheck(char *s)
2181 __setup("no_timer_check", notimercheck);
2184 * There is a nasty bug in some older SMP boards, their mptable lies
2185 * about the timer IRQ. We do the following to work around the situation:
2187 * - timer IRQ defaults to IO-APIC IRQ
2188 * - if this function detects that timer IRQs are defunct, then we fall
2189 * back to ISA timer IRQs
2191 static int __init timer_irq_works(void)
2193 unsigned long t1 = jiffies;
2194 unsigned long flags;
2199 local_save_flags(flags);
2201 /* Let ten ticks pass... */
2202 mdelay((10 * 1000) / HZ);
2203 local_irq_restore(flags);
2206 * Expect a few ticks at least, to be sure some possible
2207 * glue logic does not lock up after one or two first
2208 * ticks in a non-ExtINT mode. Also the local APIC
2209 * might have cached one ExtINT interrupt. Finally, at
2210 * least one tick may be lost due to delays.
2214 if (time_after(jiffies, t1 + 4))
2220 * In the SMP+IOAPIC case it might happen that there are an unspecified
2221 * number of pending IRQ events unhandled. These cases are very rare,
2222 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2223 * better to do it this way as thus we do not have to be aware of
2224 * 'pending' interrupts in the IRQ path, except at this point.
2227 * Edge triggered needs to resend any interrupt
2228 * that was delayed but this is now handled in the device
2233 * Starting up a edge-triggered IO-APIC interrupt is
2234 * nasty - we need to make sure that we get the edge.
2235 * If it is already asserted for some reason, we need
2236 * return 1 to indicate that is was pending.
2238 * This is not complete - we should be able to fake
2239 * an edge even if it isn't on the 8259A...
2242 static unsigned int startup_ioapic_irq(unsigned int irq)
2244 int was_pending = 0;
2245 unsigned long flags;
2246 struct irq_cfg *cfg;
2248 raw_spin_lock_irqsave(&ioapic_lock, flags);
2249 if (irq < legacy_pic->nr_legacy_irqs) {
2250 legacy_pic->chip->mask(irq);
2251 if (legacy_pic->irq_pending(irq))
2255 __unmask_IO_APIC_irq(cfg);
2256 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2261 static int ioapic_retrigger_irq(unsigned int irq)
2264 struct irq_cfg *cfg = irq_cfg(irq);
2265 unsigned long flags;
2267 raw_spin_lock_irqsave(&vector_lock, flags);
2268 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2269 raw_spin_unlock_irqrestore(&vector_lock, flags);
2275 * Level and edge triggered IO-APIC interrupts need different handling,
2276 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2277 * handled with the level-triggered descriptor, but that one has slightly
2278 * more overhead. Level-triggered interrupts cannot be handled with the
2279 * edge-triggered handler, without risking IRQ storms and other ugly
2284 void send_cleanup_vector(struct irq_cfg *cfg)
2286 cpumask_var_t cleanup_mask;
2288 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2290 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2291 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2293 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2294 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2295 free_cpumask_var(cleanup_mask);
2297 cfg->move_in_progress = 0;
2300 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2303 struct irq_pin_list *entry;
2304 u8 vector = cfg->vector;
2306 for_each_irq_pin(entry, cfg->irq_2_pin) {
2312 * With interrupt-remapping, destination information comes
2313 * from interrupt-remapping table entry.
2315 if (!irq_remapped(irq))
2316 io_apic_write(apic, 0x11 + pin*2, dest);
2317 reg = io_apic_read(apic, 0x10 + pin*2);
2318 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2320 io_apic_modify(apic, 0x10 + pin*2, reg);
2325 * Either sets desc->affinity to a valid value, and returns
2326 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2327 * leaves desc->affinity untouched.
2330 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2331 unsigned int *dest_id)
2333 struct irq_cfg *cfg;
2336 if (!cpumask_intersects(mask, cpu_online_mask))
2340 cfg = desc->chip_data;
2341 if (assign_irq_vector(irq, cfg, mask))
2344 cpumask_copy(desc->affinity, mask);
2346 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2351 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2353 struct irq_cfg *cfg;
2354 unsigned long flags;
2360 cfg = desc->chip_data;
2362 raw_spin_lock_irqsave(&ioapic_lock, flags);
2363 ret = set_desc_affinity(desc, mask, &dest);
2365 /* Only the high 8 bits are valid. */
2366 dest = SET_APIC_LOGICAL_ID(dest);
2367 __target_IO_APIC_irq(irq, dest, cfg);
2369 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2375 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2377 struct irq_desc *desc;
2379 desc = irq_to_desc(irq);
2381 return set_ioapic_affinity_irq_desc(desc, mask);
2384 #ifdef CONFIG_INTR_REMAP
2387 * Migrate the IO-APIC irq in the presence of intr-remapping.
2389 * For both level and edge triggered, irq migration is a simple atomic
2390 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2392 * For level triggered, we eliminate the io-apic RTE modification (with the
2393 * updated vector information), by using a virtual vector (io-apic pin number).
2394 * Real vector that is used for interrupting cpu will be coming from
2395 * the interrupt-remapping table entry.
2398 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2400 struct irq_cfg *cfg;
2406 if (!cpumask_intersects(mask, cpu_online_mask))
2410 if (get_irte(irq, &irte))
2413 cfg = desc->chip_data;
2414 if (assign_irq_vector(irq, cfg, mask))
2417 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2419 irte.vector = cfg->vector;
2420 irte.dest_id = IRTE_DEST(dest);
2423 * Modified the IRTE and flushes the Interrupt entry cache.
2425 modify_irte(irq, &irte);
2427 if (cfg->move_in_progress)
2428 send_cleanup_vector(cfg);
2430 cpumask_copy(desc->affinity, mask);
2436 * Migrates the IRQ destination in the process context.
2438 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2439 const struct cpumask *mask)
2441 return migrate_ioapic_irq_desc(desc, mask);
2443 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2444 const struct cpumask *mask)
2446 struct irq_desc *desc = irq_to_desc(irq);
2448 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2451 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2452 const struct cpumask *mask)
2458 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2460 unsigned vector, me;
2466 me = smp_processor_id();
2467 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2470 struct irq_desc *desc;
2471 struct irq_cfg *cfg;
2472 irq = __get_cpu_var(vector_irq)[vector];
2477 desc = irq_to_desc(irq);
2482 raw_spin_lock(&desc->lock);
2485 * Check if the irq migration is in progress. If so, we
2486 * haven't received the cleanup request yet for this irq.
2488 if (cfg->move_in_progress)
2491 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2494 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2496 * Check if the vector that needs to be cleanedup is
2497 * registered at the cpu's IRR. If so, then this is not
2498 * the best time to clean it up. Lets clean it up in the
2499 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2502 if (irr & (1 << (vector % 32))) {
2503 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2506 __get_cpu_var(vector_irq)[vector] = -1;
2508 raw_spin_unlock(&desc->lock);
2514 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2516 struct irq_desc *desc = *descp;
2517 struct irq_cfg *cfg = desc->chip_data;
2520 if (likely(!cfg->move_in_progress))
2523 me = smp_processor_id();
2525 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2526 send_cleanup_vector(cfg);
2529 static void irq_complete_move(struct irq_desc **descp)
2531 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2534 void irq_force_complete_move(int irq)
2536 struct irq_desc *desc = irq_to_desc(irq);
2537 struct irq_cfg *cfg = desc->chip_data;
2542 __irq_complete_move(&desc, cfg->vector);
2545 static inline void irq_complete_move(struct irq_desc **descp) {}
2548 static void ack_apic_edge(unsigned int irq)
2550 struct irq_desc *desc = irq_to_desc(irq);
2552 irq_complete_move(&desc);
2553 move_native_irq(irq);
2557 atomic_t irq_mis_count;
2560 * IO-APIC versions below 0x20 don't support EOI register.
2561 * For the record, here is the information about various versions:
2563 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2564 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2567 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2568 * version as 0x2. This is an error with documentation and these ICH chips
2569 * use io-apic's of version 0x20.
2571 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2572 * Otherwise, we simulate the EOI message manually by changing the trigger
2573 * mode to edge and then back to level, with RTE being masked during this.
2575 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2577 struct irq_pin_list *entry;
2579 for_each_irq_pin(entry, cfg->irq_2_pin) {
2580 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2582 * Intr-remapping uses pin number as the virtual vector
2583 * in the RTE. Actual vector is programmed in
2584 * intr-remapping table entry. Hence for the io-apic
2585 * EOI we use the pin number.
2587 if (irq_remapped(irq))
2588 io_apic_eoi(entry->apic, entry->pin);
2590 io_apic_eoi(entry->apic, cfg->vector);
2592 __mask_and_edge_IO_APIC_irq(entry);
2593 __unmask_and_level_IO_APIC_irq(entry);
2598 static void eoi_ioapic_irq(struct irq_desc *desc)
2600 struct irq_cfg *cfg;
2601 unsigned long flags;
2605 cfg = desc->chip_data;
2607 raw_spin_lock_irqsave(&ioapic_lock, flags);
2608 __eoi_ioapic_irq(irq, cfg);
2609 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2612 static void ack_apic_level(unsigned int irq)
2614 struct irq_desc *desc = irq_to_desc(irq);
2617 struct irq_cfg *cfg;
2618 int do_unmask_irq = 0;
2620 irq_complete_move(&desc);
2621 #ifdef CONFIG_GENERIC_PENDING_IRQ
2622 /* If we are moving the irq we need to mask it */
2623 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2625 mask_IO_APIC_irq_desc(desc);
2630 * It appears there is an erratum which affects at least version 0x11
2631 * of I/O APIC (that's the 82093AA and cores integrated into various
2632 * chipsets). Under certain conditions a level-triggered interrupt is
2633 * erroneously delivered as edge-triggered one but the respective IRR
2634 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2635 * message but it will never arrive and further interrupts are blocked
2636 * from the source. The exact reason is so far unknown, but the
2637 * phenomenon was observed when two consecutive interrupt requests
2638 * from a given source get delivered to the same CPU and the source is
2639 * temporarily disabled in between.
2641 * A workaround is to simulate an EOI message manually. We achieve it
2642 * by setting the trigger mode to edge and then to level when the edge
2643 * trigger mode gets detected in the TMR of a local APIC for a
2644 * level-triggered interrupt. We mask the source for the time of the
2645 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2646 * The idea is from Manfred Spraul. --macro
2648 * Also in the case when cpu goes offline, fixup_irqs() will forward
2649 * any unhandled interrupt on the offlined cpu to the new cpu
2650 * destination that is handling the corresponding interrupt. This
2651 * interrupt forwarding is done via IPI's. Hence, in this case also
2652 * level-triggered io-apic interrupt will be seen as an edge
2653 * interrupt in the IRR. And we can't rely on the cpu's EOI
2654 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2655 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2656 * supporting EOI register, we do an explicit EOI to clear the
2657 * remote IRR and on IO-APIC's which don't have an EOI register,
2658 * we use the above logic (mask+edge followed by unmask+level) from
2659 * Manfred Spraul to clear the remote IRR.
2661 cfg = desc->chip_data;
2663 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2666 * We must acknowledge the irq before we move it or the acknowledge will
2667 * not propagate properly.
2672 * Tail end of clearing remote IRR bit (either by delivering the EOI
2673 * message via io-apic EOI register write or simulating it using
2674 * mask+edge followed by unnask+level logic) manually when the
2675 * level triggered interrupt is seen as the edge triggered interrupt
2678 if (!(v & (1 << (i & 0x1f)))) {
2679 atomic_inc(&irq_mis_count);
2681 eoi_ioapic_irq(desc);
2684 /* Now we can move and renable the irq */
2685 if (unlikely(do_unmask_irq)) {
2686 /* Only migrate the irq if the ack has been received.
2688 * On rare occasions the broadcast level triggered ack gets
2689 * delayed going to ioapics, and if we reprogram the
2690 * vector while Remote IRR is still set the irq will never
2693 * To prevent this scenario we read the Remote IRR bit
2694 * of the ioapic. This has two effects.
2695 * - On any sane system the read of the ioapic will
2696 * flush writes (and acks) going to the ioapic from
2698 * - We get to see if the ACK has actually been delivered.
2700 * Based on failed experiments of reprogramming the
2701 * ioapic entry from outside of irq context starting
2702 * with masking the ioapic entry and then polling until
2703 * Remote IRR was clear before reprogramming the
2704 * ioapic I don't trust the Remote IRR bit to be
2705 * completey accurate.
2707 * However there appears to be no other way to plug
2708 * this race, so if the Remote IRR bit is not
2709 * accurate and is causing problems then it is a hardware bug
2710 * and you can go talk to the chipset vendor about it.
2712 cfg = desc->chip_data;
2713 if (!io_apic_level_ack_pending(cfg))
2714 move_masked_irq(irq);
2715 unmask_IO_APIC_irq_desc(desc);
2719 #ifdef CONFIG_INTR_REMAP
2720 static void ir_ack_apic_edge(unsigned int irq)
2725 static void ir_ack_apic_level(unsigned int irq)
2727 struct irq_desc *desc = irq_to_desc(irq);
2730 eoi_ioapic_irq(desc);
2732 #endif /* CONFIG_INTR_REMAP */
2734 static struct irq_chip ioapic_chip __read_mostly = {
2736 .startup = startup_ioapic_irq,
2737 .mask = mask_IO_APIC_irq,
2738 .unmask = unmask_IO_APIC_irq,
2739 .ack = ack_apic_edge,
2740 .eoi = ack_apic_level,
2742 .set_affinity = set_ioapic_affinity_irq,
2744 .retrigger = ioapic_retrigger_irq,
2747 static struct irq_chip ir_ioapic_chip __read_mostly = {
2748 .name = "IR-IO-APIC",
2749 .startup = startup_ioapic_irq,
2750 .mask = mask_IO_APIC_irq,
2751 .unmask = unmask_IO_APIC_irq,
2752 #ifdef CONFIG_INTR_REMAP
2753 .ack = ir_ack_apic_edge,
2754 .eoi = ir_ack_apic_level,
2756 .set_affinity = set_ir_ioapic_affinity_irq,
2759 .retrigger = ioapic_retrigger_irq,
2762 static inline void init_IO_APIC_traps(void)
2765 struct irq_desc *desc;
2766 struct irq_cfg *cfg;
2769 * NOTE! The local APIC isn't very good at handling
2770 * multiple interrupts at the same interrupt level.
2771 * As the interrupt level is determined by taking the
2772 * vector number and shifting that right by 4, we
2773 * want to spread these out a bit so that they don't
2774 * all fall in the same interrupt level.
2776 * Also, we've got to be careful not to trash gate
2777 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2779 for_each_irq_desc(irq, desc) {
2780 cfg = desc->chip_data;
2781 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2783 * Hmm.. We don't have an entry for this,
2784 * so default to an old-fashioned 8259
2785 * interrupt if we can..
2787 if (irq < legacy_pic->nr_legacy_irqs)
2788 legacy_pic->make_irq(irq);
2790 /* Strange. Oh, well.. */
2791 desc->chip = &no_irq_chip;
2797 * The local APIC irq-chip implementation:
2800 static void mask_lapic_irq(unsigned int irq)
2804 v = apic_read(APIC_LVT0);
2805 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2808 static void unmask_lapic_irq(unsigned int irq)
2812 v = apic_read(APIC_LVT0);
2813 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2816 static void ack_lapic_irq(unsigned int irq)
2821 static struct irq_chip lapic_chip __read_mostly = {
2822 .name = "local-APIC",
2823 .mask = mask_lapic_irq,
2824 .unmask = unmask_lapic_irq,
2825 .ack = ack_lapic_irq,
2828 static void lapic_register_intr(int irq, struct irq_desc *desc)
2830 desc->status &= ~IRQ_LEVEL;
2831 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2835 static void __init setup_nmi(void)
2838 * Dirty trick to enable the NMI watchdog ...
2839 * We put the 8259A master into AEOI mode and
2840 * unmask on all local APICs LVT0 as NMI.
2842 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2843 * is from Maciej W. Rozycki - so we do not have to EOI from
2844 * the NMI handler or the timer interrupt.
2846 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2848 enable_NMI_through_LVT0();
2850 apic_printk(APIC_VERBOSE, " done.\n");
2854 * This looks a bit hackish but it's about the only one way of sending
2855 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2856 * not support the ExtINT mode, unfortunately. We need to send these
2857 * cycles as some i82489DX-based boards have glue logic that keeps the
2858 * 8259A interrupt line asserted until INTA. --macro
2860 static inline void __init unlock_ExtINT_logic(void)
2863 struct IO_APIC_route_entry entry0, entry1;
2864 unsigned char save_control, save_freq_select;
2866 pin = find_isa_irq_pin(8, mp_INT);
2871 apic = find_isa_irq_apic(8, mp_INT);
2877 entry0 = ioapic_read_entry(apic, pin);
2878 clear_IO_APIC_pin(apic, pin);
2880 memset(&entry1, 0, sizeof(entry1));
2882 entry1.dest_mode = 0; /* physical delivery */
2883 entry1.mask = 0; /* unmask IRQ now */
2884 entry1.dest = hard_smp_processor_id();
2885 entry1.delivery_mode = dest_ExtINT;
2886 entry1.polarity = entry0.polarity;
2890 ioapic_write_entry(apic, pin, entry1);
2892 save_control = CMOS_READ(RTC_CONTROL);
2893 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2894 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2896 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2901 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2905 CMOS_WRITE(save_control, RTC_CONTROL);
2906 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2907 clear_IO_APIC_pin(apic, pin);
2909 ioapic_write_entry(apic, pin, entry0);
2912 static int disable_timer_pin_1 __initdata;
2913 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2914 static int __init disable_timer_pin_setup(char *arg)
2916 disable_timer_pin_1 = 1;
2919 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2921 int timer_through_8259 __initdata;
2924 * This code may look a bit paranoid, but it's supposed to cooperate with
2925 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2926 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2927 * fanatically on his truly buggy board.
2929 * FIXME: really need to revamp this for all platforms.
2931 static inline void __init check_timer(void)
2933 struct irq_desc *desc = irq_to_desc(0);
2934 struct irq_cfg *cfg = desc->chip_data;
2935 int node = cpu_to_node(0);
2936 int apic1, pin1, apic2, pin2;
2937 unsigned long flags;
2940 local_irq_save(flags);
2943 * get/set the timer IRQ vector:
2945 legacy_pic->chip->mask(0);
2946 assign_irq_vector(0, cfg, apic->target_cpus());
2949 * As IRQ0 is to be enabled in the 8259A, the virtual
2950 * wire has to be disabled in the local APIC. Also
2951 * timer interrupts need to be acknowledged manually in
2952 * the 8259A for the i82489DX when using the NMI
2953 * watchdog as that APIC treats NMIs as level-triggered.
2954 * The AEOI mode will finish them in the 8259A
2957 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2958 legacy_pic->init(1);
2959 #ifdef CONFIG_X86_32
2963 ver = apic_read(APIC_LVR);
2964 ver = GET_APIC_VERSION(ver);
2965 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2969 pin1 = find_isa_irq_pin(0, mp_INT);
2970 apic1 = find_isa_irq_apic(0, mp_INT);
2971 pin2 = ioapic_i8259.pin;
2972 apic2 = ioapic_i8259.apic;
2974 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2975 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2976 cfg->vector, apic1, pin1, apic2, pin2);
2979 * Some BIOS writers are clueless and report the ExtINTA
2980 * I/O APIC input from the cascaded 8259A as the timer
2981 * interrupt input. So just in case, if only one pin
2982 * was found above, try it both directly and through the
2986 if (intr_remapping_enabled)
2987 panic("BIOS bug: timer not connected to IO-APIC");
2991 } else if (pin2 == -1) {
2998 * Ok, does IRQ0 through the IOAPIC work?
3001 add_pin_to_irq_node(cfg, node, apic1, pin1);
3002 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3004 /* for edge trigger, setup_IO_APIC_irq already
3005 * leave it unmasked.
3006 * so only need to unmask if it is level-trigger
3007 * do we really have level trigger timer?
3010 idx = find_irq_entry(apic1, pin1, mp_INT);
3011 if (idx != -1 && irq_trigger(idx))
3012 unmask_IO_APIC_irq_desc(desc);
3014 if (timer_irq_works()) {
3015 if (nmi_watchdog == NMI_IO_APIC) {
3017 legacy_pic->chip->unmask(0);
3019 if (disable_timer_pin_1 > 0)
3020 clear_IO_APIC_pin(0, pin1);
3023 if (intr_remapping_enabled)
3024 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3025 local_irq_disable();
3026 clear_IO_APIC_pin(apic1, pin1);
3028 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3029 "8254 timer not connected to IO-APIC\n");
3031 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3032 "(IRQ0) through the 8259A ...\n");
3033 apic_printk(APIC_QUIET, KERN_INFO
3034 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3036 * legacy devices should be connected to IO APIC #0
3038 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3039 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3040 legacy_pic->chip->unmask(0);
3041 if (timer_irq_works()) {
3042 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3043 timer_through_8259 = 1;
3044 if (nmi_watchdog == NMI_IO_APIC) {
3045 legacy_pic->chip->mask(0);
3047 legacy_pic->chip->unmask(0);
3052 * Cleanup, just in case ...
3054 local_irq_disable();
3055 legacy_pic->chip->mask(0);
3056 clear_IO_APIC_pin(apic2, pin2);
3057 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3060 if (nmi_watchdog == NMI_IO_APIC) {
3061 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3062 "through the IO-APIC - disabling NMI Watchdog!\n");
3063 nmi_watchdog = NMI_NONE;
3065 #ifdef CONFIG_X86_32
3069 apic_printk(APIC_QUIET, KERN_INFO
3070 "...trying to set up timer as Virtual Wire IRQ...\n");
3072 lapic_register_intr(0, desc);
3073 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3074 legacy_pic->chip->unmask(0);
3076 if (timer_irq_works()) {
3077 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3080 local_irq_disable();
3081 legacy_pic->chip->mask(0);
3082 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3083 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3085 apic_printk(APIC_QUIET, KERN_INFO
3086 "...trying to set up timer as ExtINT IRQ...\n");
3088 legacy_pic->init(0);
3089 legacy_pic->make_irq(0);
3090 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3092 unlock_ExtINT_logic();
3094 if (timer_irq_works()) {
3095 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3098 local_irq_disable();
3099 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3100 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3101 "report. Then try booting with the 'noapic' option.\n");
3103 local_irq_restore(flags);
3107 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3108 * to devices. However there may be an I/O APIC pin available for
3109 * this interrupt regardless. The pin may be left unconnected, but
3110 * typically it will be reused as an ExtINT cascade interrupt for
3111 * the master 8259A. In the MPS case such a pin will normally be
3112 * reported as an ExtINT interrupt in the MP table. With ACPI
3113 * there is no provision for ExtINT interrupts, and in the absence
3114 * of an override it would be treated as an ordinary ISA I/O APIC
3115 * interrupt, that is edge-triggered and unmasked by default. We
3116 * used to do this, but it caused problems on some systems because
3117 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3118 * the same ExtINT cascade interrupt to drive the local APIC of the
3119 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3120 * the I/O APIC in all cases now. No actual device should request
3121 * it anyway. --macro
3123 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3125 void __init setup_IO_APIC(void)
3129 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3131 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3133 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3135 * Set up IO-APIC IRQ routing.
3137 x86_init.mpparse.setup_ioapic_ids();
3140 setup_IO_APIC_irqs();
3141 init_IO_APIC_traps();
3142 if (legacy_pic->nr_legacy_irqs)
3147 * Called after all the initialization is done. If we didnt find any
3148 * APIC bugs then we can allow the modify fast path
3151 static int __init io_apic_bug_finalize(void)
3153 if (sis_apic_bug == -1)
3158 late_initcall(io_apic_bug_finalize);
3160 struct sysfs_ioapic_data {
3161 struct sys_device dev;
3162 struct IO_APIC_route_entry entry[0];
3164 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3166 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3168 struct IO_APIC_route_entry *entry;
3169 struct sysfs_ioapic_data *data;
3172 data = container_of(dev, struct sysfs_ioapic_data, dev);
3173 entry = data->entry;
3174 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3175 *entry = ioapic_read_entry(dev->id, i);
3180 static int ioapic_resume(struct sys_device *dev)
3182 struct IO_APIC_route_entry *entry;
3183 struct sysfs_ioapic_data *data;
3184 unsigned long flags;
3185 union IO_APIC_reg_00 reg_00;
3188 data = container_of(dev, struct sysfs_ioapic_data, dev);
3189 entry = data->entry;
3191 raw_spin_lock_irqsave(&ioapic_lock, flags);
3192 reg_00.raw = io_apic_read(dev->id, 0);
3193 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3194 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3195 io_apic_write(dev->id, 0, reg_00.raw);
3197 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3198 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3199 ioapic_write_entry(dev->id, i, entry[i]);
3204 static struct sysdev_class ioapic_sysdev_class = {
3206 .suspend = ioapic_suspend,
3207 .resume = ioapic_resume,
3210 static int __init ioapic_init_sysfs(void)
3212 struct sys_device * dev;
3215 error = sysdev_class_register(&ioapic_sysdev_class);
3219 for (i = 0; i < nr_ioapics; i++ ) {
3220 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3221 * sizeof(struct IO_APIC_route_entry);
3222 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3223 if (!mp_ioapic_data[i]) {
3224 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3227 dev = &mp_ioapic_data[i]->dev;
3229 dev->cls = &ioapic_sysdev_class;
3230 error = sysdev_register(dev);
3232 kfree(mp_ioapic_data[i]);
3233 mp_ioapic_data[i] = NULL;
3234 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3242 device_initcall(ioapic_init_sysfs);
3245 * Dynamic irq allocate and deallocation
3247 unsigned int create_irq_nr(unsigned int irq_want, int node)
3249 /* Allocate an unused irq */
3252 unsigned long flags;
3253 struct irq_cfg *cfg_new = NULL;
3254 struct irq_desc *desc_new = NULL;
3257 if (irq_want < nr_irqs_gsi)
3258 irq_want = nr_irqs_gsi;
3260 raw_spin_lock_irqsave(&vector_lock, flags);
3261 for (new = irq_want; new < nr_irqs; new++) {
3262 desc_new = irq_to_desc_alloc_node(new, node);
3264 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3267 cfg_new = desc_new->chip_data;
3269 if (cfg_new->vector != 0)
3272 desc_new = move_irq_desc(desc_new, node);
3273 cfg_new = desc_new->chip_data;
3275 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3279 raw_spin_unlock_irqrestore(&vector_lock, flags);
3282 dynamic_irq_init_keep_chip_data(irq);
3287 int create_irq(void)
3289 int node = cpu_to_node(0);
3290 unsigned int irq_want;
3293 irq_want = nr_irqs_gsi;
3294 irq = create_irq_nr(irq_want, node);
3302 void destroy_irq(unsigned int irq)
3304 unsigned long flags;
3306 dynamic_irq_cleanup_keep_chip_data(irq);
3309 raw_spin_lock_irqsave(&vector_lock, flags);
3310 __clear_irq_vector(irq, get_irq_chip_data(irq));
3311 raw_spin_unlock_irqrestore(&vector_lock, flags);
3315 * MSI message composition
3317 #ifdef CONFIG_PCI_MSI
3318 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3319 struct msi_msg *msg, u8 hpet_id)
3321 struct irq_cfg *cfg;
3329 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3333 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3335 if (irq_remapped(irq)) {
3340 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3341 BUG_ON(ir_index == -1);
3343 memset (&irte, 0, sizeof(irte));
3346 irte.dst_mode = apic->irq_dest_mode;
3347 irte.trigger_mode = 0; /* edge */
3348 irte.dlvry_mode = apic->irq_delivery_mode;
3349 irte.vector = cfg->vector;
3350 irte.dest_id = IRTE_DEST(dest);
3352 /* Set source-id of interrupt request */
3354 set_msi_sid(&irte, pdev);
3356 set_hpet_sid(&irte, hpet_id);
3358 modify_irte(irq, &irte);
3360 msg->address_hi = MSI_ADDR_BASE_HI;
3361 msg->data = sub_handle;
3362 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3364 MSI_ADDR_IR_INDEX1(ir_index) |
3365 MSI_ADDR_IR_INDEX2(ir_index);
3367 if (x2apic_enabled())
3368 msg->address_hi = MSI_ADDR_BASE_HI |
3369 MSI_ADDR_EXT_DEST_ID(dest);
3371 msg->address_hi = MSI_ADDR_BASE_HI;
3375 ((apic->irq_dest_mode == 0) ?
3376 MSI_ADDR_DEST_MODE_PHYSICAL:
3377 MSI_ADDR_DEST_MODE_LOGICAL) |
3378 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3379 MSI_ADDR_REDIRECTION_CPU:
3380 MSI_ADDR_REDIRECTION_LOWPRI) |
3381 MSI_ADDR_DEST_ID(dest);
3384 MSI_DATA_TRIGGER_EDGE |
3385 MSI_DATA_LEVEL_ASSERT |
3386 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3387 MSI_DATA_DELIVERY_FIXED:
3388 MSI_DATA_DELIVERY_LOWPRI) |
3389 MSI_DATA_VECTOR(cfg->vector);
3395 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3397 struct irq_desc *desc = irq_to_desc(irq);
3398 struct irq_cfg *cfg;
3402 if (set_desc_affinity(desc, mask, &dest))
3405 cfg = desc->chip_data;
3407 get_cached_msi_msg_desc(desc, &msg);
3409 msg.data &= ~MSI_DATA_VECTOR_MASK;
3410 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3411 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3412 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3414 write_msi_msg_desc(desc, &msg);
3418 #ifdef CONFIG_INTR_REMAP
3420 * Migrate the MSI irq to another cpumask. This migration is
3421 * done in the process context using interrupt-remapping hardware.
3424 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3426 struct irq_desc *desc = irq_to_desc(irq);
3427 struct irq_cfg *cfg = desc->chip_data;
3431 if (get_irte(irq, &irte))
3434 if (set_desc_affinity(desc, mask, &dest))
3437 irte.vector = cfg->vector;
3438 irte.dest_id = IRTE_DEST(dest);
3441 * atomically update the IRTE with the new destination and vector.
3443 modify_irte(irq, &irte);
3446 * After this point, all the interrupts will start arriving
3447 * at the new destination. So, time to cleanup the previous
3448 * vector allocation.
3450 if (cfg->move_in_progress)
3451 send_cleanup_vector(cfg);
3457 #endif /* CONFIG_SMP */
3460 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3461 * which implement the MSI or MSI-X Capability Structure.
3463 static struct irq_chip msi_chip = {
3465 .unmask = unmask_msi_irq,
3466 .mask = mask_msi_irq,
3467 .ack = ack_apic_edge,
3469 .set_affinity = set_msi_irq_affinity,
3471 .retrigger = ioapic_retrigger_irq,
3474 static struct irq_chip msi_ir_chip = {
3475 .name = "IR-PCI-MSI",
3476 .unmask = unmask_msi_irq,
3477 .mask = mask_msi_irq,
3478 #ifdef CONFIG_INTR_REMAP
3479 .ack = ir_ack_apic_edge,
3481 .set_affinity = ir_set_msi_irq_affinity,
3484 .retrigger = ioapic_retrigger_irq,
3488 * Map the PCI dev to the corresponding remapping hardware unit
3489 * and allocate 'nvec' consecutive interrupt-remapping table entries
3492 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3494 struct intel_iommu *iommu;
3497 iommu = map_dev_to_ir(dev);
3500 "Unable to map PCI %s to iommu\n", pci_name(dev));
3504 index = alloc_irte(iommu, irq, nvec);
3507 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3514 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3519 ret = msi_compose_msg(dev, irq, &msg, -1);
3523 set_irq_msi(irq, msidesc);
3524 write_msi_msg(irq, &msg);
3526 if (irq_remapped(irq)) {
3527 struct irq_desc *desc = irq_to_desc(irq);
3529 * irq migration in process context
3531 desc->status |= IRQ_MOVE_PCNTXT;
3532 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3534 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3536 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3541 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3544 int ret, sub_handle;
3545 struct msi_desc *msidesc;
3546 unsigned int irq_want;
3547 struct intel_iommu *iommu = NULL;
3551 /* x86 doesn't support multiple MSI yet */
3552 if (type == PCI_CAP_ID_MSI && nvec > 1)
3555 node = dev_to_node(&dev->dev);
3556 irq_want = nr_irqs_gsi;
3558 list_for_each_entry(msidesc, &dev->msi_list, list) {
3559 irq = create_irq_nr(irq_want, node);
3563 if (!intr_remapping_enabled)
3568 * allocate the consecutive block of IRTE's
3571 index = msi_alloc_irte(dev, irq, nvec);
3577 iommu = map_dev_to_ir(dev);
3583 * setup the mapping between the irq and the IRTE
3584 * base index, the sub_handle pointing to the
3585 * appropriate interrupt remap table entry.
3587 set_irte_irq(irq, iommu, index, sub_handle);
3590 ret = setup_msi_irq(dev, msidesc, irq);
3602 void arch_teardown_msi_irq(unsigned int irq)
3607 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3609 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3611 struct irq_desc *desc = irq_to_desc(irq);
3612 struct irq_cfg *cfg;
3616 if (set_desc_affinity(desc, mask, &dest))
3619 cfg = desc->chip_data;
3621 dmar_msi_read(irq, &msg);
3623 msg.data &= ~MSI_DATA_VECTOR_MASK;
3624 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3625 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3626 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3628 dmar_msi_write(irq, &msg);
3633 #endif /* CONFIG_SMP */
3635 static struct irq_chip dmar_msi_type = {
3637 .unmask = dmar_msi_unmask,
3638 .mask = dmar_msi_mask,
3639 .ack = ack_apic_edge,
3641 .set_affinity = dmar_msi_set_affinity,
3643 .retrigger = ioapic_retrigger_irq,
3646 int arch_setup_dmar_msi(unsigned int irq)
3651 ret = msi_compose_msg(NULL, irq, &msg, -1);
3654 dmar_msi_write(irq, &msg);
3655 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3661 #ifdef CONFIG_HPET_TIMER
3664 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3666 struct irq_desc *desc = irq_to_desc(irq);
3667 struct irq_cfg *cfg;
3671 if (set_desc_affinity(desc, mask, &dest))
3674 cfg = desc->chip_data;
3676 hpet_msi_read(irq, &msg);
3678 msg.data &= ~MSI_DATA_VECTOR_MASK;
3679 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3680 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3681 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3683 hpet_msi_write(irq, &msg);
3688 #endif /* CONFIG_SMP */
3690 static struct irq_chip ir_hpet_msi_type = {
3691 .name = "IR-HPET_MSI",
3692 .unmask = hpet_msi_unmask,
3693 .mask = hpet_msi_mask,
3694 #ifdef CONFIG_INTR_REMAP
3695 .ack = ir_ack_apic_edge,
3697 .set_affinity = ir_set_msi_irq_affinity,
3700 .retrigger = ioapic_retrigger_irq,
3703 static struct irq_chip hpet_msi_type = {
3705 .unmask = hpet_msi_unmask,
3706 .mask = hpet_msi_mask,
3707 .ack = ack_apic_edge,
3709 .set_affinity = hpet_msi_set_affinity,
3711 .retrigger = ioapic_retrigger_irq,
3714 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3718 struct irq_desc *desc = irq_to_desc(irq);
3720 if (intr_remapping_enabled) {
3721 struct intel_iommu *iommu = map_hpet_to_ir(id);
3727 index = alloc_irte(iommu, irq, 1);
3732 ret = msi_compose_msg(NULL, irq, &msg, id);
3736 hpet_msi_write(irq, &msg);
3737 desc->status |= IRQ_MOVE_PCNTXT;
3738 if (irq_remapped(irq))
3739 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3740 handle_edge_irq, "edge");
3742 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3743 handle_edge_irq, "edge");
3749 #endif /* CONFIG_PCI_MSI */
3751 * Hypertransport interrupt support
3753 #ifdef CONFIG_HT_IRQ
3757 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3759 struct ht_irq_msg msg;
3760 fetch_ht_irq_msg(irq, &msg);
3762 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3763 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3765 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3766 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3768 write_ht_irq_msg(irq, &msg);
3771 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3773 struct irq_desc *desc = irq_to_desc(irq);
3774 struct irq_cfg *cfg;
3777 if (set_desc_affinity(desc, mask, &dest))
3780 cfg = desc->chip_data;
3782 target_ht_irq(irq, dest, cfg->vector);
3789 static struct irq_chip ht_irq_chip = {
3791 .mask = mask_ht_irq,
3792 .unmask = unmask_ht_irq,
3793 .ack = ack_apic_edge,
3795 .set_affinity = set_ht_irq_affinity,
3797 .retrigger = ioapic_retrigger_irq,
3800 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3802 struct irq_cfg *cfg;
3809 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3811 struct ht_irq_msg msg;
3814 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3815 apic->target_cpus());
3817 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3821 HT_IRQ_LOW_DEST_ID(dest) |
3822 HT_IRQ_LOW_VECTOR(cfg->vector) |
3823 ((apic->irq_dest_mode == 0) ?
3824 HT_IRQ_LOW_DM_PHYSICAL :
3825 HT_IRQ_LOW_DM_LOGICAL) |
3826 HT_IRQ_LOW_RQEOI_EDGE |
3827 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3828 HT_IRQ_LOW_MT_FIXED :
3829 HT_IRQ_LOW_MT_ARBITRATED) |
3830 HT_IRQ_LOW_IRQ_MASKED;
3832 write_ht_irq_msg(irq, &msg);
3834 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3835 handle_edge_irq, "edge");
3837 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3841 #endif /* CONFIG_HT_IRQ */
3843 int __init io_apic_get_redir_entries (int ioapic)
3845 union IO_APIC_reg_01 reg_01;
3846 unsigned long flags;
3848 raw_spin_lock_irqsave(&ioapic_lock, flags);
3849 reg_01.raw = io_apic_read(ioapic, 1);
3850 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3852 /* The register returns the maximum index redir index
3853 * supported, which is one less than the total number of redir
3856 return reg_01.bits.entries + 1;
3859 void __init probe_nr_irqs_gsi(void)
3863 nr = gsi_top + NR_IRQS_LEGACY;
3864 if (nr > nr_irqs_gsi)
3867 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3870 #ifdef CONFIG_SPARSE_IRQ
3871 int __init arch_probe_nr_irqs(void)
3875 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3876 nr_irqs = NR_VECTORS * nr_cpu_ids;
3878 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3879 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3881 * for MSI and HT dyn irq
3883 nr += nr_irqs_gsi * 16;
3892 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3893 struct io_apic_irq_attr *irq_attr)
3895 struct irq_desc *desc;
3896 struct irq_cfg *cfg;
3899 int trigger, polarity;
3901 ioapic = irq_attr->ioapic;
3902 if (!IO_APIC_IRQ(irq)) {
3903 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3909 node = dev_to_node(dev);
3911 node = cpu_to_node(0);
3913 desc = irq_to_desc_alloc_node(irq, node);
3915 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3919 pin = irq_attr->ioapic_pin;
3920 trigger = irq_attr->trigger;
3921 polarity = irq_attr->polarity;
3924 * IRQs < 16 are already in the irq_2_pin[] map
3926 if (irq >= legacy_pic->nr_legacy_irqs) {
3927 cfg = desc->chip_data;
3928 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3929 printk(KERN_INFO "can not add pin %d for irq %d\n",
3935 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3940 int io_apic_set_pci_routing(struct device *dev, int irq,
3941 struct io_apic_irq_attr *irq_attr)
3945 * Avoid pin reprogramming. PRTs typically include entries
3946 * with redundant pin->gsi mappings (but unique PCI devices);
3947 * we only program the IOAPIC on the first.
3949 ioapic = irq_attr->ioapic;
3950 pin = irq_attr->ioapic_pin;
3951 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3952 pr_debug("Pin %d-%d already programmed\n",
3953 mp_ioapics[ioapic].apicid, pin);
3956 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3958 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3961 u8 __init io_apic_unique_id(u8 id)
3963 #ifdef CONFIG_X86_32
3964 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3965 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3966 return io_apic_get_unique_id(nr_ioapics, id);
3971 DECLARE_BITMAP(used, 256);
3973 bitmap_zero(used, 256);
3974 for (i = 0; i < nr_ioapics; i++) {
3975 struct mpc_ioapic *ia = &mp_ioapics[i];
3976 __set_bit(ia->apicid, used);
3978 if (!test_bit(id, used))
3980 return find_first_zero_bit(used, 256);
3984 #ifdef CONFIG_X86_32
3985 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3987 union IO_APIC_reg_00 reg_00;
3988 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3990 unsigned long flags;
3994 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3995 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3996 * supports up to 16 on one shared APIC bus.
3998 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3999 * advantage of new APIC bus architecture.
4002 if (physids_empty(apic_id_map))
4003 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4005 raw_spin_lock_irqsave(&ioapic_lock, flags);
4006 reg_00.raw = io_apic_read(ioapic, 0);
4007 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4009 if (apic_id >= get_physical_broadcast()) {
4010 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4011 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4012 apic_id = reg_00.bits.ID;
4016 * Every APIC in a system must have a unique ID or we get lots of nice
4017 * 'stuck on smp_invalidate_needed IPI wait' messages.
4019 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4021 for (i = 0; i < get_physical_broadcast(); i++) {
4022 if (!apic->check_apicid_used(&apic_id_map, i))
4026 if (i == get_physical_broadcast())
4027 panic("Max apic_id exceeded!\n");
4029 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4030 "trying %d\n", ioapic, apic_id, i);
4035 apic->apicid_to_cpu_present(apic_id, &tmp);
4036 physids_or(apic_id_map, apic_id_map, tmp);
4038 if (reg_00.bits.ID != apic_id) {
4039 reg_00.bits.ID = apic_id;
4041 raw_spin_lock_irqsave(&ioapic_lock, flags);
4042 io_apic_write(ioapic, 0, reg_00.raw);
4043 reg_00.raw = io_apic_read(ioapic, 0);
4044 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4047 if (reg_00.bits.ID != apic_id) {
4048 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4053 apic_printk(APIC_VERBOSE, KERN_INFO
4054 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4060 int __init io_apic_get_version(int ioapic)
4062 union IO_APIC_reg_01 reg_01;
4063 unsigned long flags;
4065 raw_spin_lock_irqsave(&ioapic_lock, flags);
4066 reg_01.raw = io_apic_read(ioapic, 1);
4067 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4069 return reg_01.bits.version;
4072 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
4074 int ioapic, pin, idx;
4076 if (skip_ioapic_setup)
4079 ioapic = mp_find_ioapic(gsi);
4083 pin = mp_find_ioapic_pin(ioapic, gsi);
4087 idx = find_irq_entry(ioapic, pin, mp_INT);
4091 *trigger = irq_trigger(idx);
4092 *polarity = irq_polarity(idx);
4097 * This function currently is only a helper for the i386 smp boot process where
4098 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4099 * so mask in all cases should simply be apic->target_cpus()
4102 void __init setup_ioapic_dest(void)
4104 int pin, ioapic, irq, irq_entry;
4105 struct irq_desc *desc;
4106 const struct cpumask *mask;
4108 if (skip_ioapic_setup == 1)
4111 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4112 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4113 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4114 if (irq_entry == -1)
4116 irq = pin_2_irq(irq_entry, ioapic, pin);
4118 if ((ioapic > 0) && (irq > 16))
4121 desc = irq_to_desc(irq);
4124 * Honour affinities which have been set in early boot
4127 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4128 mask = desc->affinity;
4130 mask = apic->target_cpus();
4132 if (intr_remapping_enabled)
4133 set_ir_ioapic_affinity_irq_desc(desc, mask);
4135 set_ioapic_affinity_irq_desc(desc, mask);
4141 #define IOAPIC_RESOURCE_NAME_SIZE 11
4143 static struct resource *ioapic_resources;
4145 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4148 struct resource *res;
4152 if (nr_ioapics <= 0)
4155 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4158 mem = alloc_bootmem(n);
4161 mem += sizeof(struct resource) * nr_ioapics;
4163 for (i = 0; i < nr_ioapics; i++) {
4165 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4166 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4167 mem += IOAPIC_RESOURCE_NAME_SIZE;
4170 ioapic_resources = res;
4175 void __init ioapic_init_mappings(void)
4177 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4178 struct resource *ioapic_res;
4181 ioapic_res = ioapic_setup_resources(nr_ioapics);
4182 for (i = 0; i < nr_ioapics; i++) {
4183 if (smp_found_config) {
4184 ioapic_phys = mp_ioapics[i].apicaddr;
4185 #ifdef CONFIG_X86_32
4188 "WARNING: bogus zero IO-APIC "
4189 "address found in MPTABLE, "
4190 "disabling IO/APIC support!\n");
4191 smp_found_config = 0;
4192 skip_ioapic_setup = 1;
4193 goto fake_ioapic_page;
4197 #ifdef CONFIG_X86_32
4200 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4201 ioapic_phys = __pa(ioapic_phys);
4203 set_fixmap_nocache(idx, ioapic_phys);
4204 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4205 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4209 ioapic_res->start = ioapic_phys;
4210 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4215 void __init ioapic_insert_resources(void)
4218 struct resource *r = ioapic_resources;
4223 "IO APIC resources couldn't be allocated.\n");
4227 for (i = 0; i < nr_ioapics; i++) {
4228 insert_resource(&iomem_resource, r);
4233 int mp_find_ioapic(u32 gsi)
4237 /* Find the IOAPIC that manages this GSI. */
4238 for (i = 0; i < nr_ioapics; i++) {
4239 if ((gsi >= mp_gsi_routing[i].gsi_base)
4240 && (gsi <= mp_gsi_routing[i].gsi_end))
4244 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4248 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4250 if (WARN_ON(ioapic == -1))
4252 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4255 return gsi - mp_gsi_routing[ioapic].gsi_base;
4258 static int bad_ioapic(unsigned long address)
4260 if (nr_ioapics >= MAX_IO_APICS) {
4261 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4262 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4266 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4267 " found in table, skipping!\n");
4273 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4278 if (bad_ioapic(address))
4283 mp_ioapics[idx].type = MP_IOAPIC;
4284 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4285 mp_ioapics[idx].apicaddr = address;
4287 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4288 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4289 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4292 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4293 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4295 entries = io_apic_get_redir_entries(idx);
4296 mp_gsi_routing[idx].gsi_base = gsi_base;
4297 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4300 * The number of IO-APIC IRQ registers (== #pins):
4302 nr_ioapic_registers[idx] = entries;
4304 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4305 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4307 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4308 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4309 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4310 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4315 /* Enable IOAPIC early just for system timer */
4316 void __init pre_init_apic_IRQ0(void)
4318 struct irq_cfg *cfg;
4319 struct irq_desc *desc;
4321 printk(KERN_INFO "Early APIC setup for system timer0\n");
4323 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4325 desc = irq_to_desc_alloc_node(0, 0);
4330 add_pin_to_irq_node(cfg, 0, 0, 0);
4331 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4333 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);