2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
79 static struct ioapic {
81 * # of IRQ routing registers
85 * Saved state during suspend/resume, or while enabling intr-remap.
87 struct IO_APIC_route_entry *saved_registers;
89 struct mpc_ioapic mp_config;
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi gsi_config;
92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
93 } ioapics[MAX_IO_APICS];
95 #define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver
97 int mpc_ioapic_id(int id)
99 return ioapics[id].mp_config.apicid;
102 unsigned int mpc_ioapic_addr(int id)
104 return ioapics[id].mp_config.apicaddr;
107 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id)
109 return &ioapics[id].gsi_config;
114 /* The one past the highest gsi number used */
117 /* MP IRQ source entries */
118 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
120 /* # of MP IRQ source entries */
124 static int nr_irqs_gsi = NR_IRQS_LEGACY;
126 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
127 int mp_bus_id_to_type[MAX_MP_BUSSES];
130 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
132 int skip_ioapic_setup;
135 * disable_ioapic_support() - disables ioapic support at runtime
137 void disable_ioapic_support(void)
141 noioapicreroute = -1;
143 skip_ioapic_setup = 1;
146 static int __init parse_noapic(char *str)
148 /* disable IO-APIC */
149 disable_ioapic_support();
152 early_param("noapic", parse_noapic);
154 static int io_apic_setup_irq_pin(unsigned int irq, int node,
155 struct io_apic_irq_attr *attr);
157 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
158 void mp_save_irq(struct mpc_intsrc *m)
162 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
163 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
164 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
165 m->srcbusirq, m->dstapic, m->dstirq);
167 for (i = 0; i < mp_irq_entries; i++) {
168 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
172 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
173 if (++mp_irq_entries == MAX_IRQ_SOURCES)
174 panic("Max # of irq sources exceeded!!\n");
177 struct irq_pin_list {
179 struct irq_pin_list *next;
182 static struct irq_pin_list *alloc_irq_pin_list(int node)
184 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
188 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189 #ifdef CONFIG_SPARSE_IRQ
190 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
192 static struct irq_cfg irq_cfgx[NR_IRQS];
195 int __init arch_early_irq_init(void)
200 if (!legacy_pic->nr_legacy_irqs) {
205 for (i = 0; i < nr_ioapics; i++) {
206 ioapics[i].saved_registers =
207 kzalloc(sizeof(struct IO_APIC_route_entry) *
208 ioapics[i].nr_registers, GFP_KERNEL);
209 if (!ioapics[i].saved_registers)
210 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
214 count = ARRAY_SIZE(irq_cfgx);
215 node = cpu_to_node(0);
217 /* Make sure the legacy interrupts are marked in the bitmap */
218 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
220 for (i = 0; i < count; i++) {
221 irq_set_chip_data(i, &cfg[i]);
222 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
223 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
225 * For legacy IRQ's, start with assigning irq0 to irq15 to
226 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
228 if (i < legacy_pic->nr_legacy_irqs) {
229 cfg[i].vector = IRQ0_VECTOR + i;
230 cpumask_set_cpu(0, cfg[i].domain);
237 #ifdef CONFIG_SPARSE_IRQ
238 static struct irq_cfg *irq_cfg(unsigned int irq)
240 return irq_get_chip_data(irq);
243 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
247 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
250 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
252 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
256 free_cpumask_var(cfg->domain);
262 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
266 irq_set_chip_data(at, NULL);
267 free_cpumask_var(cfg->domain);
268 free_cpumask_var(cfg->old_domain);
274 struct irq_cfg *irq_cfg(unsigned int irq)
276 return irq < nr_irqs ? irq_cfgx + irq : NULL;
279 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
281 return irq_cfgx + irq;
284 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
288 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
290 int res = irq_alloc_desc_at(at, node);
296 cfg = irq_get_chip_data(at);
301 cfg = alloc_irq_cfg(at, node);
303 irq_set_chip_data(at, cfg);
309 static int alloc_irq_from(unsigned int from, int node)
311 return irq_alloc_desc_from(from, node);
314 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
316 free_irq_cfg(at, cfg);
322 unsigned int unused[3];
324 unsigned int unused2[11];
328 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
330 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
331 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
334 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
336 struct io_apic __iomem *io_apic = io_apic_base(apic);
337 writel(vector, &io_apic->eoi);
340 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
342 struct io_apic __iomem *io_apic = io_apic_base(apic);
343 writel(reg, &io_apic->index);
344 return readl(&io_apic->data);
347 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(reg, &io_apic->index);
351 writel(value, &io_apic->data);
355 * Re-write a value: to be used for read-modify-write
356 * cycles where the read already set up the index register.
358 * Older SiS APIC requires we rewrite the index register
360 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(reg, &io_apic->index);
366 writel(value, &io_apic->data);
369 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
371 struct irq_pin_list *entry;
374 raw_spin_lock_irqsave(&ioapic_lock, flags);
375 for_each_irq_pin(entry, cfg->irq_2_pin) {
380 reg = io_apic_read(entry->apic, 0x10 + pin*2);
381 /* Is the remote IRR bit set? */
382 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
383 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
393 struct { u32 w1, w2; };
394 struct IO_APIC_route_entry entry;
397 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
399 union entry_union eu;
401 raw_spin_lock_irqsave(&ioapic_lock, flags);
402 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
403 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409 * When we write a new IO APIC routing entry, we need to write the high
410 * word first! If the mask bit in the low word is clear, we will enable
411 * the interrupt, and we need to make sure the entry is fully populated
412 * before that happens.
415 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
417 union entry_union eu = {{0, 0}};
420 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
421 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
424 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
427 raw_spin_lock_irqsave(&ioapic_lock, flags);
428 __ioapic_write_entry(apic, pin, e);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
433 * When we mask an IO APIC routing entry, we need to write the low
434 * word first, in order to set the mask bit before we change the
437 static void ioapic_mask_entry(int apic, int pin)
440 union entry_union eu = { .entry.mask = 1 };
442 raw_spin_lock_irqsave(&ioapic_lock, flags);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
444 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
445 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
449 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
450 * shared ISA-space IRQs, so we have to support them. We are super
451 * fast in the common case, and fast for shared ISA-space IRQs.
454 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
456 struct irq_pin_list **last, *entry;
458 /* don't allow duplicates */
459 last = &cfg->irq_2_pin;
460 for_each_irq_pin(entry, cfg->irq_2_pin) {
461 if (entry->apic == apic && entry->pin == pin)
466 entry = alloc_irq_pin_list(node);
468 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
479 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
481 if (__add_pin_to_irq_node(cfg, node, apic, pin))
482 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
486 * Reroute an IRQ to a different pin.
488 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
489 int oldapic, int oldpin,
490 int newapic, int newpin)
492 struct irq_pin_list *entry;
494 for_each_irq_pin(entry, cfg->irq_2_pin) {
495 if (entry->apic == oldapic && entry->pin == oldpin) {
496 entry->apic = newapic;
498 /* every one is different, right? */
503 /* old apic/pin didn't exist, so just add new ones */
504 add_pin_to_irq_node(cfg, node, newapic, newpin);
507 static void __io_apic_modify_irq(struct irq_pin_list *entry,
508 int mask_and, int mask_or,
509 void (*final)(struct irq_pin_list *entry))
511 unsigned int reg, pin;
514 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
517 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
522 static void io_apic_modify_irq(struct irq_cfg *cfg,
523 int mask_and, int mask_or,
524 void (*final)(struct irq_pin_list *entry))
526 struct irq_pin_list *entry;
528 for_each_irq_pin(entry, cfg->irq_2_pin)
529 __io_apic_modify_irq(entry, mask_and, mask_or, final);
532 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
534 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
535 IO_APIC_REDIR_MASKED, NULL);
538 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
540 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
541 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
544 static void io_apic_sync(struct irq_pin_list *entry)
547 * Synchronize the IO-APIC and the CPU by doing
548 * a dummy read from the IO-APIC
550 struct io_apic __iomem *io_apic;
551 io_apic = io_apic_base(entry->apic);
552 readl(&io_apic->data);
555 static void mask_ioapic(struct irq_cfg *cfg)
559 raw_spin_lock_irqsave(&ioapic_lock, flags);
560 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
561 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
564 static void mask_ioapic_irq(struct irq_data *data)
566 mask_ioapic(data->chip_data);
569 static void __unmask_ioapic(struct irq_cfg *cfg)
571 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
574 static void unmask_ioapic(struct irq_cfg *cfg)
578 raw_spin_lock_irqsave(&ioapic_lock, flags);
579 __unmask_ioapic(cfg);
580 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
583 static void unmask_ioapic_irq(struct irq_data *data)
585 unmask_ioapic(data->chip_data);
588 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
590 struct IO_APIC_route_entry entry;
592 /* Check delivery_mode to be sure we're not clearing an SMI pin */
593 entry = ioapic_read_entry(apic, pin);
594 if (entry.delivery_mode == dest_SMI)
597 * Disable it in the IO-APIC irq-routing table:
599 ioapic_mask_entry(apic, pin);
602 static void clear_IO_APIC (void)
606 for (apic = 0; apic < nr_ioapics; apic++)
607 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
608 clear_IO_APIC_pin(apic, pin);
613 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
614 * specific CPU-side IRQs.
618 static int pirq_entries[MAX_PIRQS] = {
619 [0 ... MAX_PIRQS - 1] = -1
622 static int __init ioapic_pirq_setup(char *str)
625 int ints[MAX_PIRQS+1];
627 get_options(str, ARRAY_SIZE(ints), ints);
629 apic_printk(APIC_VERBOSE, KERN_INFO
630 "PIRQ redirection, working around broken MP-BIOS.\n");
632 if (ints[0] < MAX_PIRQS)
635 for (i = 0; i < max; i++) {
636 apic_printk(APIC_VERBOSE, KERN_DEBUG
637 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
639 * PIRQs are mapped upside down, usually.
641 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
646 __setup("pirq=", ioapic_pirq_setup);
647 #endif /* CONFIG_X86_32 */
650 * Saves all the IO-APIC RTE's
652 int save_ioapic_entries(void)
657 for (apic = 0; apic < nr_ioapics; apic++) {
658 if (!ioapics[apic].saved_registers) {
663 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
664 ioapics[apic].saved_registers[pin] =
665 ioapic_read_entry(apic, pin);
672 * Mask all IO APIC entries.
674 void mask_ioapic_entries(void)
678 for (apic = 0; apic < nr_ioapics; apic++) {
679 if (!ioapics[apic].saved_registers)
682 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
683 struct IO_APIC_route_entry entry;
685 entry = ioapics[apic].saved_registers[pin];
688 ioapic_write_entry(apic, pin, entry);
695 * Restore IO APIC entries which was saved in the ioapic structure.
697 int restore_ioapic_entries(void)
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 if (!ioapics[apic].saved_registers)
705 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
706 ioapic_write_entry(apic, pin,
707 ioapics[apic].saved_registers[pin]);
713 * Find the IRQ entry number of a certain pin.
715 static int find_irq_entry(int apic, int pin, int type)
719 for (i = 0; i < mp_irq_entries; i++)
720 if (mp_irqs[i].irqtype == type &&
721 (mp_irqs[i].dstapic == mpc_ioapic_id(apic) ||
722 mp_irqs[i].dstapic == MP_APIC_ALL) &&
723 mp_irqs[i].dstirq == pin)
730 * Find the pin to which IRQ[irq] (ISA) is connected
732 static int __init find_isa_irq_pin(int irq, int type)
736 for (i = 0; i < mp_irq_entries; i++) {
737 int lbus = mp_irqs[i].srcbus;
739 if (test_bit(lbus, mp_bus_not_pci) &&
740 (mp_irqs[i].irqtype == type) &&
741 (mp_irqs[i].srcbusirq == irq))
743 return mp_irqs[i].dstirq;
748 static int __init find_isa_irq_apic(int irq, int type)
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].srcbus;
755 if (test_bit(lbus, mp_bus_not_pci) &&
756 (mp_irqs[i].irqtype == type) &&
757 (mp_irqs[i].srcbusirq == irq))
760 if (i < mp_irq_entries) {
762 for(apic = 0; apic < nr_ioapics; apic++) {
763 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic)
771 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
773 * EISA Edge/Level control register, ELCR
775 static int EISA_ELCR(unsigned int irq)
777 if (irq < legacy_pic->nr_legacy_irqs) {
778 unsigned int port = 0x4d0 + (irq >> 3);
779 return (inb(port) >> (irq & 7)) & 1;
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "Broken MPtable reports ISA irq %d\n", irq);
788 /* ISA interrupts are always polarity zero edge triggered,
789 * when listed as conforming in the MP table. */
791 #define default_ISA_trigger(idx) (0)
792 #define default_ISA_polarity(idx) (0)
794 /* EISA interrupts are always polarity zero and can be edge or level
795 * trigger depending on the ELCR value. If an interrupt is listed as
796 * EISA conforming in the MP table, that means its trigger type must
797 * be read in from the ELCR */
799 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
800 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
802 /* PCI interrupts are always polarity one level triggered,
803 * when listed as conforming in the MP table. */
805 #define default_PCI_trigger(idx) (1)
806 #define default_PCI_polarity(idx) (1)
808 /* MCA interrupts are always polarity zero level triggered,
809 * when listed as conforming in the MP table. */
811 #define default_MCA_trigger(idx) (1)
812 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
814 static int irq_polarity(int idx)
816 int bus = mp_irqs[idx].srcbus;
820 * Determine IRQ line polarity (high active or low active):
822 switch (mp_irqs[idx].irqflag & 3)
824 case 0: /* conforms, ie. bus-type dependent polarity */
825 if (test_bit(bus, mp_bus_not_pci))
826 polarity = default_ISA_polarity(idx);
828 polarity = default_PCI_polarity(idx);
830 case 1: /* high active */
835 case 2: /* reserved */
837 printk(KERN_WARNING "broken BIOS!!\n");
841 case 3: /* low active */
846 default: /* invalid */
848 printk(KERN_WARNING "broken BIOS!!\n");
856 static int irq_trigger(int idx)
858 int bus = mp_irqs[idx].srcbus;
862 * Determine IRQ trigger mode (edge or level sensitive):
864 switch ((mp_irqs[idx].irqflag>>2) & 3)
866 case 0: /* conforms, ie. bus-type dependent */
867 if (test_bit(bus, mp_bus_not_pci))
868 trigger = default_ISA_trigger(idx);
870 trigger = default_PCI_trigger(idx);
871 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
872 switch (mp_bus_id_to_type[bus]) {
873 case MP_BUS_ISA: /* ISA pin */
875 /* set before the switch */
878 case MP_BUS_EISA: /* EISA pin */
880 trigger = default_EISA_trigger(idx);
883 case MP_BUS_PCI: /* PCI pin */
885 /* set before the switch */
888 case MP_BUS_MCA: /* MCA pin */
890 trigger = default_MCA_trigger(idx);
895 printk(KERN_WARNING "broken BIOS!!\n");
907 case 2: /* reserved */
909 printk(KERN_WARNING "broken BIOS!!\n");
918 default: /* invalid */
920 printk(KERN_WARNING "broken BIOS!!\n");
928 static int pin_2_irq(int idx, int apic, int pin)
931 int bus = mp_irqs[idx].srcbus;
932 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
935 * Debugging check, we are in big trouble if this message pops up!
937 if (mp_irqs[idx].dstirq != pin)
938 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
940 if (test_bit(bus, mp_bus_not_pci)) {
941 irq = mp_irqs[idx].srcbusirq;
943 u32 gsi = gsi_cfg->gsi_base + pin;
945 if (gsi >= NR_IRQS_LEGACY)
953 * PCI IRQ command line redirection. Yes, limits are hardcoded.
955 if ((pin >= 16) && (pin <= 23)) {
956 if (pirq_entries[pin-16] != -1) {
957 if (!pirq_entries[pin-16]) {
958 apic_printk(APIC_VERBOSE, KERN_DEBUG
959 "disabling PIRQ%d\n", pin-16);
961 irq = pirq_entries[pin-16];
962 apic_printk(APIC_VERBOSE, KERN_DEBUG
963 "using PIRQ%d -> IRQ %d\n",
974 * Find a specific PCI IRQ entry.
975 * Not an __init, possibly needed by modules
977 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
978 struct io_apic_irq_attr *irq_attr)
980 int apic, i, best_guess = -1;
982 apic_printk(APIC_DEBUG,
983 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
985 if (test_bit(bus, mp_bus_not_pci)) {
986 apic_printk(APIC_VERBOSE,
987 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
990 for (i = 0; i < mp_irq_entries; i++) {
991 int lbus = mp_irqs[i].srcbus;
993 for (apic = 0; apic < nr_ioapics; apic++)
994 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic ||
995 mp_irqs[i].dstapic == MP_APIC_ALL)
998 if (!test_bit(lbus, mp_bus_not_pci) &&
999 !mp_irqs[i].irqtype &&
1001 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1002 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1004 if (!(apic || IO_APIC_IRQ(irq)))
1007 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1008 set_io_apic_irq_attr(irq_attr, apic,
1015 * Use the first all-but-pin matching entry as a
1016 * best-guess fuzzy result for broken mptables.
1018 if (best_guess < 0) {
1019 set_io_apic_irq_attr(irq_attr, apic,
1029 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1031 void lock_vector_lock(void)
1033 /* Used to the online set of cpus does not change
1034 * during assign_irq_vector.
1036 raw_spin_lock(&vector_lock);
1039 void unlock_vector_lock(void)
1041 raw_spin_unlock(&vector_lock);
1045 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1048 * NOTE! The local APIC isn't very good at handling
1049 * multiple interrupts at the same interrupt level.
1050 * As the interrupt level is determined by taking the
1051 * vector number and shifting that right by 4, we
1052 * want to spread these out a bit so that they don't
1053 * all fall in the same interrupt level.
1055 * Also, we've got to be careful not to trash gate
1056 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1058 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1059 static int current_offset = VECTOR_OFFSET_START % 8;
1060 unsigned int old_vector;
1062 cpumask_var_t tmp_mask;
1064 if (cfg->move_in_progress)
1067 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1070 old_vector = cfg->vector;
1072 cpumask_and(tmp_mask, mask, cpu_online_mask);
1073 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1074 if (!cpumask_empty(tmp_mask)) {
1075 free_cpumask_var(tmp_mask);
1080 /* Only try and allocate irqs on cpus that are present */
1082 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1086 apic->vector_allocation_domain(cpu, tmp_mask);
1088 vector = current_vector;
1089 offset = current_offset;
1092 if (vector >= first_system_vector) {
1093 /* If out of vectors on large boxen, must share them. */
1094 offset = (offset + 1) % 8;
1095 vector = FIRST_EXTERNAL_VECTOR + offset;
1097 if (unlikely(current_vector == vector))
1100 if (test_bit(vector, used_vectors))
1103 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1104 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1107 current_vector = vector;
1108 current_offset = offset;
1110 cfg->move_in_progress = 1;
1111 cpumask_copy(cfg->old_domain, cfg->domain);
1113 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1114 per_cpu(vector_irq, new_cpu)[vector] = irq;
1115 cfg->vector = vector;
1116 cpumask_copy(cfg->domain, tmp_mask);
1120 free_cpumask_var(tmp_mask);
1124 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1127 unsigned long flags;
1129 raw_spin_lock_irqsave(&vector_lock, flags);
1130 err = __assign_irq_vector(irq, cfg, mask);
1131 raw_spin_unlock_irqrestore(&vector_lock, flags);
1135 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1139 BUG_ON(!cfg->vector);
1141 vector = cfg->vector;
1142 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1143 per_cpu(vector_irq, cpu)[vector] = -1;
1146 cpumask_clear(cfg->domain);
1148 if (likely(!cfg->move_in_progress))
1150 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1151 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1153 if (per_cpu(vector_irq, cpu)[vector] != irq)
1155 per_cpu(vector_irq, cpu)[vector] = -1;
1159 cfg->move_in_progress = 0;
1162 void __setup_vector_irq(int cpu)
1164 /* Initialize vector_irq on a new cpu */
1166 struct irq_cfg *cfg;
1169 * vector_lock will make sure that we don't run into irq vector
1170 * assignments that might be happening on another cpu in parallel,
1171 * while we setup our initial vector to irq mappings.
1173 raw_spin_lock(&vector_lock);
1174 /* Mark the inuse vectors */
1175 for_each_active_irq(irq) {
1176 cfg = irq_get_chip_data(irq);
1180 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1181 * will be part of the irq_cfg's domain.
1183 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1184 cpumask_set_cpu(cpu, cfg->domain);
1186 if (!cpumask_test_cpu(cpu, cfg->domain))
1188 vector = cfg->vector;
1189 per_cpu(vector_irq, cpu)[vector] = irq;
1191 /* Mark the free vectors */
1192 for (vector = 0; vector < NR_VECTORS; ++vector) {
1193 irq = per_cpu(vector_irq, cpu)[vector];
1198 if (!cpumask_test_cpu(cpu, cfg->domain))
1199 per_cpu(vector_irq, cpu)[vector] = -1;
1201 raw_spin_unlock(&vector_lock);
1204 static struct irq_chip ioapic_chip;
1205 static struct irq_chip ir_ioapic_chip;
1207 #ifdef CONFIG_X86_32
1208 static inline int IO_APIC_irq_trigger(int irq)
1212 for (apic = 0; apic < nr_ioapics; apic++) {
1213 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1214 idx = find_irq_entry(apic, pin, mp_INT);
1215 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1216 return irq_trigger(idx);
1220 * nonexistent IRQs are edge default
1225 static inline int IO_APIC_irq_trigger(int irq)
1231 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1232 unsigned long trigger)
1234 struct irq_chip *chip = &ioapic_chip;
1235 irq_flow_handler_t hdl;
1238 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1239 trigger == IOAPIC_LEVEL) {
1240 irq_set_status_flags(irq, IRQ_LEVEL);
1243 irq_clear_status_flags(irq, IRQ_LEVEL);
1247 if (irq_remapped(cfg)) {
1248 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1249 chip = &ir_ioapic_chip;
1250 fasteoi = trigger != 0;
1253 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1254 irq_set_chip_and_handler_name(irq, chip, hdl,
1255 fasteoi ? "fasteoi" : "edge");
1259 static int setup_ir_ioapic_entry(int irq,
1260 struct IR_IO_APIC_route_entry *entry,
1261 unsigned int destination, int vector,
1262 struct io_apic_irq_attr *attr)
1266 int apic_id = mpc_ioapic_id(attr->ioapic);
1267 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1270 pr_warn("No mapping iommu for ioapic %d\n", apic_id);
1274 index = alloc_irte(iommu, irq, 1);
1276 pr_warn("Failed to allocate IRTE for ioapic %d\n", apic_id);
1280 prepare_irte(&irte, vector, destination);
1282 /* Set source-id of interrupt request */
1283 set_ioapic_sid(&irte, apic_id);
1285 modify_irte(irq, &irte);
1287 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1288 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1289 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1290 "Avail:%X Vector:%02X Dest:%08X "
1291 "SID:%04X SQ:%X SVT:%X)\n",
1292 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1293 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1294 irte.avail, irte.vector, irte.dest_id,
1295 irte.sid, irte.sq, irte.svt);
1297 memset(entry, 0, sizeof(*entry));
1299 entry->index2 = (index >> 15) & 0x1;
1302 entry->index = (index & 0x7fff);
1304 * IO-APIC RTE will be configured with virtual vector.
1305 * irq handler will do the explicit EOI to the io-apic.
1307 entry->vector = attr->ioapic_pin;
1308 entry->mask = 0; /* enable IRQ */
1309 entry->trigger = attr->trigger;
1310 entry->polarity = attr->polarity;
1312 /* Mask level triggered irqs.
1313 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1321 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1322 unsigned int destination, int vector,
1323 struct io_apic_irq_attr *attr)
1325 if (intr_remapping_enabled)
1326 return setup_ir_ioapic_entry(irq,
1327 (struct IR_IO_APIC_route_entry *)entry,
1328 destination, vector, attr);
1330 memset(entry, 0, sizeof(*entry));
1332 entry->delivery_mode = apic->irq_delivery_mode;
1333 entry->dest_mode = apic->irq_dest_mode;
1334 entry->dest = destination;
1335 entry->vector = vector;
1336 entry->mask = 0; /* enable IRQ */
1337 entry->trigger = attr->trigger;
1338 entry->polarity = attr->polarity;
1341 * Mask level triggered irqs.
1342 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1350 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1351 struct io_apic_irq_attr *attr)
1353 struct IO_APIC_route_entry entry;
1356 if (!IO_APIC_IRQ(irq))
1359 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1360 * controllers like 8259. Now that IO-APIC can handle this irq, update
1363 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1364 apic->vector_allocation_domain(0, cfg->domain);
1366 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1369 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1371 apic_printk(APIC_VERBOSE,KERN_DEBUG
1372 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1373 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1374 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1375 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1377 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1378 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1379 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1380 __clear_irq_vector(irq, cfg);
1385 ioapic_register_intr(irq, cfg, attr->trigger);
1386 if (irq < legacy_pic->nr_legacy_irqs)
1387 legacy_pic->mask(irq);
1389 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1392 static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1397 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1398 mpc_ioapic_id(apic_id), pin);
1402 static void __init __io_apic_setup_irqs(unsigned int apic_id)
1404 int idx, node = cpu_to_node(0);
1405 struct io_apic_irq_attr attr;
1406 unsigned int pin, irq;
1408 for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) {
1409 idx = find_irq_entry(apic_id, pin, mp_INT);
1410 if (io_apic_pin_not_connected(idx, apic_id, pin))
1413 irq = pin_2_irq(idx, apic_id, pin);
1415 if ((apic_id > 0) && (irq > 16))
1419 * Skip the timer IRQ if there's a quirk handler
1420 * installed and if it returns 1:
1422 if (apic->multi_timer_check &&
1423 apic->multi_timer_check(apic_id, irq))
1426 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1429 io_apic_setup_irq_pin(irq, node, &attr);
1433 static void __init setup_IO_APIC_irqs(void)
1435 unsigned int apic_id;
1437 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1439 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1440 __io_apic_setup_irqs(apic_id);
1444 * for the gsit that is not in first ioapic
1445 * but could not use acpi_register_gsi()
1446 * like some special sci in IBM x3330
1448 void setup_IO_APIC_irq_extra(u32 gsi)
1450 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1451 struct io_apic_irq_attr attr;
1454 * Convert 'gsi' to 'ioapic.pin'.
1456 apic_id = mp_find_ioapic(gsi);
1460 pin = mp_find_ioapic_pin(apic_id, gsi);
1461 idx = find_irq_entry(apic_id, pin, mp_INT);
1465 irq = pin_2_irq(idx, apic_id, pin);
1467 /* Only handle the non legacy irqs on secondary ioapics */
1468 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1471 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1474 io_apic_setup_irq_pin_once(irq, node, &attr);
1478 * Set up the timer pin, possibly with the 8259A-master behind.
1480 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1483 struct IO_APIC_route_entry entry;
1485 if (intr_remapping_enabled)
1488 memset(&entry, 0, sizeof(entry));
1491 * We use logical delivery to get the timer IRQ
1494 entry.dest_mode = apic->irq_dest_mode;
1495 entry.mask = 0; /* don't mask IRQ for edge */
1496 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1497 entry.delivery_mode = apic->irq_delivery_mode;
1500 entry.vector = vector;
1503 * The timer IRQ doesn't have to know that behind the
1504 * scene we may have a 8259A-master in AEOI mode ...
1506 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1510 * Add it to the IO-APIC irq-routing table:
1512 ioapic_write_entry(apic_id, pin, entry);
1516 __apicdebuginit(void) print_IO_APIC(void)
1519 union IO_APIC_reg_00 reg_00;
1520 union IO_APIC_reg_01 reg_01;
1521 union IO_APIC_reg_02 reg_02;
1522 union IO_APIC_reg_03 reg_03;
1523 unsigned long flags;
1524 struct irq_cfg *cfg;
1527 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1528 for (i = 0; i < nr_ioapics; i++)
1529 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1530 mpc_ioapic_id(i), ioapics[i].nr_registers);
1533 * We are a bit conservative about what we expect. We have to
1534 * know about every hardware change ASAP.
1536 printk(KERN_INFO "testing the IO APIC.......................\n");
1538 for (apic = 0; apic < nr_ioapics; apic++) {
1540 raw_spin_lock_irqsave(&ioapic_lock, flags);
1541 reg_00.raw = io_apic_read(apic, 0);
1542 reg_01.raw = io_apic_read(apic, 1);
1543 if (reg_01.bits.version >= 0x10)
1544 reg_02.raw = io_apic_read(apic, 2);
1545 if (reg_01.bits.version >= 0x20)
1546 reg_03.raw = io_apic_read(apic, 3);
1547 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1550 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic));
1551 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1552 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1553 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1554 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1556 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1557 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1558 reg_01.bits.entries);
1560 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1561 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1562 reg_01.bits.version);
1565 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1566 * but the value of reg_02 is read as the previous read register
1567 * value, so ignore it if reg_02 == reg_01.
1569 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1570 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1571 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1575 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1576 * or reg_03, but the value of reg_0[23] is read as the previous read
1577 * register value, so ignore it if reg_03 == reg_0[12].
1579 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1580 reg_03.raw != reg_01.raw) {
1581 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1582 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1585 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1587 if (intr_remapping_enabled) {
1588 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1589 " Pol Stat Indx2 Zero Vect:\n");
1591 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1592 " Stat Dmod Deli Vect:\n");
1595 for (i = 0; i <= reg_01.bits.entries; i++) {
1596 if (intr_remapping_enabled) {
1597 struct IO_APIC_route_entry entry;
1598 struct IR_IO_APIC_route_entry *ir_entry;
1600 entry = ioapic_read_entry(apic, i);
1601 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1602 printk(KERN_DEBUG " %02x %04X ",
1606 printk("%1d %1d %1d %1d %1d "
1607 "%1d %1d %X %02X\n",
1613 ir_entry->delivery_status,
1619 struct IO_APIC_route_entry entry;
1621 entry = ioapic_read_entry(apic, i);
1622 printk(KERN_DEBUG " %02x %02X ",
1626 printk("%1d %1d %1d %1d %1d "
1632 entry.delivery_status,
1634 entry.delivery_mode,
1641 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1642 for_each_active_irq(irq) {
1643 struct irq_pin_list *entry;
1645 cfg = irq_get_chip_data(irq);
1648 entry = cfg->irq_2_pin;
1651 printk(KERN_DEBUG "IRQ%d ", irq);
1652 for_each_irq_pin(entry, cfg->irq_2_pin)
1653 printk("-> %d:%d", entry->apic, entry->pin);
1657 printk(KERN_INFO ".................................... done.\n");
1662 __apicdebuginit(void) print_APIC_field(int base)
1668 for (i = 0; i < 8; i++)
1669 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1671 printk(KERN_CONT "\n");
1674 __apicdebuginit(void) print_local_APIC(void *dummy)
1676 unsigned int i, v, ver, maxlvt;
1679 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1680 smp_processor_id(), hard_smp_processor_id());
1681 v = apic_read(APIC_ID);
1682 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1683 v = apic_read(APIC_LVR);
1684 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1685 ver = GET_APIC_VERSION(v);
1686 maxlvt = lapic_get_maxlvt();
1688 v = apic_read(APIC_TASKPRI);
1689 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1691 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1692 if (!APIC_XAPIC(ver)) {
1693 v = apic_read(APIC_ARBPRI);
1694 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1695 v & APIC_ARBPRI_MASK);
1697 v = apic_read(APIC_PROCPRI);
1698 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1702 * Remote read supported only in the 82489DX and local APIC for
1703 * Pentium processors.
1705 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1706 v = apic_read(APIC_RRR);
1707 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1710 v = apic_read(APIC_LDR);
1711 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1712 if (!x2apic_enabled()) {
1713 v = apic_read(APIC_DFR);
1714 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1716 v = apic_read(APIC_SPIV);
1717 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1719 printk(KERN_DEBUG "... APIC ISR field:\n");
1720 print_APIC_field(APIC_ISR);
1721 printk(KERN_DEBUG "... APIC TMR field:\n");
1722 print_APIC_field(APIC_TMR);
1723 printk(KERN_DEBUG "... APIC IRR field:\n");
1724 print_APIC_field(APIC_IRR);
1726 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1727 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1728 apic_write(APIC_ESR, 0);
1730 v = apic_read(APIC_ESR);
1731 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1734 icr = apic_icr_read();
1735 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1736 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1738 v = apic_read(APIC_LVTT);
1739 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1741 if (maxlvt > 3) { /* PC is LVT#4. */
1742 v = apic_read(APIC_LVTPC);
1743 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1745 v = apic_read(APIC_LVT0);
1746 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1747 v = apic_read(APIC_LVT1);
1748 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1750 if (maxlvt > 2) { /* ERR is LVT#3. */
1751 v = apic_read(APIC_LVTERR);
1752 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1755 v = apic_read(APIC_TMICT);
1756 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1757 v = apic_read(APIC_TMCCT);
1758 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1759 v = apic_read(APIC_TDCR);
1760 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1762 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1763 v = apic_read(APIC_EFEAT);
1764 maxlvt = (v >> 16) & 0xff;
1765 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1766 v = apic_read(APIC_ECTRL);
1767 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1768 for (i = 0; i < maxlvt; i++) {
1769 v = apic_read(APIC_EILVTn(i));
1770 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1776 __apicdebuginit(void) print_local_APICs(int maxcpu)
1784 for_each_online_cpu(cpu) {
1787 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1792 __apicdebuginit(void) print_PIC(void)
1795 unsigned long flags;
1797 if (!legacy_pic->nr_legacy_irqs)
1800 printk(KERN_DEBUG "\nprinting PIC contents\n");
1802 raw_spin_lock_irqsave(&i8259A_lock, flags);
1804 v = inb(0xa1) << 8 | inb(0x21);
1805 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1807 v = inb(0xa0) << 8 | inb(0x20);
1808 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1812 v = inb(0xa0) << 8 | inb(0x20);
1816 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1818 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1820 v = inb(0x4d1) << 8 | inb(0x4d0);
1821 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1824 static int __initdata show_lapic = 1;
1825 static __init int setup_show_lapic(char *arg)
1829 if (strcmp(arg, "all") == 0) {
1830 show_lapic = CONFIG_NR_CPUS;
1832 get_option(&arg, &num);
1839 __setup("show_lapic=", setup_show_lapic);
1841 __apicdebuginit(int) print_ICs(void)
1843 if (apic_verbosity == APIC_QUIET)
1848 /* don't print out if apic is not there */
1849 if (!cpu_has_apic && !apic_from_smp_config())
1852 print_local_APICs(show_lapic);
1858 late_initcall(print_ICs);
1861 /* Where if anywhere is the i8259 connect in external int mode */
1862 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1864 void __init enable_IO_APIC(void)
1866 int i8259_apic, i8259_pin;
1869 if (!legacy_pic->nr_legacy_irqs)
1872 for(apic = 0; apic < nr_ioapics; apic++) {
1874 /* See if any of the pins is in ExtINT mode */
1875 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1876 struct IO_APIC_route_entry entry;
1877 entry = ioapic_read_entry(apic, pin);
1879 /* If the interrupt line is enabled and in ExtInt mode
1880 * I have found the pin where the i8259 is connected.
1882 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1883 ioapic_i8259.apic = apic;
1884 ioapic_i8259.pin = pin;
1890 /* Look to see what if the MP table has reported the ExtINT */
1891 /* If we could not find the appropriate pin by looking at the ioapic
1892 * the i8259 probably is not connected the ioapic but give the
1893 * mptable a chance anyway.
1895 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1896 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1897 /* Trust the MP table if nothing is setup in the hardware */
1898 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1899 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1900 ioapic_i8259.pin = i8259_pin;
1901 ioapic_i8259.apic = i8259_apic;
1903 /* Complain if the MP table and the hardware disagree */
1904 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1905 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1907 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1911 * Do not trust the IO-APIC being empty at bootup
1917 * Not an __init, needed by the reboot code
1919 void disable_IO_APIC(void)
1922 * Clear the IO-APIC before rebooting:
1926 if (!legacy_pic->nr_legacy_irqs)
1930 * If the i8259 is routed through an IOAPIC
1931 * Put that IOAPIC in virtual wire mode
1932 * so legacy interrupts can be delivered.
1934 * With interrupt-remapping, for now we will use virtual wire A mode,
1935 * as virtual wire B is little complex (need to configure both
1936 * IOAPIC RTE as well as interrupt-remapping table entry).
1937 * As this gets called during crash dump, keep this simple for now.
1939 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1940 struct IO_APIC_route_entry entry;
1942 memset(&entry, 0, sizeof(entry));
1943 entry.mask = 0; /* Enabled */
1944 entry.trigger = 0; /* Edge */
1946 entry.polarity = 0; /* High */
1947 entry.delivery_status = 0;
1948 entry.dest_mode = 0; /* Physical */
1949 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1951 entry.dest = read_apic_id();
1954 * Add it to the IO-APIC irq-routing table:
1956 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1960 * Use virtual wire A mode when interrupt remapping is enabled.
1962 if (cpu_has_apic || apic_from_smp_config())
1963 disconnect_bsp_APIC(!intr_remapping_enabled &&
1964 ioapic_i8259.pin != -1);
1967 #ifdef CONFIG_X86_32
1969 * function to set the IO-APIC physical IDs based on the
1970 * values stored in the MPC table.
1972 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1974 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1976 union IO_APIC_reg_00 reg_00;
1977 physid_mask_t phys_id_present_map;
1980 unsigned char old_id;
1981 unsigned long flags;
1984 * This is broken; anything with a real cpu count has to
1985 * circumvent this idiocy regardless.
1987 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1990 * Set the IOAPIC ID to the value stored in the MPC table.
1992 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1994 /* Read the register 0 value */
1995 raw_spin_lock_irqsave(&ioapic_lock, flags);
1996 reg_00.raw = io_apic_read(apic_id, 0);
1997 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1999 old_id = mpc_ioapic_id(apic_id);
2001 if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) {
2002 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2003 apic_id, mpc_ioapic_id(apic_id));
2004 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2006 ioapics[apic_id].mp_config.apicid = reg_00.bits.ID;
2010 * Sanity check, is the ID really free? Every APIC in a
2011 * system must have a unique ID or we get lots of nice
2012 * 'stuck on smp_invalidate_needed IPI wait' messages.
2014 if (apic->check_apicid_used(&phys_id_present_map,
2015 mpc_ioapic_id(apic_id))) {
2016 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2017 apic_id, mpc_ioapic_id(apic_id));
2018 for (i = 0; i < get_physical_broadcast(); i++)
2019 if (!physid_isset(i, phys_id_present_map))
2021 if (i >= get_physical_broadcast())
2022 panic("Max APIC ID exceeded!\n");
2023 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2025 physid_set(i, phys_id_present_map);
2026 ioapics[apic_id].mp_config.apicid = i;
2029 apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id),
2031 apic_printk(APIC_VERBOSE, "Setting %d in the "
2032 "phys_id_present_map\n",
2033 mpc_ioapic_id(apic_id));
2034 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2038 * We need to adjust the IRQ routing table
2039 * if the ID changed.
2041 if (old_id != mpc_ioapic_id(apic_id))
2042 for (i = 0; i < mp_irq_entries; i++)
2043 if (mp_irqs[i].dstapic == old_id)
2045 = mpc_ioapic_id(apic_id);
2048 * Update the ID register according to the right value
2049 * from the MPC table if they are different.
2051 if (mpc_ioapic_id(apic_id) == reg_00.bits.ID)
2054 apic_printk(APIC_VERBOSE, KERN_INFO
2055 "...changing IO-APIC physical APIC ID to %d ...",
2056 mpc_ioapic_id(apic_id));
2058 reg_00.bits.ID = mpc_ioapic_id(apic_id);
2059 raw_spin_lock_irqsave(&ioapic_lock, flags);
2060 io_apic_write(apic_id, 0, reg_00.raw);
2061 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2066 raw_spin_lock_irqsave(&ioapic_lock, flags);
2067 reg_00.raw = io_apic_read(apic_id, 0);
2068 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2069 if (reg_00.bits.ID != mpc_ioapic_id(apic_id))
2070 printk("could not set ID!\n");
2072 apic_printk(APIC_VERBOSE, " ok.\n");
2076 void __init setup_ioapic_ids_from_mpc(void)
2082 * Don't check I/O APIC IDs for xAPIC systems. They have
2083 * no meaning without the serial APIC bus.
2085 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2086 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2088 setup_ioapic_ids_from_mpc_nocheck();
2092 int no_timer_check __initdata;
2094 static int __init notimercheck(char *s)
2099 __setup("no_timer_check", notimercheck);
2102 * There is a nasty bug in some older SMP boards, their mptable lies
2103 * about the timer IRQ. We do the following to work around the situation:
2105 * - timer IRQ defaults to IO-APIC IRQ
2106 * - if this function detects that timer IRQs are defunct, then we fall
2107 * back to ISA timer IRQs
2109 static int __init timer_irq_works(void)
2111 unsigned long t1 = jiffies;
2112 unsigned long flags;
2117 local_save_flags(flags);
2119 /* Let ten ticks pass... */
2120 mdelay((10 * 1000) / HZ);
2121 local_irq_restore(flags);
2124 * Expect a few ticks at least, to be sure some possible
2125 * glue logic does not lock up after one or two first
2126 * ticks in a non-ExtINT mode. Also the local APIC
2127 * might have cached one ExtINT interrupt. Finally, at
2128 * least one tick may be lost due to delays.
2132 if (time_after(jiffies, t1 + 4))
2138 * In the SMP+IOAPIC case it might happen that there are an unspecified
2139 * number of pending IRQ events unhandled. These cases are very rare,
2140 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2141 * better to do it this way as thus we do not have to be aware of
2142 * 'pending' interrupts in the IRQ path, except at this point.
2145 * Edge triggered needs to resend any interrupt
2146 * that was delayed but this is now handled in the device
2151 * Starting up a edge-triggered IO-APIC interrupt is
2152 * nasty - we need to make sure that we get the edge.
2153 * If it is already asserted for some reason, we need
2154 * return 1 to indicate that is was pending.
2156 * This is not complete - we should be able to fake
2157 * an edge even if it isn't on the 8259A...
2160 static unsigned int startup_ioapic_irq(struct irq_data *data)
2162 int was_pending = 0, irq = data->irq;
2163 unsigned long flags;
2165 raw_spin_lock_irqsave(&ioapic_lock, flags);
2166 if (irq < legacy_pic->nr_legacy_irqs) {
2167 legacy_pic->mask(irq);
2168 if (legacy_pic->irq_pending(irq))
2171 __unmask_ioapic(data->chip_data);
2172 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2177 static int ioapic_retrigger_irq(struct irq_data *data)
2179 struct irq_cfg *cfg = data->chip_data;
2180 unsigned long flags;
2182 raw_spin_lock_irqsave(&vector_lock, flags);
2183 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2184 raw_spin_unlock_irqrestore(&vector_lock, flags);
2190 * Level and edge triggered IO-APIC interrupts need different handling,
2191 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2192 * handled with the level-triggered descriptor, but that one has slightly
2193 * more overhead. Level-triggered interrupts cannot be handled with the
2194 * edge-triggered handler, without risking IRQ storms and other ugly
2199 void send_cleanup_vector(struct irq_cfg *cfg)
2201 cpumask_var_t cleanup_mask;
2203 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2205 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2206 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2208 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2209 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2210 free_cpumask_var(cleanup_mask);
2212 cfg->move_in_progress = 0;
2215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2218 struct irq_pin_list *entry;
2219 u8 vector = cfg->vector;
2221 for_each_irq_pin(entry, cfg->irq_2_pin) {
2227 * With interrupt-remapping, destination information comes
2228 * from interrupt-remapping table entry.
2230 if (!irq_remapped(cfg))
2231 io_apic_write(apic, 0x11 + pin*2, dest);
2232 reg = io_apic_read(apic, 0x10 + pin*2);
2233 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2235 io_apic_modify(apic, 0x10 + pin*2, reg);
2240 * Either sets data->affinity to a valid value, and returns
2241 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2242 * leaves data->affinity untouched.
2244 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2245 unsigned int *dest_id)
2247 struct irq_cfg *cfg = data->chip_data;
2249 if (!cpumask_intersects(mask, cpu_online_mask))
2252 if (assign_irq_vector(data->irq, data->chip_data, mask))
2255 cpumask_copy(data->affinity, mask);
2257 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2262 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2265 unsigned int dest, irq = data->irq;
2266 unsigned long flags;
2269 raw_spin_lock_irqsave(&ioapic_lock, flags);
2270 ret = __ioapic_set_affinity(data, mask, &dest);
2272 /* Only the high 8 bits are valid. */
2273 dest = SET_APIC_LOGICAL_ID(dest);
2274 __target_IO_APIC_irq(irq, dest, data->chip_data);
2276 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2280 #ifdef CONFIG_INTR_REMAP
2283 * Migrate the IO-APIC irq in the presence of intr-remapping.
2285 * For both level and edge triggered, irq migration is a simple atomic
2286 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2288 * For level triggered, we eliminate the io-apic RTE modification (with the
2289 * updated vector information), by using a virtual vector (io-apic pin number).
2290 * Real vector that is used for interrupting cpu will be coming from
2291 * the interrupt-remapping table entry.
2294 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2297 struct irq_cfg *cfg = data->chip_data;
2298 unsigned int dest, irq = data->irq;
2301 if (!cpumask_intersects(mask, cpu_online_mask))
2304 if (get_irte(irq, &irte))
2307 if (assign_irq_vector(irq, cfg, mask))
2310 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2312 irte.vector = cfg->vector;
2313 irte.dest_id = IRTE_DEST(dest);
2316 * Modified the IRTE and flushes the Interrupt entry cache.
2318 modify_irte(irq, &irte);
2320 if (cfg->move_in_progress)
2321 send_cleanup_vector(cfg);
2323 cpumask_copy(data->affinity, mask);
2329 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2336 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2338 unsigned vector, me;
2344 me = smp_processor_id();
2345 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2348 struct irq_desc *desc;
2349 struct irq_cfg *cfg;
2350 irq = __this_cpu_read(vector_irq[vector]);
2355 desc = irq_to_desc(irq);
2360 raw_spin_lock(&desc->lock);
2363 * Check if the irq migration is in progress. If so, we
2364 * haven't received the cleanup request yet for this irq.
2366 if (cfg->move_in_progress)
2369 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2372 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2374 * Check if the vector that needs to be cleanedup is
2375 * registered at the cpu's IRR. If so, then this is not
2376 * the best time to clean it up. Lets clean it up in the
2377 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2380 if (irr & (1 << (vector % 32))) {
2381 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2384 __this_cpu_write(vector_irq[vector], -1);
2386 raw_spin_unlock(&desc->lock);
2392 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2396 if (likely(!cfg->move_in_progress))
2399 me = smp_processor_id();
2401 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2402 send_cleanup_vector(cfg);
2405 static void irq_complete_move(struct irq_cfg *cfg)
2407 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2410 void irq_force_complete_move(int irq)
2412 struct irq_cfg *cfg = irq_get_chip_data(irq);
2417 __irq_complete_move(cfg, cfg->vector);
2420 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2423 static void ack_apic_edge(struct irq_data *data)
2425 irq_complete_move(data->chip_data);
2430 atomic_t irq_mis_count;
2433 * IO-APIC versions below 0x20 don't support EOI register.
2434 * For the record, here is the information about various versions:
2436 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2437 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2440 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2441 * version as 0x2. This is an error with documentation and these ICH chips
2442 * use io-apic's of version 0x20.
2444 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2445 * Otherwise, we simulate the EOI message manually by changing the trigger
2446 * mode to edge and then back to level, with RTE being masked during this.
2448 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2450 struct irq_pin_list *entry;
2451 unsigned long flags;
2453 raw_spin_lock_irqsave(&ioapic_lock, flags);
2454 for_each_irq_pin(entry, cfg->irq_2_pin) {
2455 if (mpc_ioapic_ver(entry->apic) >= 0x20) {
2457 * Intr-remapping uses pin number as the virtual vector
2458 * in the RTE. Actual vector is programmed in
2459 * intr-remapping table entry. Hence for the io-apic
2460 * EOI we use the pin number.
2462 if (irq_remapped(cfg))
2463 io_apic_eoi(entry->apic, entry->pin);
2465 io_apic_eoi(entry->apic, cfg->vector);
2467 __mask_and_edge_IO_APIC_irq(entry);
2468 __unmask_and_level_IO_APIC_irq(entry);
2471 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2474 static void ack_apic_level(struct irq_data *data)
2476 struct irq_cfg *cfg = data->chip_data;
2477 int i, do_unmask_irq = 0, irq = data->irq;
2480 irq_complete_move(cfg);
2481 #ifdef CONFIG_GENERIC_PENDING_IRQ
2482 /* If we are moving the irq we need to mask it */
2483 if (unlikely(irqd_is_setaffinity_pending(data))) {
2490 * It appears there is an erratum which affects at least version 0x11
2491 * of I/O APIC (that's the 82093AA and cores integrated into various
2492 * chipsets). Under certain conditions a level-triggered interrupt is
2493 * erroneously delivered as edge-triggered one but the respective IRR
2494 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2495 * message but it will never arrive and further interrupts are blocked
2496 * from the source. The exact reason is so far unknown, but the
2497 * phenomenon was observed when two consecutive interrupt requests
2498 * from a given source get delivered to the same CPU and the source is
2499 * temporarily disabled in between.
2501 * A workaround is to simulate an EOI message manually. We achieve it
2502 * by setting the trigger mode to edge and then to level when the edge
2503 * trigger mode gets detected in the TMR of a local APIC for a
2504 * level-triggered interrupt. We mask the source for the time of the
2505 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2506 * The idea is from Manfred Spraul. --macro
2508 * Also in the case when cpu goes offline, fixup_irqs() will forward
2509 * any unhandled interrupt on the offlined cpu to the new cpu
2510 * destination that is handling the corresponding interrupt. This
2511 * interrupt forwarding is done via IPI's. Hence, in this case also
2512 * level-triggered io-apic interrupt will be seen as an edge
2513 * interrupt in the IRR. And we can't rely on the cpu's EOI
2514 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2515 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2516 * supporting EOI register, we do an explicit EOI to clear the
2517 * remote IRR and on IO-APIC's which don't have an EOI register,
2518 * we use the above logic (mask+edge followed by unmask+level) from
2519 * Manfred Spraul to clear the remote IRR.
2522 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2525 * We must acknowledge the irq before we move it or the acknowledge will
2526 * not propagate properly.
2531 * Tail end of clearing remote IRR bit (either by delivering the EOI
2532 * message via io-apic EOI register write or simulating it using
2533 * mask+edge followed by unnask+level logic) manually when the
2534 * level triggered interrupt is seen as the edge triggered interrupt
2537 if (!(v & (1 << (i & 0x1f)))) {
2538 atomic_inc(&irq_mis_count);
2540 eoi_ioapic_irq(irq, cfg);
2543 /* Now we can move and renable the irq */
2544 if (unlikely(do_unmask_irq)) {
2545 /* Only migrate the irq if the ack has been received.
2547 * On rare occasions the broadcast level triggered ack gets
2548 * delayed going to ioapics, and if we reprogram the
2549 * vector while Remote IRR is still set the irq will never
2552 * To prevent this scenario we read the Remote IRR bit
2553 * of the ioapic. This has two effects.
2554 * - On any sane system the read of the ioapic will
2555 * flush writes (and acks) going to the ioapic from
2557 * - We get to see if the ACK has actually been delivered.
2559 * Based on failed experiments of reprogramming the
2560 * ioapic entry from outside of irq context starting
2561 * with masking the ioapic entry and then polling until
2562 * Remote IRR was clear before reprogramming the
2563 * ioapic I don't trust the Remote IRR bit to be
2564 * completey accurate.
2566 * However there appears to be no other way to plug
2567 * this race, so if the Remote IRR bit is not
2568 * accurate and is causing problems then it is a hardware bug
2569 * and you can go talk to the chipset vendor about it.
2571 if (!io_apic_level_ack_pending(cfg))
2572 irq_move_masked_irq(data);
2577 #ifdef CONFIG_INTR_REMAP
2578 static void ir_ack_apic_edge(struct irq_data *data)
2583 static void ir_ack_apic_level(struct irq_data *data)
2586 eoi_ioapic_irq(data->irq, data->chip_data);
2588 #endif /* CONFIG_INTR_REMAP */
2590 static struct irq_chip ioapic_chip __read_mostly = {
2592 .irq_startup = startup_ioapic_irq,
2593 .irq_mask = mask_ioapic_irq,
2594 .irq_unmask = unmask_ioapic_irq,
2595 .irq_ack = ack_apic_edge,
2596 .irq_eoi = ack_apic_level,
2598 .irq_set_affinity = ioapic_set_affinity,
2600 .irq_retrigger = ioapic_retrigger_irq,
2603 static struct irq_chip ir_ioapic_chip __read_mostly = {
2604 .name = "IR-IO-APIC",
2605 .irq_startup = startup_ioapic_irq,
2606 .irq_mask = mask_ioapic_irq,
2607 .irq_unmask = unmask_ioapic_irq,
2608 #ifdef CONFIG_INTR_REMAP
2609 .irq_ack = ir_ack_apic_edge,
2610 .irq_eoi = ir_ack_apic_level,
2612 .irq_set_affinity = ir_ioapic_set_affinity,
2615 .irq_retrigger = ioapic_retrigger_irq,
2618 static inline void init_IO_APIC_traps(void)
2620 struct irq_cfg *cfg;
2624 * NOTE! The local APIC isn't very good at handling
2625 * multiple interrupts at the same interrupt level.
2626 * As the interrupt level is determined by taking the
2627 * vector number and shifting that right by 4, we
2628 * want to spread these out a bit so that they don't
2629 * all fall in the same interrupt level.
2631 * Also, we've got to be careful not to trash gate
2632 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2634 for_each_active_irq(irq) {
2635 cfg = irq_get_chip_data(irq);
2636 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2638 * Hmm.. We don't have an entry for this,
2639 * so default to an old-fashioned 8259
2640 * interrupt if we can..
2642 if (irq < legacy_pic->nr_legacy_irqs)
2643 legacy_pic->make_irq(irq);
2645 /* Strange. Oh, well.. */
2646 irq_set_chip(irq, &no_irq_chip);
2652 * The local APIC irq-chip implementation:
2655 static void mask_lapic_irq(struct irq_data *data)
2659 v = apic_read(APIC_LVT0);
2660 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2663 static void unmask_lapic_irq(struct irq_data *data)
2667 v = apic_read(APIC_LVT0);
2668 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2671 static void ack_lapic_irq(struct irq_data *data)
2676 static struct irq_chip lapic_chip __read_mostly = {
2677 .name = "local-APIC",
2678 .irq_mask = mask_lapic_irq,
2679 .irq_unmask = unmask_lapic_irq,
2680 .irq_ack = ack_lapic_irq,
2683 static void lapic_register_intr(int irq)
2685 irq_clear_status_flags(irq, IRQ_LEVEL);
2686 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2691 * This looks a bit hackish but it's about the only one way of sending
2692 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2693 * not support the ExtINT mode, unfortunately. We need to send these
2694 * cycles as some i82489DX-based boards have glue logic that keeps the
2695 * 8259A interrupt line asserted until INTA. --macro
2697 static inline void __init unlock_ExtINT_logic(void)
2700 struct IO_APIC_route_entry entry0, entry1;
2701 unsigned char save_control, save_freq_select;
2703 pin = find_isa_irq_pin(8, mp_INT);
2708 apic = find_isa_irq_apic(8, mp_INT);
2714 entry0 = ioapic_read_entry(apic, pin);
2715 clear_IO_APIC_pin(apic, pin);
2717 memset(&entry1, 0, sizeof(entry1));
2719 entry1.dest_mode = 0; /* physical delivery */
2720 entry1.mask = 0; /* unmask IRQ now */
2721 entry1.dest = hard_smp_processor_id();
2722 entry1.delivery_mode = dest_ExtINT;
2723 entry1.polarity = entry0.polarity;
2727 ioapic_write_entry(apic, pin, entry1);
2729 save_control = CMOS_READ(RTC_CONTROL);
2730 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2731 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2733 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2738 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2742 CMOS_WRITE(save_control, RTC_CONTROL);
2743 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2744 clear_IO_APIC_pin(apic, pin);
2746 ioapic_write_entry(apic, pin, entry0);
2749 static int disable_timer_pin_1 __initdata;
2750 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2751 static int __init disable_timer_pin_setup(char *arg)
2753 disable_timer_pin_1 = 1;
2756 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2758 int timer_through_8259 __initdata;
2761 * This code may look a bit paranoid, but it's supposed to cooperate with
2762 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2763 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2764 * fanatically on his truly buggy board.
2766 * FIXME: really need to revamp this for all platforms.
2768 static inline void __init check_timer(void)
2770 struct irq_cfg *cfg = irq_get_chip_data(0);
2771 int node = cpu_to_node(0);
2772 int apic1, pin1, apic2, pin2;
2773 unsigned long flags;
2776 local_irq_save(flags);
2779 * get/set the timer IRQ vector:
2781 legacy_pic->mask(0);
2782 assign_irq_vector(0, cfg, apic->target_cpus());
2785 * As IRQ0 is to be enabled in the 8259A, the virtual
2786 * wire has to be disabled in the local APIC. Also
2787 * timer interrupts need to be acknowledged manually in
2788 * the 8259A for the i82489DX when using the NMI
2789 * watchdog as that APIC treats NMIs as level-triggered.
2790 * The AEOI mode will finish them in the 8259A
2793 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2794 legacy_pic->init(1);
2796 pin1 = find_isa_irq_pin(0, mp_INT);
2797 apic1 = find_isa_irq_apic(0, mp_INT);
2798 pin2 = ioapic_i8259.pin;
2799 apic2 = ioapic_i8259.apic;
2801 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2802 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2803 cfg->vector, apic1, pin1, apic2, pin2);
2806 * Some BIOS writers are clueless and report the ExtINTA
2807 * I/O APIC input from the cascaded 8259A as the timer
2808 * interrupt input. So just in case, if only one pin
2809 * was found above, try it both directly and through the
2813 if (intr_remapping_enabled)
2814 panic("BIOS bug: timer not connected to IO-APIC");
2818 } else if (pin2 == -1) {
2825 * Ok, does IRQ0 through the IOAPIC work?
2828 add_pin_to_irq_node(cfg, node, apic1, pin1);
2829 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2831 /* for edge trigger, setup_ioapic_irq already
2832 * leave it unmasked.
2833 * so only need to unmask if it is level-trigger
2834 * do we really have level trigger timer?
2837 idx = find_irq_entry(apic1, pin1, mp_INT);
2838 if (idx != -1 && irq_trigger(idx))
2841 if (timer_irq_works()) {
2842 if (disable_timer_pin_1 > 0)
2843 clear_IO_APIC_pin(0, pin1);
2846 if (intr_remapping_enabled)
2847 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2848 local_irq_disable();
2849 clear_IO_APIC_pin(apic1, pin1);
2851 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2852 "8254 timer not connected to IO-APIC\n");
2854 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2855 "(IRQ0) through the 8259A ...\n");
2856 apic_printk(APIC_QUIET, KERN_INFO
2857 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2859 * legacy devices should be connected to IO APIC #0
2861 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2862 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2863 legacy_pic->unmask(0);
2864 if (timer_irq_works()) {
2865 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2866 timer_through_8259 = 1;
2870 * Cleanup, just in case ...
2872 local_irq_disable();
2873 legacy_pic->mask(0);
2874 clear_IO_APIC_pin(apic2, pin2);
2875 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2878 apic_printk(APIC_QUIET, KERN_INFO
2879 "...trying to set up timer as Virtual Wire IRQ...\n");
2881 lapic_register_intr(0);
2882 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2883 legacy_pic->unmask(0);
2885 if (timer_irq_works()) {
2886 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2889 local_irq_disable();
2890 legacy_pic->mask(0);
2891 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2892 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2894 apic_printk(APIC_QUIET, KERN_INFO
2895 "...trying to set up timer as ExtINT IRQ...\n");
2897 legacy_pic->init(0);
2898 legacy_pic->make_irq(0);
2899 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2901 unlock_ExtINT_logic();
2903 if (timer_irq_works()) {
2904 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2907 local_irq_disable();
2908 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2909 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2910 "report. Then try booting with the 'noapic' option.\n");
2912 local_irq_restore(flags);
2916 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2917 * to devices. However there may be an I/O APIC pin available for
2918 * this interrupt regardless. The pin may be left unconnected, but
2919 * typically it will be reused as an ExtINT cascade interrupt for
2920 * the master 8259A. In the MPS case such a pin will normally be
2921 * reported as an ExtINT interrupt in the MP table. With ACPI
2922 * there is no provision for ExtINT interrupts, and in the absence
2923 * of an override it would be treated as an ordinary ISA I/O APIC
2924 * interrupt, that is edge-triggered and unmasked by default. We
2925 * used to do this, but it caused problems on some systems because
2926 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2927 * the same ExtINT cascade interrupt to drive the local APIC of the
2928 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2929 * the I/O APIC in all cases now. No actual device should request
2930 * it anyway. --macro
2932 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2934 void __init setup_IO_APIC(void)
2938 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2940 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2942 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2944 * Set up IO-APIC IRQ routing.
2946 x86_init.mpparse.setup_ioapic_ids();
2949 setup_IO_APIC_irqs();
2950 init_IO_APIC_traps();
2951 if (legacy_pic->nr_legacy_irqs)
2956 * Called after all the initialization is done. If we didn't find any
2957 * APIC bugs then we can allow the modify fast path
2960 static int __init io_apic_bug_finalize(void)
2962 if (sis_apic_bug == -1)
2967 late_initcall(io_apic_bug_finalize);
2969 static void resume_ioapic_id(int ioapic_id)
2971 unsigned long flags;
2972 union IO_APIC_reg_00 reg_00;
2975 raw_spin_lock_irqsave(&ioapic_lock, flags);
2976 reg_00.raw = io_apic_read(ioapic_id, 0);
2977 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) {
2978 reg_00.bits.ID = mpc_ioapic_id(ioapic_id);
2979 io_apic_write(ioapic_id, 0, reg_00.raw);
2981 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2984 static void ioapic_resume(void)
2988 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2989 resume_ioapic_id(ioapic_id);
2991 restore_ioapic_entries();
2994 static struct syscore_ops ioapic_syscore_ops = {
2995 .suspend = save_ioapic_entries,
2996 .resume = ioapic_resume,
2999 static int __init ioapic_init_ops(void)
3001 register_syscore_ops(&ioapic_syscore_ops);
3006 device_initcall(ioapic_init_ops);
3009 * Dynamic irq allocate and deallocation
3011 unsigned int create_irq_nr(unsigned int from, int node)
3013 struct irq_cfg *cfg;
3014 unsigned long flags;
3015 unsigned int ret = 0;
3018 if (from < nr_irqs_gsi)
3021 irq = alloc_irq_from(from, node);
3024 cfg = alloc_irq_cfg(irq, node);
3026 free_irq_at(irq, NULL);
3030 raw_spin_lock_irqsave(&vector_lock, flags);
3031 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3033 raw_spin_unlock_irqrestore(&vector_lock, flags);
3036 irq_set_chip_data(irq, cfg);
3037 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3039 free_irq_at(irq, cfg);
3044 int create_irq(void)
3046 int node = cpu_to_node(0);
3047 unsigned int irq_want;
3050 irq_want = nr_irqs_gsi;
3051 irq = create_irq_nr(irq_want, node);
3059 void destroy_irq(unsigned int irq)
3061 struct irq_cfg *cfg = irq_get_chip_data(irq);
3062 unsigned long flags;
3064 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3066 if (irq_remapped(cfg))
3068 raw_spin_lock_irqsave(&vector_lock, flags);
3069 __clear_irq_vector(irq, cfg);
3070 raw_spin_unlock_irqrestore(&vector_lock, flags);
3071 free_irq_at(irq, cfg);
3075 * MSI message composition
3077 #ifdef CONFIG_PCI_MSI
3078 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3079 struct msi_msg *msg, u8 hpet_id)
3081 struct irq_cfg *cfg;
3089 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3093 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3095 if (irq_remapped(cfg)) {
3100 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3101 BUG_ON(ir_index == -1);
3103 prepare_irte(&irte, cfg->vector, dest);
3105 /* Set source-id of interrupt request */
3107 set_msi_sid(&irte, pdev);
3109 set_hpet_sid(&irte, hpet_id);
3111 modify_irte(irq, &irte);
3113 msg->address_hi = MSI_ADDR_BASE_HI;
3114 msg->data = sub_handle;
3115 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3117 MSI_ADDR_IR_INDEX1(ir_index) |
3118 MSI_ADDR_IR_INDEX2(ir_index);
3120 if (x2apic_enabled())
3121 msg->address_hi = MSI_ADDR_BASE_HI |
3122 MSI_ADDR_EXT_DEST_ID(dest);
3124 msg->address_hi = MSI_ADDR_BASE_HI;
3128 ((apic->irq_dest_mode == 0) ?
3129 MSI_ADDR_DEST_MODE_PHYSICAL:
3130 MSI_ADDR_DEST_MODE_LOGICAL) |
3131 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3132 MSI_ADDR_REDIRECTION_CPU:
3133 MSI_ADDR_REDIRECTION_LOWPRI) |
3134 MSI_ADDR_DEST_ID(dest);
3137 MSI_DATA_TRIGGER_EDGE |
3138 MSI_DATA_LEVEL_ASSERT |
3139 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3140 MSI_DATA_DELIVERY_FIXED:
3141 MSI_DATA_DELIVERY_LOWPRI) |
3142 MSI_DATA_VECTOR(cfg->vector);
3149 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3151 struct irq_cfg *cfg = data->chip_data;
3155 if (__ioapic_set_affinity(data, mask, &dest))
3158 __get_cached_msi_msg(data->msi_desc, &msg);
3160 msg.data &= ~MSI_DATA_VECTOR_MASK;
3161 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3162 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3163 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3165 __write_msi_msg(data->msi_desc, &msg);
3169 #ifdef CONFIG_INTR_REMAP
3171 * Migrate the MSI irq to another cpumask. This migration is
3172 * done in the process context using interrupt-remapping hardware.
3175 ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3178 struct irq_cfg *cfg = data->chip_data;
3179 unsigned int dest, irq = data->irq;
3182 if (get_irte(irq, &irte))
3185 if (__ioapic_set_affinity(data, mask, &dest))
3188 irte.vector = cfg->vector;
3189 irte.dest_id = IRTE_DEST(dest);
3192 * atomically update the IRTE with the new destination and vector.
3194 modify_irte(irq, &irte);
3197 * After this point, all the interrupts will start arriving
3198 * at the new destination. So, time to cleanup the previous
3199 * vector allocation.
3201 if (cfg->move_in_progress)
3202 send_cleanup_vector(cfg);
3208 #endif /* CONFIG_SMP */
3211 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3212 * which implement the MSI or MSI-X Capability Structure.
3214 static struct irq_chip msi_chip = {
3216 .irq_unmask = unmask_msi_irq,
3217 .irq_mask = mask_msi_irq,
3218 .irq_ack = ack_apic_edge,
3220 .irq_set_affinity = msi_set_affinity,
3222 .irq_retrigger = ioapic_retrigger_irq,
3225 static struct irq_chip msi_ir_chip = {
3226 .name = "IR-PCI-MSI",
3227 .irq_unmask = unmask_msi_irq,
3228 .irq_mask = mask_msi_irq,
3229 #ifdef CONFIG_INTR_REMAP
3230 .irq_ack = ir_ack_apic_edge,
3232 .irq_set_affinity = ir_msi_set_affinity,
3235 .irq_retrigger = ioapic_retrigger_irq,
3239 * Map the PCI dev to the corresponding remapping hardware unit
3240 * and allocate 'nvec' consecutive interrupt-remapping table entries
3243 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3245 struct intel_iommu *iommu;
3248 iommu = map_dev_to_ir(dev);
3251 "Unable to map PCI %s to iommu\n", pci_name(dev));
3255 index = alloc_irte(iommu, irq, nvec);
3258 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3265 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3267 struct irq_chip *chip = &msi_chip;
3271 ret = msi_compose_msg(dev, irq, &msg, -1);
3275 irq_set_msi_desc(irq, msidesc);
3276 write_msi_msg(irq, &msg);
3278 if (irq_remapped(irq_get_chip_data(irq))) {
3279 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3280 chip = &msi_ir_chip;
3283 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3285 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3290 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3292 int node, ret, sub_handle, index = 0;
3293 unsigned int irq, irq_want;
3294 struct msi_desc *msidesc;
3295 struct intel_iommu *iommu = NULL;
3297 /* x86 doesn't support multiple MSI yet */
3298 if (type == PCI_CAP_ID_MSI && nvec > 1)
3301 node = dev_to_node(&dev->dev);
3302 irq_want = nr_irqs_gsi;
3304 list_for_each_entry(msidesc, &dev->msi_list, list) {
3305 irq = create_irq_nr(irq_want, node);
3309 if (!intr_remapping_enabled)
3314 * allocate the consecutive block of IRTE's
3317 index = msi_alloc_irte(dev, irq, nvec);
3323 iommu = map_dev_to_ir(dev);
3329 * setup the mapping between the irq and the IRTE
3330 * base index, the sub_handle pointing to the
3331 * appropriate interrupt remap table entry.
3333 set_irte_irq(irq, iommu, index, sub_handle);
3336 ret = setup_msi_irq(dev, msidesc, irq);
3348 void native_teardown_msi_irq(unsigned int irq)
3353 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3356 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3359 struct irq_cfg *cfg = data->chip_data;
3360 unsigned int dest, irq = data->irq;
3363 if (__ioapic_set_affinity(data, mask, &dest))
3366 dmar_msi_read(irq, &msg);
3368 msg.data &= ~MSI_DATA_VECTOR_MASK;
3369 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3370 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3371 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3372 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3374 dmar_msi_write(irq, &msg);
3379 #endif /* CONFIG_SMP */
3381 static struct irq_chip dmar_msi_type = {
3383 .irq_unmask = dmar_msi_unmask,
3384 .irq_mask = dmar_msi_mask,
3385 .irq_ack = ack_apic_edge,
3387 .irq_set_affinity = dmar_msi_set_affinity,
3389 .irq_retrigger = ioapic_retrigger_irq,
3392 int arch_setup_dmar_msi(unsigned int irq)
3397 ret = msi_compose_msg(NULL, irq, &msg, -1);
3400 dmar_msi_write(irq, &msg);
3401 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3407 #ifdef CONFIG_HPET_TIMER
3410 static int hpet_msi_set_affinity(struct irq_data *data,
3411 const struct cpumask *mask, bool force)
3413 struct irq_cfg *cfg = data->chip_data;
3417 if (__ioapic_set_affinity(data, mask, &dest))
3420 hpet_msi_read(data->handler_data, &msg);
3422 msg.data &= ~MSI_DATA_VECTOR_MASK;
3423 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3424 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3425 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3427 hpet_msi_write(data->handler_data, &msg);
3432 #endif /* CONFIG_SMP */
3434 static struct irq_chip ir_hpet_msi_type = {
3435 .name = "IR-HPET_MSI",
3436 .irq_unmask = hpet_msi_unmask,
3437 .irq_mask = hpet_msi_mask,
3438 #ifdef CONFIG_INTR_REMAP
3439 .irq_ack = ir_ack_apic_edge,
3441 .irq_set_affinity = ir_msi_set_affinity,
3444 .irq_retrigger = ioapic_retrigger_irq,
3447 static struct irq_chip hpet_msi_type = {
3449 .irq_unmask = hpet_msi_unmask,
3450 .irq_mask = hpet_msi_mask,
3451 .irq_ack = ack_apic_edge,
3453 .irq_set_affinity = hpet_msi_set_affinity,
3455 .irq_retrigger = ioapic_retrigger_irq,
3458 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3460 struct irq_chip *chip = &hpet_msi_type;
3464 if (intr_remapping_enabled) {
3465 struct intel_iommu *iommu = map_hpet_to_ir(id);
3471 index = alloc_irte(iommu, irq, 1);
3476 ret = msi_compose_msg(NULL, irq, &msg, id);
3480 hpet_msi_write(irq_get_handler_data(irq), &msg);
3481 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3482 if (irq_remapped(irq_get_chip_data(irq)))
3483 chip = &ir_hpet_msi_type;
3485 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3490 #endif /* CONFIG_PCI_MSI */
3492 * Hypertransport interrupt support
3494 #ifdef CONFIG_HT_IRQ
3498 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3500 struct ht_irq_msg msg;
3501 fetch_ht_irq_msg(irq, &msg);
3503 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3504 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3506 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3507 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3509 write_ht_irq_msg(irq, &msg);
3513 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3515 struct irq_cfg *cfg = data->chip_data;
3518 if (__ioapic_set_affinity(data, mask, &dest))
3521 target_ht_irq(data->irq, dest, cfg->vector);
3527 static struct irq_chip ht_irq_chip = {
3529 .irq_mask = mask_ht_irq,
3530 .irq_unmask = unmask_ht_irq,
3531 .irq_ack = ack_apic_edge,
3533 .irq_set_affinity = ht_set_affinity,
3535 .irq_retrigger = ioapic_retrigger_irq,
3538 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3540 struct irq_cfg *cfg;
3547 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3549 struct ht_irq_msg msg;
3552 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3553 apic->target_cpus());
3555 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3559 HT_IRQ_LOW_DEST_ID(dest) |
3560 HT_IRQ_LOW_VECTOR(cfg->vector) |
3561 ((apic->irq_dest_mode == 0) ?
3562 HT_IRQ_LOW_DM_PHYSICAL :
3563 HT_IRQ_LOW_DM_LOGICAL) |
3564 HT_IRQ_LOW_RQEOI_EDGE |
3565 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3566 HT_IRQ_LOW_MT_FIXED :
3567 HT_IRQ_LOW_MT_ARBITRATED) |
3568 HT_IRQ_LOW_IRQ_MASKED;
3570 write_ht_irq_msg(irq, &msg);
3572 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3573 handle_edge_irq, "edge");
3575 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3579 #endif /* CONFIG_HT_IRQ */
3582 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3584 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3589 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3591 setup_ioapic_irq(irq, cfg, attr);
3595 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3596 struct io_apic_irq_attr *attr)
3598 unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3601 /* Avoid redundant programming */
3602 if (test_bit(pin, ioapics[id].pin_programmed)) {
3603 pr_debug("Pin %d-%d already programmed\n",
3604 mpc_ioapic_id(id), pin);
3607 ret = io_apic_setup_irq_pin(irq, node, attr);
3609 set_bit(pin, ioapics[id].pin_programmed);
3613 static int __init io_apic_get_redir_entries(int ioapic)
3615 union IO_APIC_reg_01 reg_01;
3616 unsigned long flags;
3618 raw_spin_lock_irqsave(&ioapic_lock, flags);
3619 reg_01.raw = io_apic_read(ioapic, 1);
3620 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3622 /* The register returns the maximum index redir index
3623 * supported, which is one less than the total number of redir
3626 return reg_01.bits.entries + 1;
3629 static void __init probe_nr_irqs_gsi(void)
3633 nr = gsi_top + NR_IRQS_LEGACY;
3634 if (nr > nr_irqs_gsi)
3637 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3640 int get_nr_irqs_gsi(void)
3645 #ifdef CONFIG_SPARSE_IRQ
3646 int __init arch_probe_nr_irqs(void)
3650 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3651 nr_irqs = NR_VECTORS * nr_cpu_ids;
3653 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3654 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3656 * for MSI and HT dyn irq
3658 nr += nr_irqs_gsi * 16;
3663 return NR_IRQS_LEGACY;
3667 int io_apic_set_pci_routing(struct device *dev, int irq,
3668 struct io_apic_irq_attr *irq_attr)
3672 if (!IO_APIC_IRQ(irq)) {
3673 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3678 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3680 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3683 #ifdef CONFIG_X86_32
3684 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3686 union IO_APIC_reg_00 reg_00;
3687 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3689 unsigned long flags;
3693 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3694 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3695 * supports up to 16 on one shared APIC bus.
3697 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3698 * advantage of new APIC bus architecture.
3701 if (physids_empty(apic_id_map))
3702 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3704 raw_spin_lock_irqsave(&ioapic_lock, flags);
3705 reg_00.raw = io_apic_read(ioapic, 0);
3706 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3708 if (apic_id >= get_physical_broadcast()) {
3709 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3710 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3711 apic_id = reg_00.bits.ID;
3715 * Every APIC in a system must have a unique ID or we get lots of nice
3716 * 'stuck on smp_invalidate_needed IPI wait' messages.
3718 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3720 for (i = 0; i < get_physical_broadcast(); i++) {
3721 if (!apic->check_apicid_used(&apic_id_map, i))
3725 if (i == get_physical_broadcast())
3726 panic("Max apic_id exceeded!\n");
3728 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3729 "trying %d\n", ioapic, apic_id, i);
3734 apic->apicid_to_cpu_present(apic_id, &tmp);
3735 physids_or(apic_id_map, apic_id_map, tmp);
3737 if (reg_00.bits.ID != apic_id) {
3738 reg_00.bits.ID = apic_id;
3740 raw_spin_lock_irqsave(&ioapic_lock, flags);
3741 io_apic_write(ioapic, 0, reg_00.raw);
3742 reg_00.raw = io_apic_read(ioapic, 0);
3743 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3746 if (reg_00.bits.ID != apic_id) {
3747 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3752 apic_printk(APIC_VERBOSE, KERN_INFO
3753 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3758 static u8 __init io_apic_unique_id(u8 id)
3760 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3761 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3762 return io_apic_get_unique_id(nr_ioapics, id);
3767 static u8 __init io_apic_unique_id(u8 id)
3770 DECLARE_BITMAP(used, 256);
3772 bitmap_zero(used, 256);
3773 for (i = 0; i < nr_ioapics; i++) {
3774 __set_bit(mpc_ioapic_id(i), used);
3776 if (!test_bit(id, used))
3778 return find_first_zero_bit(used, 256);
3782 static int __init io_apic_get_version(int ioapic)
3784 union IO_APIC_reg_01 reg_01;
3785 unsigned long flags;
3787 raw_spin_lock_irqsave(&ioapic_lock, flags);
3788 reg_01.raw = io_apic_read(ioapic, 1);
3789 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3791 return reg_01.bits.version;
3794 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3796 int ioapic, pin, idx;
3798 if (skip_ioapic_setup)
3801 ioapic = mp_find_ioapic(gsi);
3805 pin = mp_find_ioapic_pin(ioapic, gsi);
3809 idx = find_irq_entry(ioapic, pin, mp_INT);
3813 *trigger = irq_trigger(idx);
3814 *polarity = irq_polarity(idx);
3819 * This function currently is only a helper for the i386 smp boot process where
3820 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3821 * so mask in all cases should simply be apic->target_cpus()
3824 void __init setup_ioapic_dest(void)
3826 int pin, ioapic, irq, irq_entry;
3827 const struct cpumask *mask;
3828 struct irq_data *idata;
3830 if (skip_ioapic_setup == 1)
3833 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3834 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3835 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3836 if (irq_entry == -1)
3838 irq = pin_2_irq(irq_entry, ioapic, pin);
3840 if ((ioapic > 0) && (irq > 16))
3843 idata = irq_get_irq_data(irq);
3846 * Honour affinities which have been set in early boot
3848 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3849 mask = idata->affinity;
3851 mask = apic->target_cpus();
3853 if (intr_remapping_enabled)
3854 ir_ioapic_set_affinity(idata, mask, false);
3856 ioapic_set_affinity(idata, mask, false);
3862 #define IOAPIC_RESOURCE_NAME_SIZE 11
3864 static struct resource *ioapic_resources;
3866 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3869 struct resource *res;
3873 if (nr_ioapics <= 0)
3876 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3879 mem = alloc_bootmem(n);
3882 mem += sizeof(struct resource) * nr_ioapics;
3884 for (i = 0; i < nr_ioapics; i++) {
3886 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3887 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3888 mem += IOAPIC_RESOURCE_NAME_SIZE;
3891 ioapic_resources = res;
3896 void __init ioapic_and_gsi_init(void)
3898 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3899 struct resource *ioapic_res;
3902 ioapic_res = ioapic_setup_resources(nr_ioapics);
3903 for (i = 0; i < nr_ioapics; i++) {
3904 if (smp_found_config) {
3905 ioapic_phys = mpc_ioapic_addr(i);
3906 #ifdef CONFIG_X86_32
3909 "WARNING: bogus zero IO-APIC "
3910 "address found in MPTABLE, "
3911 "disabling IO/APIC support!\n");
3912 smp_found_config = 0;
3913 skip_ioapic_setup = 1;
3914 goto fake_ioapic_page;
3918 #ifdef CONFIG_X86_32
3921 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3922 ioapic_phys = __pa(ioapic_phys);
3924 set_fixmap_nocache(idx, ioapic_phys);
3925 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3926 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3930 ioapic_res->start = ioapic_phys;
3931 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3935 probe_nr_irqs_gsi();
3938 void __init ioapic_insert_resources(void)
3941 struct resource *r = ioapic_resources;
3946 "IO APIC resources couldn't be allocated.\n");
3950 for (i = 0; i < nr_ioapics; i++) {
3951 insert_resource(&iomem_resource, r);
3956 int mp_find_ioapic(u32 gsi)
3960 if (nr_ioapics == 0)
3963 /* Find the IOAPIC that manages this GSI. */
3964 for (i = 0; i < nr_ioapics; i++) {
3965 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3966 if ((gsi >= gsi_cfg->gsi_base)
3967 && (gsi <= gsi_cfg->gsi_end))
3971 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3975 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3977 struct mp_ioapic_gsi *gsi_cfg;
3979 if (WARN_ON(ioapic == -1))
3982 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3983 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3986 return gsi - gsi_cfg->gsi_base;
3989 static __init int bad_ioapic(unsigned long address)
3991 if (nr_ioapics >= MAX_IO_APICS) {
3992 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3993 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3997 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3998 " found in table, skipping!\n");
4004 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4008 struct mp_ioapic_gsi *gsi_cfg;
4010 if (bad_ioapic(address))
4015 ioapics[idx].mp_config.type = MP_IOAPIC;
4016 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
4017 ioapics[idx].mp_config.apicaddr = address;
4019 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4020 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4021 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4024 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4025 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4027 entries = io_apic_get_redir_entries(idx);
4028 gsi_cfg = mp_ioapic_gsi_routing(idx);
4029 gsi_cfg->gsi_base = gsi_base;
4030 gsi_cfg->gsi_end = gsi_base + entries - 1;
4033 * The number of IO-APIC IRQ registers (== #pins):
4035 ioapics[idx].nr_registers = entries;
4037 if (gsi_cfg->gsi_end >= gsi_top)
4038 gsi_top = gsi_cfg->gsi_end + 1;
4040 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4041 "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
4042 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4043 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4048 /* Enable IOAPIC early just for system timer */
4049 void __init pre_init_apic_IRQ0(void)
4051 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4053 printk(KERN_INFO "Early APIC setup for system timer0\n");
4055 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4056 &phys_cpu_present_map);
4060 io_apic_setup_irq_pin(0, 0, &attr);
4061 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,