2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
60 unsigned int num_processors;
62 unsigned disabled_cpus;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_physical_apicid = -1U;
66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68 u8 boot_cpu_apic_version;
71 * The highest APIC ID seen during enumeration.
73 static unsigned int max_physical_apicid;
76 * Bitmask of physically existing CPUs:
78 physid_mask_t phys_cpu_present_map;
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
91 static int apic_extnmi = APIC_EXTNMI_BSP;
94 * Map cpu index to physical APIC ID
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
124 static inline void imcr_pic_to_apic(void)
126 /* select IMCR register */
128 /* NMI and 8259 INTR go through APIC */
132 static inline void imcr_apic_to_pic(void)
134 /* select IMCR register */
136 /* NMI and 8259 INTR go directly to BSP */
142 * Knob to control our willingness to enable the local APIC.
146 static int force_enable_local_apic __initdata;
149 * APIC command line parameters
151 static int __init parse_lapic(char *arg)
153 if (IS_ENABLED(CONFIG_X86_32) && !arg)
154 force_enable_local_apic = 1;
155 else if (arg && !strncmp(arg, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
159 early_param("lapic", parse_lapic);
162 static int apic_calibrate_pmtmr __initdata;
163 static __init int setup_apicpmtimer(char *s)
165 apic_calibrate_pmtmr = 1;
169 __setup("apicpmtimer", setup_apicpmtimer);
172 unsigned long mp_lapic_addr;
174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
175 static int disable_apic_timer __initdata;
176 /* Local APIC timer works in C2 */
177 int local_apic_timer_c2_ok;
178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
181 * Debug level, exported for io_apic.c
183 unsigned int apic_verbosity;
187 /* Have we found an MP table */
188 int smp_found_config;
190 static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 unsigned int lapic_timer_frequency = 0;
197 static void apic_pm_activate(void);
199 static unsigned long apic_phys;
202 * Get the LAPIC version
204 static inline int lapic_get_version(void)
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
210 * Check, if the APIC is integrated or a separate chip
212 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
222 * Check, whether this is a modern or a first generation APIC
224 static int modern_apic(void)
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
228 boot_cpu_data.x86 >= 0xf)
230 return lapic_get_version() >= 0x14;
234 * right after this call apic become NOOP driven
235 * so apic->write/read doesn't do anything
237 static void __init apic_disable(void)
239 pr_info("APIC: switched to apic NOOP\n");
243 void native_apic_wait_icr_idle(void)
245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
249 u32 native_safe_apic_wait_icr_idle(void)
256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
259 inc_irq_stat(icr_read_retry_count);
261 } while (timeout++ < 1000);
266 void native_apic_icr_write(u32 low, u32 id)
270 local_irq_save(flags);
271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272 apic_write(APIC_ICR, low);
273 local_irq_restore(flags);
276 u64 native_apic_icr_read(void)
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
283 return icr1 | ((u64)icr2 << 32);
288 * get_physical_broadcast - Get number of physical broadcast IDs
290 int get_physical_broadcast(void)
292 return modern_apic() ? 0xff : 0xf;
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 int lapic_get_maxlvt(void)
303 v = apic_read(APIC_LVR);
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR 8
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 unsigned int lvtt_value, tmp_value;
333 lvtt_value = LOCAL_TIMER_VECTOR;
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 if (!lapic_is_integrated())
340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343 lvtt_value |= APIC_LVT_MASKED;
345 apic_write(APIC_LVTT, lvtt_value);
347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
353 asm volatile("mfence" : : : "memory");
355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372 * Setup extended LVT, AMD specific
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 return (old & APIC_EILVT_MASKED)
396 || (new == APIC_EILVT_MASKED)
397 || ((new & ~APIC_EILVT_MASKED) == old);
400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 unsigned int rsvd, vector;
404 if (offset >= APIC_EILVT_NR_MAX)
407 rsvd = atomic_read(&eilvt_offsets[offset]);
409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
410 if (vector && !eilvt_entry_is_changeable(vector, new))
411 /* may not change if vectors are different */
413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
414 } while (rsvd != new);
416 rsvd &= ~APIC_EILVT_MASKED;
417 if (rsvd && rsvd != vector)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 unsigned long reg = APIC_EILVTn(offset);
433 unsigned int new, old, reserved;
435 new = (mask << 16) | (msg_type << 8) | vector;
436 old = apic_read(reg);
437 reserved = reserve_eilvt_offset(offset, new);
439 if (reserved != new) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg, offset, new, reserved);
447 if (!eilvt_entry_is_changeable(old, new)) {
448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg, offset, new, old);
455 apic_write(reg, new);
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
462 * Program the next event, relative to now
464 static int lapic_next_event(unsigned long delta,
465 struct clock_event_device *evt)
467 apic_write(APIC_TMICT, delta);
471 static int lapic_next_deadline(unsigned long delta,
472 struct clock_event_device *evt)
477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
481 static int lapic_timer_shutdown(struct clock_event_device *evt)
485 /* Lapic used as dummy for broadcast ? */
486 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
489 v = apic_read(APIC_LVTT);
490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
491 apic_write(APIC_LVTT, v);
492 apic_write(APIC_TMICT, 0);
497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499 /* Lapic used as dummy for broadcast ? */
500 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
507 static int lapic_timer_set_periodic(struct clock_event_device *evt)
509 return lapic_timer_set_periodic_oneshot(evt, false);
512 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514 return lapic_timer_set_periodic_oneshot(evt, true);
518 * Local APIC timer broadcast function
520 static void lapic_timer_broadcast(const struct cpumask *mask)
523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
529 * The local apic timer can be used for any function which is CPU local.
531 static struct clock_event_device lapic_clockevent = {
533 .features = CLOCK_EVT_FEAT_PERIODIC |
534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
535 | CLOCK_EVT_FEAT_DUMMY,
537 .set_state_shutdown = lapic_timer_shutdown,
538 .set_state_periodic = lapic_timer_set_periodic,
539 .set_state_oneshot = lapic_timer_set_oneshot,
540 .set_state_oneshot_stopped = lapic_timer_shutdown,
541 .set_next_event = lapic_next_event,
542 .broadcast = lapic_timer_broadcast,
546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
548 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
549 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
551 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
554 static u32 hsx_deadline_rev(void)
556 switch (boot_cpu_data.x86_stepping) {
557 case 0x02: return 0x3a; /* EP */
558 case 0x04: return 0x0f; /* EX */
564 static u32 bdx_deadline_rev(void)
566 switch (boot_cpu_data.x86_stepping) {
567 case 0x02: return 0x00000011;
568 case 0x03: return 0x0700000e;
569 case 0x04: return 0x0f00000c;
570 case 0x05: return 0x0e000003;
576 static u32 skx_deadline_rev(void)
578 switch (boot_cpu_data.x86_stepping) {
579 case 0x03: return 0x01000136;
580 case 0x04: return 0x02000014;
583 if (boot_cpu_data.x86_stepping > 4)
589 static const struct x86_cpu_id deadline_match[] = {
590 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
592 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
602 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
605 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
611 static void apic_check_deadline_errata(void)
613 const struct x86_cpu_id *m;
616 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
617 boot_cpu_has(X86_FEATURE_HYPERVISOR))
620 m = x86_match_cpu(deadline_match);
625 * Function pointers will have the MSB set due to address layout,
626 * immediate revisions will not.
628 if ((long)m->driver_data < 0)
629 rev = ((u32 (*)(void))(m->driver_data))();
631 rev = (u32)m->driver_data;
633 if (boot_cpu_data.microcode >= rev)
636 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
637 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
638 "please update microcode to version: 0x%x (or later)\n", rev);
642 * Setup the local APIC timer for this CPU. Copy the initialized values
643 * of the boot CPU and register the clock event in the framework.
645 static void setup_APIC_timer(void)
647 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
649 if (this_cpu_has(X86_FEATURE_ARAT)) {
650 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
651 /* Make LAPIC timer preferrable over percpu HPET */
652 lapic_clockevent.rating = 150;
655 memcpy(levt, &lapic_clockevent, sizeof(*levt));
656 levt->cpumask = cpumask_of(smp_processor_id());
658 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
659 levt->name = "lapic-deadline";
660 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
661 CLOCK_EVT_FEAT_DUMMY);
662 levt->set_next_event = lapic_next_deadline;
663 clockevents_config_and_register(levt,
664 tsc_khz * (1000 / TSC_DIVISOR),
667 clockevents_register_device(levt);
671 * Install the updated TSC frequency from recalibration at the TSC
672 * deadline clockevent devices.
674 static void __lapic_update_tsc_freq(void *info)
676 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
678 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
681 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
684 void lapic_update_tsc_freq(void)
687 * The clockevent device's ->mult and ->shift can both be
688 * changed. In order to avoid races, schedule the frequency
689 * update code on each CPU.
691 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
695 * In this functions we calibrate APIC bus clocks to the external timer.
697 * We want to do the calibration only once since we want to have local timer
698 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
701 * This was previously done by reading the PIT/HPET and waiting for a wrap
702 * around to find out, that a tick has elapsed. I have a box, where the PIT
703 * readout is broken, so it never gets out of the wait loop again. This was
704 * also reported by others.
706 * Monitoring the jiffies value is inaccurate and the clockevents
707 * infrastructure allows us to do a simple substitution of the interrupt
710 * The calibration routine also uses the pm_timer when possible, as the PIT
711 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
712 * back to normal later in the boot process).
715 #define LAPIC_CAL_LOOPS (HZ/10)
717 static __initdata int lapic_cal_loops = -1;
718 static __initdata long lapic_cal_t1, lapic_cal_t2;
719 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
720 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
721 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
724 * Temporary interrupt handler.
726 static void __init lapic_cal_handler(struct clock_event_device *dev)
728 unsigned long long tsc = 0;
729 long tapic = apic_read(APIC_TMCCT);
730 unsigned long pm = acpi_pm_read_early();
732 if (boot_cpu_has(X86_FEATURE_TSC))
735 switch (lapic_cal_loops++) {
737 lapic_cal_t1 = tapic;
738 lapic_cal_tsc1 = tsc;
740 lapic_cal_j1 = jiffies;
743 case LAPIC_CAL_LOOPS:
744 lapic_cal_t2 = tapic;
745 lapic_cal_tsc2 = tsc;
746 if (pm < lapic_cal_pm1)
747 pm += ACPI_PM_OVRRUN;
749 lapic_cal_j2 = jiffies;
755 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
757 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
758 const long pm_thresh = pm_100ms / 100;
762 #ifndef CONFIG_X86_PM_TIMER
766 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
768 /* Check, if the PM timer is available */
772 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
774 if (deltapm > (pm_100ms - pm_thresh) &&
775 deltapm < (pm_100ms + pm_thresh)) {
776 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
780 res = (((u64)deltapm) * mult) >> 22;
781 do_div(res, 1000000);
782 pr_warning("APIC calibration not consistent "
783 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
785 /* Correct the lapic counter value */
786 res = (((u64)(*delta)) * pm_100ms);
787 do_div(res, deltapm);
788 pr_info("APIC delta adjusted to PM-Timer: "
789 "%lu (%ld)\n", (unsigned long)res, *delta);
792 /* Correct the tsc counter value */
793 if (boot_cpu_has(X86_FEATURE_TSC)) {
794 res = (((u64)(*deltatsc)) * pm_100ms);
795 do_div(res, deltapm);
796 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
797 "PM-Timer: %lu (%ld)\n",
798 (unsigned long)res, *deltatsc);
799 *deltatsc = (long)res;
805 static int __init calibrate_APIC_clock(void)
807 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
808 void (*real_handler)(struct clock_event_device *dev);
809 unsigned long deltaj;
810 long delta, deltatsc;
811 int pm_referenced = 0;
814 * check if lapic timer has already been calibrated by platform
815 * specific routine, such as tsc calibration code. if so, we just fill
816 * in the clockevent structure and return.
819 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
821 } else if (lapic_timer_frequency) {
822 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
823 lapic_timer_frequency);
824 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
825 TICK_NSEC, lapic_clockevent.shift);
826 lapic_clockevent.max_delta_ns =
827 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
828 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
829 lapic_clockevent.min_delta_ns =
830 clockevent_delta2ns(0xF, &lapic_clockevent);
831 lapic_clockevent.min_delta_ticks = 0xF;
832 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
836 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
837 "calibrating APIC timer ...\n");
841 /* Replace the global interrupt handler */
842 real_handler = global_clock_event->event_handler;
843 global_clock_event->event_handler = lapic_cal_handler;
846 * Setup the APIC counter to maximum. There is no way the lapic
847 * can underflow in the 100ms detection time frame
849 __setup_APIC_LVTT(0xffffffff, 0, 0);
851 /* Let the interrupts run */
854 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
859 /* Restore the real event handler */
860 global_clock_event->event_handler = real_handler;
862 /* Build delta t1-t2 as apic timer counts down */
863 delta = lapic_cal_t1 - lapic_cal_t2;
864 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
866 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
868 /* we trust the PM based calibration if possible */
869 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
872 /* Calculate the scaled math multiplication factor */
873 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
874 lapic_clockevent.shift);
875 lapic_clockevent.max_delta_ns =
876 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
877 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
878 lapic_clockevent.min_delta_ns =
879 clockevent_delta2ns(0xF, &lapic_clockevent);
880 lapic_clockevent.min_delta_ticks = 0xF;
882 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
884 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
885 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
886 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
887 lapic_timer_frequency);
889 if (boot_cpu_has(X86_FEATURE_TSC)) {
890 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
892 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
893 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
896 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
898 lapic_timer_frequency / (1000000 / HZ),
899 lapic_timer_frequency % (1000000 / HZ));
902 * Do a sanity check on the APIC calibration result
904 if (lapic_timer_frequency < (1000000 / HZ)) {
906 pr_warning("APIC frequency too slow, disabling apic timer\n");
910 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
913 * PM timer calibration failed or not turned on
914 * so lets try APIC timer based calibration
916 if (!pm_referenced) {
917 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
920 * Setup the apic timer manually
922 levt->event_handler = lapic_cal_handler;
923 lapic_timer_set_periodic(levt);
924 lapic_cal_loops = -1;
926 /* Let the interrupts run */
929 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
932 /* Stop the lapic timer */
934 lapic_timer_shutdown(levt);
937 deltaj = lapic_cal_j2 - lapic_cal_j1;
938 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
940 /* Check, if the jiffies result is consistent */
941 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
942 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
944 levt->features |= CLOCK_EVT_FEAT_DUMMY;
948 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
949 pr_warning("APIC timer disabled due to verification failure\n");
957 * Setup the boot APIC
959 * Calibrate and verify the result.
961 void __init setup_boot_APIC_clock(void)
964 * The local apic timer can be disabled via the kernel
965 * commandline or from the CPU detection code. Register the lapic
966 * timer as a dummy clock event source on SMP systems, so the
967 * broadcast mechanism is used. On UP systems simply ignore it.
969 if (disable_apic_timer) {
970 pr_info("Disabling APIC timer\n");
971 /* No broadcast on UP ! */
972 if (num_possible_cpus() > 1) {
973 lapic_clockevent.mult = 1;
979 if (calibrate_APIC_clock()) {
980 /* No broadcast on UP ! */
981 if (num_possible_cpus() > 1)
987 * If nmi_watchdog is set to IO_APIC, we need the
988 * PIT/HPET going. Otherwise register lapic as a dummy
991 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
993 /* Setup the lapic or request the broadcast */
995 amd_e400_c1e_apic_setup();
998 void setup_secondary_APIC_clock(void)
1001 amd_e400_c1e_apic_setup();
1005 * The guts of the apic timer interrupt
1007 static void local_apic_timer_interrupt(void)
1009 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1012 * Normally we should not be here till LAPIC has been initialized but
1013 * in some cases like kdump, its possible that there is a pending LAPIC
1014 * timer interrupt from previous kernel's context and is delivered in
1015 * new kernel the moment interrupts are enabled.
1017 * Interrupts are enabled early and LAPIC is setup much later, hence
1018 * its possible that when we get here evt->event_handler is NULL.
1019 * Check for event_handler being NULL and discard the interrupt as
1022 if (!evt->event_handler) {
1023 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1024 smp_processor_id());
1026 lapic_timer_shutdown(evt);
1031 * the NMI deadlock-detector uses this.
1033 inc_irq_stat(apic_timer_irqs);
1035 evt->event_handler(evt);
1039 * Local APIC timer interrupt. This is the most natural way for doing
1040 * local interrupts, but local timer interrupts can be emulated by
1041 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1043 * [ if a single-CPU system runs an SMP kernel then we call the local
1044 * interrupt as well. Thus we cannot inline the local irq ... ]
1046 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1048 struct pt_regs *old_regs = set_irq_regs(regs);
1051 * NOTE! We'd better ACK the irq immediately,
1052 * because timer handling can be slow.
1054 * update_process_times() expects us to have done irq_enter().
1055 * Besides, if we don't timer interrupts ignore the global
1056 * interrupt lock, which is the WrongThing (tm) to do.
1059 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1060 local_apic_timer_interrupt();
1061 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1064 set_irq_regs(old_regs);
1067 int setup_profiling_timer(unsigned int multiplier)
1073 * Local APIC start and shutdown
1077 * clear_local_APIC - shutdown the local APIC
1079 * This is called, when a CPU is disabled and before rebooting, so the state of
1080 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1081 * leftovers during boot.
1083 void clear_local_APIC(void)
1088 /* APIC hasn't been mapped yet */
1089 if (!x2apic_mode && !apic_phys)
1092 maxlvt = lapic_get_maxlvt();
1094 * Masking an LVT entry can trigger a local APIC error
1095 * if the vector is zero. Mask LVTERR first to prevent this.
1098 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1099 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1102 * Careful: we have to set masks only first to deassert
1103 * any level-triggered sources.
1105 v = apic_read(APIC_LVTT);
1106 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1107 v = apic_read(APIC_LVT0);
1108 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1109 v = apic_read(APIC_LVT1);
1110 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1112 v = apic_read(APIC_LVTPC);
1113 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1116 /* lets not touch this if we didn't frob it */
1117 #ifdef CONFIG_X86_THERMAL_VECTOR
1119 v = apic_read(APIC_LVTTHMR);
1120 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1123 #ifdef CONFIG_X86_MCE_INTEL
1125 v = apic_read(APIC_LVTCMCI);
1126 if (!(v & APIC_LVT_MASKED))
1127 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1132 * Clean APIC state for other OSs:
1134 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1135 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1136 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1138 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1140 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1142 /* Integrated APIC (!82489DX) ? */
1143 if (lapic_is_integrated()) {
1145 /* Clear ESR due to Pentium errata 3AP and 11AP */
1146 apic_write(APIC_ESR, 0);
1147 apic_read(APIC_ESR);
1152 * disable_local_APIC - clear and disable the local APIC
1154 void disable_local_APIC(void)
1158 /* APIC hasn't been mapped yet */
1159 if (!x2apic_mode && !apic_phys)
1165 * Disable APIC (implies clearing of registers
1168 value = apic_read(APIC_SPIV);
1169 value &= ~APIC_SPIV_APIC_ENABLED;
1170 apic_write(APIC_SPIV, value);
1172 #ifdef CONFIG_X86_32
1174 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1175 * restore the disabled state.
1177 if (enabled_via_apicbase) {
1180 rdmsr(MSR_IA32_APICBASE, l, h);
1181 l &= ~MSR_IA32_APICBASE_ENABLE;
1182 wrmsr(MSR_IA32_APICBASE, l, h);
1188 * If Linux enabled the LAPIC against the BIOS default disable it down before
1189 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1190 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1191 * for the case where Linux didn't enable the LAPIC.
1193 void lapic_shutdown(void)
1195 unsigned long flags;
1197 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1200 local_irq_save(flags);
1202 #ifdef CONFIG_X86_32
1203 if (!enabled_via_apicbase)
1207 disable_local_APIC();
1210 local_irq_restore(flags);
1214 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1216 void __init sync_Arb_IDs(void)
1219 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1222 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1228 apic_wait_icr_idle();
1230 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1231 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1232 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1236 * An initial setup of the virtual wire mode.
1238 void __init init_bsp_APIC(void)
1243 * Don't do the setup now if we have a SMP BIOS as the
1244 * through-I/O-APIC virtual wire mode might be active.
1246 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1250 * Do not trust the local APIC being empty at bootup.
1257 value = apic_read(APIC_SPIV);
1258 value &= ~APIC_VECTOR_MASK;
1259 value |= APIC_SPIV_APIC_ENABLED;
1261 #ifdef CONFIG_X86_32
1262 /* This bit is reserved on P4/Xeon and should be cleared */
1263 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1264 (boot_cpu_data.x86 == 15))
1265 value &= ~APIC_SPIV_FOCUS_DISABLED;
1268 value |= APIC_SPIV_FOCUS_DISABLED;
1269 value |= SPURIOUS_APIC_VECTOR;
1270 apic_write(APIC_SPIV, value);
1273 * Set up the virtual wire mode.
1275 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1276 value = APIC_DM_NMI;
1277 if (!lapic_is_integrated()) /* 82489DX */
1278 value |= APIC_LVT_LEVEL_TRIGGER;
1279 if (apic_extnmi == APIC_EXTNMI_NONE)
1280 value |= APIC_LVT_MASKED;
1281 apic_write(APIC_LVT1, value);
1284 static void lapic_setup_esr(void)
1286 unsigned int oldvalue, value, maxlvt;
1288 if (!lapic_is_integrated()) {
1289 pr_info("No ESR for 82489DX.\n");
1293 if (apic->disable_esr) {
1295 * Something untraceable is creating bad interrupts on
1296 * secondary quads ... for the moment, just leave the
1297 * ESR disabled - we can't do anything useful with the
1298 * errors anyway - mbligh
1300 pr_info("Leaving ESR disabled.\n");
1304 maxlvt = lapic_get_maxlvt();
1305 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1306 apic_write(APIC_ESR, 0);
1307 oldvalue = apic_read(APIC_ESR);
1309 /* enables sending errors */
1310 value = ERROR_APIC_VECTOR;
1311 apic_write(APIC_LVTERR, value);
1314 * spec says clear errors after enabling vector.
1317 apic_write(APIC_ESR, 0);
1318 value = apic_read(APIC_ESR);
1319 if (value != oldvalue)
1320 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1321 "vector: 0x%08x after: 0x%08x\n",
1326 * setup_local_APIC - setup the local APIC
1328 * Used to setup local APIC while initializing BSP or bringing up APs.
1329 * Always called with preemption disabled.
1331 void setup_local_APIC(void)
1333 int cpu = smp_processor_id();
1334 unsigned int value, queued;
1335 int i, j, acked = 0;
1336 unsigned long long tsc = 0, ntsc;
1337 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1339 if (boot_cpu_has(X86_FEATURE_TSC))
1343 disable_ioapic_support();
1347 #ifdef CONFIG_X86_32
1348 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1349 if (lapic_is_integrated() && apic->disable_esr) {
1350 apic_write(APIC_ESR, 0);
1351 apic_write(APIC_ESR, 0);
1352 apic_write(APIC_ESR, 0);
1353 apic_write(APIC_ESR, 0);
1356 perf_events_lapic_init();
1359 * Double-check whether this APIC is really registered.
1360 * This is meaningless in clustered apic mode, so we skip it.
1362 BUG_ON(!apic->apic_id_registered());
1365 * Intel recommends to set DFR, LDR and TPR before enabling
1366 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1367 * document number 292116). So here it goes...
1369 apic->init_apic_ldr();
1371 #ifdef CONFIG_X86_32
1373 * APIC LDR is initialized. If logical_apicid mapping was
1374 * initialized during get_smp_config(), make sure it matches the
1377 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1378 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1379 /* always use the value from LDR */
1380 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1381 logical_smp_processor_id();
1385 * Set Task Priority to 'accept all'. We never change this
1388 value = apic_read(APIC_TASKPRI);
1389 value &= ~APIC_TPRI_MASK;
1390 apic_write(APIC_TASKPRI, value);
1393 * After a crash, we no longer service the interrupts and a pending
1394 * interrupt from previous kernel might still have ISR bit set.
1396 * Most probably by now CPU has serviced that pending interrupt and
1397 * it might not have done the ack_APIC_irq() because it thought,
1398 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1399 * does not clear the ISR bit and cpu thinks it has already serivced
1400 * the interrupt. Hence a vector might get locked. It was noticed
1401 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1405 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1406 queued |= apic_read(APIC_IRR + i*0x10);
1408 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1409 value = apic_read(APIC_ISR + i*0x10);
1410 for (j = 31; j >= 0; j--) {
1411 if (value & (1<<j)) {
1418 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1423 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1425 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1429 } while (queued && max_loops > 0);
1430 WARN_ON(max_loops <= 0);
1433 * Now that we are all set up, enable the APIC
1435 value = apic_read(APIC_SPIV);
1436 value &= ~APIC_VECTOR_MASK;
1440 value |= APIC_SPIV_APIC_ENABLED;
1442 #ifdef CONFIG_X86_32
1444 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1445 * certain networking cards. If high frequency interrupts are
1446 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1447 * entry is masked/unmasked at a high rate as well then sooner or
1448 * later IOAPIC line gets 'stuck', no more interrupts are received
1449 * from the device. If focus CPU is disabled then the hang goes
1452 * [ This bug can be reproduced easily with a level-triggered
1453 * PCI Ne2000 networking cards and PII/PIII processors, dual
1457 * Actually disabling the focus CPU check just makes the hang less
1458 * frequent as it makes the interrupt distributon model be more
1459 * like LRU than MRU (the short-term load is more even across CPUs).
1463 * - enable focus processor (bit==0)
1464 * - 64bit mode always use processor focus
1465 * so no need to set it
1467 value &= ~APIC_SPIV_FOCUS_DISABLED;
1471 * Set spurious IRQ vector
1473 value |= SPURIOUS_APIC_VECTOR;
1474 apic_write(APIC_SPIV, value);
1477 * Set up LVT0, LVT1:
1479 * set up through-local-APIC on the BP's LINT0. This is not
1480 * strictly necessary in pure symmetric-IO mode, but sometimes
1481 * we delegate interrupts to the 8259A.
1484 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1486 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1487 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1488 value = APIC_DM_EXTINT;
1489 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1491 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1492 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1494 apic_write(APIC_LVT0, value);
1497 * Only the BSP sees the LINT1 NMI signal by default. This can be
1498 * modified by apic_extnmi= boot option.
1500 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1501 apic_extnmi == APIC_EXTNMI_ALL)
1502 value = APIC_DM_NMI;
1504 value = APIC_DM_NMI | APIC_LVT_MASKED;
1505 if (!lapic_is_integrated()) /* 82489DX */
1506 value |= APIC_LVT_LEVEL_TRIGGER;
1507 apic_write(APIC_LVT1, value);
1509 #ifdef CONFIG_X86_MCE_INTEL
1510 /* Recheck CMCI information after local APIC is up on CPU #0 */
1516 static void end_local_APIC_setup(void)
1520 #ifdef CONFIG_X86_32
1523 /* Disable the local apic timer */
1524 value = apic_read(APIC_LVTT);
1525 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1526 apic_write(APIC_LVTT, value);
1534 * APIC setup function for application processors. Called from smpboot.c
1536 void apic_ap_setup(void)
1539 end_local_APIC_setup();
1542 #ifdef CONFIG_X86_X2APIC
1550 static int x2apic_state;
1552 static void __x2apic_disable(void)
1556 if (!boot_cpu_has(X86_FEATURE_APIC))
1559 rdmsrl(MSR_IA32_APICBASE, msr);
1560 if (!(msr & X2APIC_ENABLE))
1562 /* Disable xapic and x2apic first and then reenable xapic mode */
1563 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1564 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1565 printk_once(KERN_INFO "x2apic disabled\n");
1568 static void __x2apic_enable(void)
1572 rdmsrl(MSR_IA32_APICBASE, msr);
1573 if (msr & X2APIC_ENABLE)
1575 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1576 printk_once(KERN_INFO "x2apic enabled\n");
1579 static int __init setup_nox2apic(char *str)
1581 if (x2apic_enabled()) {
1582 int apicid = native_apic_msr_read(APIC_ID);
1584 if (apicid >= 255) {
1585 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1589 pr_warning("x2apic already enabled.\n");
1592 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1593 x2apic_state = X2APIC_DISABLED;
1597 early_param("nox2apic", setup_nox2apic);
1599 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1600 void x2apic_setup(void)
1603 * If x2apic is not in ON state, disable it if already enabled
1606 if (x2apic_state != X2APIC_ON) {
1613 static __init void x2apic_disable(void)
1615 u32 x2apic_id, state = x2apic_state;
1618 x2apic_state = X2APIC_DISABLED;
1620 if (state != X2APIC_ON)
1623 x2apic_id = read_apic_id();
1624 if (x2apic_id >= 255)
1625 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1628 register_lapic_address(mp_lapic_addr);
1631 static __init void x2apic_enable(void)
1633 if (x2apic_state != X2APIC_OFF)
1637 x2apic_state = X2APIC_ON;
1641 static __init void try_to_enable_x2apic(int remap_mode)
1643 if (x2apic_state == X2APIC_DISABLED)
1646 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1647 /* IR is required if there is APIC ID > 255 even when running
1650 if (max_physical_apicid > 255 ||
1651 !x86_init.hyper.x2apic_available()) {
1652 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1658 * without IR all CPUs can be addressed by IOAPIC/MSI
1659 * only in physical mode
1666 void __init check_x2apic(void)
1668 if (x2apic_enabled()) {
1669 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1671 x2apic_state = X2APIC_ON;
1672 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1673 x2apic_state = X2APIC_DISABLED;
1676 #else /* CONFIG_X86_X2APIC */
1677 static int __init validate_x2apic(void)
1679 if (!apic_is_x2apic_enabled())
1682 * Checkme: Can we simply turn off x2apic here instead of panic?
1684 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1686 early_initcall(validate_x2apic);
1688 static inline void try_to_enable_x2apic(int remap_mode) { }
1689 static inline void __x2apic_enable(void) { }
1690 #endif /* !CONFIG_X86_X2APIC */
1692 void __init enable_IR_x2apic(void)
1694 unsigned long flags;
1697 if (skip_ioapic_setup) {
1698 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1702 ir_stat = irq_remapping_prepare();
1703 if (ir_stat < 0 && !x2apic_supported())
1706 ret = save_ioapic_entries();
1708 pr_info("Saving IO-APIC state failed: %d\n", ret);
1712 local_irq_save(flags);
1713 legacy_pic->mask_all();
1714 mask_ioapic_entries();
1716 /* If irq_remapping_prepare() succeeded, try to enable it */
1718 ir_stat = irq_remapping_enable();
1719 /* ir_stat contains the remap mode or an error code */
1720 try_to_enable_x2apic(ir_stat);
1723 restore_ioapic_entries();
1724 legacy_pic->restore_mask();
1725 local_irq_restore(flags);
1728 #ifdef CONFIG_X86_64
1730 * Detect and enable local APICs on non-SMP boards.
1731 * Original code written by Keir Fraser.
1732 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1733 * not correctly set up (usually the APIC timer won't work etc.)
1735 static int __init detect_init_APIC(void)
1737 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1738 pr_info("No local APIC present\n");
1742 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1747 static int __init apic_verify(void)
1752 * The APIC feature bit should now be enabled
1755 features = cpuid_edx(1);
1756 if (!(features & (1 << X86_FEATURE_APIC))) {
1757 pr_warning("Could not enable APIC!\n");
1760 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1761 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1763 /* The BIOS may have set up the APIC at some other address */
1764 if (boot_cpu_data.x86 >= 6) {
1765 rdmsr(MSR_IA32_APICBASE, l, h);
1766 if (l & MSR_IA32_APICBASE_ENABLE)
1767 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1770 pr_info("Found and enabled local APIC!\n");
1774 int __init apic_force_enable(unsigned long addr)
1782 * Some BIOSes disable the local APIC in the APIC_BASE
1783 * MSR. This can only be done in software for Intel P6 or later
1784 * and AMD K7 (Model > 1) or later.
1786 if (boot_cpu_data.x86 >= 6) {
1787 rdmsr(MSR_IA32_APICBASE, l, h);
1788 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1789 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1790 l &= ~MSR_IA32_APICBASE_BASE;
1791 l |= MSR_IA32_APICBASE_ENABLE | addr;
1792 wrmsr(MSR_IA32_APICBASE, l, h);
1793 enabled_via_apicbase = 1;
1796 return apic_verify();
1800 * Detect and initialize APIC
1802 static int __init detect_init_APIC(void)
1804 /* Disabled by kernel option? */
1808 switch (boot_cpu_data.x86_vendor) {
1809 case X86_VENDOR_AMD:
1810 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1811 (boot_cpu_data.x86 >= 15))
1814 case X86_VENDOR_INTEL:
1815 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1816 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1823 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1825 * Over-ride BIOS and try to enable the local APIC only if
1826 * "lapic" specified.
1828 if (!force_enable_local_apic) {
1829 pr_info("Local APIC disabled by BIOS -- "
1830 "you can enable it with \"lapic\"\n");
1833 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1845 pr_info("No local APIC present or hardware disabled\n");
1851 * init_apic_mappings - initialize APIC mappings
1853 void __init init_apic_mappings(void)
1855 unsigned int new_apicid;
1857 apic_check_deadline_errata();
1860 boot_cpu_physical_apicid = read_apic_id();
1864 /* If no local APIC can be found return early */
1865 if (!smp_found_config && detect_init_APIC()) {
1866 /* lets NOP'ify apic operations */
1867 pr_info("APIC: disable apic facility\n");
1870 apic_phys = mp_lapic_addr;
1873 * If the system has ACPI MADT tables or MP info, the LAPIC
1874 * address is already registered.
1876 if (!acpi_lapic && !smp_found_config)
1877 register_lapic_address(apic_phys);
1881 * Fetch the APIC ID of the BSP in case we have a
1882 * default configuration (or the MP table is broken).
1884 new_apicid = read_apic_id();
1885 if (boot_cpu_physical_apicid != new_apicid) {
1886 boot_cpu_physical_apicid = new_apicid;
1888 * yeah -- we lie about apic_version
1889 * in case if apic was disabled via boot option
1890 * but it's not a problem for SMP compiled kernel
1891 * since smp_sanity_check is prepared for such a case
1892 * and disable smp mode
1894 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1898 void __init register_lapic_address(unsigned long address)
1900 mp_lapic_addr = address;
1903 set_fixmap_nocache(FIX_APIC_BASE, address);
1904 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1905 APIC_BASE, address);
1907 if (boot_cpu_physical_apicid == -1U) {
1908 boot_cpu_physical_apicid = read_apic_id();
1909 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1914 * Local APIC interrupts
1918 * This interrupt should _never_ happen with our APIC/SMP architecture
1920 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1922 u8 vector = ~regs->orig_ax;
1926 trace_spurious_apic_entry(vector);
1929 * Check if this really is a spurious interrupt and ACK it
1930 * if it is a vectored one. Just in case...
1931 * Spurious interrupts should not be ACKed.
1933 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1934 if (v & (1 << (vector & 0x1f)))
1937 inc_irq_stat(irq_spurious_count);
1939 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1940 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1941 "should never happen.\n", vector, smp_processor_id());
1943 trace_spurious_apic_exit(vector);
1948 * This interrupt should never happen with our APIC/SMP architecture
1950 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
1952 static const char * const error_interrupt_reason[] = {
1953 "Send CS error", /* APIC Error Bit 0 */
1954 "Receive CS error", /* APIC Error Bit 1 */
1955 "Send accept error", /* APIC Error Bit 2 */
1956 "Receive accept error", /* APIC Error Bit 3 */
1957 "Redirectable IPI", /* APIC Error Bit 4 */
1958 "Send illegal vector", /* APIC Error Bit 5 */
1959 "Received illegal vector", /* APIC Error Bit 6 */
1960 "Illegal register address", /* APIC Error Bit 7 */
1965 trace_error_apic_entry(ERROR_APIC_VECTOR);
1967 /* First tickle the hardware, only then report what went on. -- REW */
1968 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1969 apic_write(APIC_ESR, 0);
1970 v = apic_read(APIC_ESR);
1972 atomic_inc(&irq_err_count);
1974 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1975 smp_processor_id(), v);
1980 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1985 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1987 trace_error_apic_exit(ERROR_APIC_VECTOR);
1992 * connect_bsp_APIC - attach the APIC to the interrupt system
1994 static void __init connect_bsp_APIC(void)
1996 #ifdef CONFIG_X86_32
1999 * Do not trust the local APIC being empty at bootup.
2003 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2004 * local APIC to INT and NMI lines.
2006 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2007 "enabling APIC mode.\n");
2014 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2015 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2017 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2020 void disconnect_bsp_APIC(int virt_wire_setup)
2024 #ifdef CONFIG_X86_32
2027 * Put the board back into PIC mode (has an effect only on
2028 * certain older boards). Note that APIC interrupts, including
2029 * IPIs, won't work beyond this point! The only exception are
2032 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2033 "entering PIC mode.\n");
2039 /* Go back to Virtual Wire compatibility mode */
2041 /* For the spurious interrupt use vector F, and enable it */
2042 value = apic_read(APIC_SPIV);
2043 value &= ~APIC_VECTOR_MASK;
2044 value |= APIC_SPIV_APIC_ENABLED;
2046 apic_write(APIC_SPIV, value);
2048 if (!virt_wire_setup) {
2050 * For LVT0 make it edge triggered, active high,
2051 * external and enabled
2053 value = apic_read(APIC_LVT0);
2054 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2055 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2056 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2057 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2058 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2059 apic_write(APIC_LVT0, value);
2062 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2066 * For LVT1 make it edge triggered, active high,
2069 value = apic_read(APIC_LVT1);
2070 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2071 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2072 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2073 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2074 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2075 apic_write(APIC_LVT1, value);
2079 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2080 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2081 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2082 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2084 * NOTE: Reserve 0 for BSP.
2086 static int nr_logical_cpuids = 1;
2089 * Used to store mapping between logical CPU IDs and APIC IDs.
2091 static int cpuid_to_apicid[] = {
2092 [0 ... NR_CPUS - 1] = -1,
2096 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2097 * @id: APIC ID to check
2099 bool apic_id_is_primary_thread(unsigned int apicid)
2103 if (smp_num_siblings == 1)
2105 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2106 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2107 return !(apicid & mask);
2111 * apic_id_disabled - Check whether APIC ID is disabled via SMT control
2112 * @id: APIC ID to check
2114 bool apic_id_disabled(unsigned int id)
2116 return (cpu_smt_control == CPU_SMT_FORCE_DISABLED &&
2117 !apic_id_is_primary_thread(id));
2121 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2122 * and cpuid_to_apicid[] synchronized.
2124 static int allocate_logical_cpuid(int apicid)
2129 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2130 * check if the kernel has allocated a cpuid for it.
2132 for (i = 0; i < nr_logical_cpuids; i++) {
2133 if (cpuid_to_apicid[i] == apicid)
2137 /* Allocate a new cpuid. */
2138 if (nr_logical_cpuids >= nr_cpu_ids) {
2139 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2140 "Processor %d/0x%x and the rest are ignored.\n",
2141 nr_cpu_ids, nr_logical_cpuids, apicid);
2145 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2146 return nr_logical_cpuids++;
2149 int generic_processor_info(int apicid, int version)
2151 int cpu, max = nr_cpu_ids;
2152 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2153 phys_cpu_present_map);
2156 * boot_cpu_physical_apicid is designed to have the apicid
2157 * returned by read_apic_id(), i.e, the apicid of the
2158 * currently booting-up processor. However, on some platforms,
2159 * it is temporarily modified by the apicid reported as BSP
2160 * through MP table. Concretely:
2162 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2163 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2165 * This function is executed with the modified
2166 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2167 * parameter doesn't work to disable APs on kdump 2nd kernel.
2169 * Since fixing handling of boot_cpu_physical_apicid requires
2170 * another discussion and tests on each platform, we leave it
2171 * for now and here we use read_apic_id() directly in this
2172 * function, generic_processor_info().
2174 if (disabled_cpu_apicid != BAD_APICID &&
2175 disabled_cpu_apicid != read_apic_id() &&
2176 disabled_cpu_apicid == apicid) {
2177 int thiscpu = num_processors + disabled_cpus;
2179 pr_warning("APIC: Disabling requested cpu."
2180 " Processor %d/0x%x ignored.\n",
2188 * If boot cpu has not been detected yet, then only allow upto
2189 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2191 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2192 apicid != boot_cpu_physical_apicid) {
2193 int thiscpu = max + disabled_cpus - 1;
2196 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2197 " reached. Keeping one slot for boot cpu."
2198 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2204 if (num_processors >= nr_cpu_ids) {
2205 int thiscpu = max + disabled_cpus;
2207 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2208 "reached. Processor %d/0x%x ignored.\n",
2209 max, thiscpu, apicid);
2216 * If SMT is force disabled and the APIC ID belongs to
2217 * a secondary thread, ignore it.
2219 if (apic_id_disabled(apicid)) {
2220 pr_info_once("Ignoring secondary SMT threads\n");
2224 if (apicid == boot_cpu_physical_apicid) {
2226 * x86_bios_cpu_apicid is required to have processors listed
2227 * in same order as logical cpu numbers. Hence the first
2228 * entry is BSP, and so on.
2229 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2234 /* Logical cpuid 0 is reserved for BSP. */
2235 cpuid_to_apicid[0] = apicid;
2237 cpu = allocate_logical_cpuid(apicid);
2247 if (version == 0x0) {
2248 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2253 if (version != boot_cpu_apic_version) {
2254 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2255 boot_cpu_apic_version, cpu, version);
2258 if (apicid > max_physical_apicid)
2259 max_physical_apicid = apicid;
2261 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2262 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2263 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2265 #ifdef CONFIG_X86_32
2266 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2267 apic->x86_32_early_logical_apicid(cpu);
2269 set_cpu_possible(cpu, true);
2270 physid_set(apicid, phys_cpu_present_map);
2271 set_cpu_present(cpu, true);
2277 int hard_smp_processor_id(void)
2279 return read_apic_id();
2282 void default_init_apic_ldr(void)
2286 apic_write(APIC_DFR, APIC_DFR_VALUE);
2287 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2288 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2289 apic_write(APIC_LDR, val);
2292 int default_cpu_mask_to_apicid(const struct cpumask *mask,
2293 struct irq_data *irqdata,
2294 unsigned int *apicid)
2296 unsigned int cpu = cpumask_first(mask);
2298 if (cpu >= nr_cpu_ids)
2300 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2301 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2305 int flat_cpu_mask_to_apicid(const struct cpumask *mask,
2306 struct irq_data *irqdata,
2307 unsigned int *apicid)
2310 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2311 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2315 *apicid = (unsigned int)cpu_mask;
2316 cpumask_bits(effmsk)[0] = cpu_mask;
2321 * Override the generic EOI implementation with an optimized version.
2322 * Only called during early boot when only one CPU is active and with
2323 * interrupts disabled, so we know this does not race with actual APIC driver
2326 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2330 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2331 /* Should happen once for each apic */
2332 WARN_ON((*drv)->eoi_write == eoi_write);
2333 (*drv)->native_eoi_write = (*drv)->eoi_write;
2334 (*drv)->eoi_write = eoi_write;
2338 static void __init apic_bsp_up_setup(void)
2340 #ifdef CONFIG_X86_64
2341 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2344 * Hack: In case of kdump, after a crash, kernel might be booting
2345 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2346 * might be zero if read from MP tables. Get it from LAPIC.
2348 # ifdef CONFIG_CRASH_DUMP
2349 boot_cpu_physical_apicid = read_apic_id();
2352 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2356 * apic_bsp_setup - Setup function for local apic and io-apic
2357 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2360 * apic_id of BSP APIC
2362 int __init apic_bsp_setup(bool upmode)
2368 apic_bsp_up_setup();
2372 id = apic_read(APIC_LDR);
2374 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2377 end_local_APIC_setup();
2378 irq_remap_enable_fault_handling();
2380 /* Setup local timer */
2381 x86_init.timers.setup_percpu_clockev();
2386 * This initializes the IO-APIC and APIC hardware if this is
2389 int __init APIC_init_uniprocessor(void)
2392 pr_info("Apic disabled\n");
2395 #ifdef CONFIG_X86_64
2396 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2398 pr_info("Apic disabled by BIOS\n");
2402 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2406 * Complain if the BIOS pretends there is one.
2408 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2409 APIC_INTEGRATED(boot_cpu_apic_version)) {
2410 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2411 boot_cpu_physical_apicid);
2416 if (!smp_found_config)
2417 disable_ioapic_support();
2419 default_setup_apic_routing();
2420 apic_bsp_setup(true);
2424 #ifdef CONFIG_UP_LATE_INIT
2425 void __init up_late_init(void)
2427 APIC_init_uniprocessor();
2438 * 'active' is true if the local APIC was enabled by us and
2439 * not the BIOS; this signifies that we are also responsible
2440 * for disabling it before entering apm/acpi suspend
2443 /* r/w apic fields */
2444 unsigned int apic_id;
2445 unsigned int apic_taskpri;
2446 unsigned int apic_ldr;
2447 unsigned int apic_dfr;
2448 unsigned int apic_spiv;
2449 unsigned int apic_lvtt;
2450 unsigned int apic_lvtpc;
2451 unsigned int apic_lvt0;
2452 unsigned int apic_lvt1;
2453 unsigned int apic_lvterr;
2454 unsigned int apic_tmict;
2455 unsigned int apic_tdcr;
2456 unsigned int apic_thmr;
2457 unsigned int apic_cmci;
2460 static int lapic_suspend(void)
2462 unsigned long flags;
2465 if (!apic_pm_state.active)
2468 maxlvt = lapic_get_maxlvt();
2470 apic_pm_state.apic_id = apic_read(APIC_ID);
2471 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2472 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2473 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2474 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2475 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2477 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2478 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2479 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2480 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2481 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2482 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2483 #ifdef CONFIG_X86_THERMAL_VECTOR
2485 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2487 #ifdef CONFIG_X86_MCE_INTEL
2489 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2492 local_irq_save(flags);
2493 disable_local_APIC();
2495 irq_remapping_disable();
2497 local_irq_restore(flags);
2501 static void lapic_resume(void)
2504 unsigned long flags;
2507 if (!apic_pm_state.active)
2510 local_irq_save(flags);
2513 * IO-APIC and PIC have their own resume routines.
2514 * We just mask them here to make sure the interrupt
2515 * subsystem is completely quiet while we enable x2apic
2516 * and interrupt-remapping.
2518 mask_ioapic_entries();
2519 legacy_pic->mask_all();
2525 * Make sure the APICBASE points to the right address
2527 * FIXME! This will be wrong if we ever support suspend on
2528 * SMP! We'll need to do this as part of the CPU restore!
2530 if (boot_cpu_data.x86 >= 6) {
2531 rdmsr(MSR_IA32_APICBASE, l, h);
2532 l &= ~MSR_IA32_APICBASE_BASE;
2533 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2534 wrmsr(MSR_IA32_APICBASE, l, h);
2538 maxlvt = lapic_get_maxlvt();
2539 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2540 apic_write(APIC_ID, apic_pm_state.apic_id);
2541 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2542 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2543 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2544 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2545 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2546 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2547 #ifdef CONFIG_X86_THERMAL_VECTOR
2549 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2551 #ifdef CONFIG_X86_MCE_INTEL
2553 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2556 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2557 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2558 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2559 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2560 apic_write(APIC_ESR, 0);
2561 apic_read(APIC_ESR);
2562 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2563 apic_write(APIC_ESR, 0);
2564 apic_read(APIC_ESR);
2566 irq_remapping_reenable(x2apic_mode);
2568 local_irq_restore(flags);
2572 * This device has no shutdown method - fully functioning local APICs
2573 * are needed on every CPU up until machine_halt/restart/poweroff.
2576 static struct syscore_ops lapic_syscore_ops = {
2577 .resume = lapic_resume,
2578 .suspend = lapic_suspend,
2581 static void apic_pm_activate(void)
2583 apic_pm_state.active = 1;
2586 static int __init init_lapic_sysfs(void)
2588 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2589 if (boot_cpu_has(X86_FEATURE_APIC))
2590 register_syscore_ops(&lapic_syscore_ops);
2595 /* local apic needs to resume before other devices access its registers. */
2596 core_initcall(init_lapic_sysfs);
2598 #else /* CONFIG_PM */
2600 static void apic_pm_activate(void) { }
2602 #endif /* CONFIG_PM */
2604 #ifdef CONFIG_X86_64
2606 static int multi_checked;
2609 static int set_multi(const struct dmi_system_id *d)
2613 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2618 static const struct dmi_system_id multi_dmi_table[] = {
2620 .callback = set_multi,
2621 .ident = "IBM System Summit2",
2623 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2624 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2630 static void dmi_check_multi(void)
2635 dmi_check_system(multi_dmi_table);
2640 * apic_is_clustered_box() -- Check if we can expect good TSC
2642 * Thus far, the major user of this is IBM's Summit2 series:
2643 * Clustered boxes may have unsynced TSC problems if they are
2645 * Use DMI to check them
2647 int apic_is_clustered_box(void)
2655 * APIC command line parameters
2657 static int __init setup_disableapic(char *arg)
2660 setup_clear_cpu_cap(X86_FEATURE_APIC);
2663 early_param("disableapic", setup_disableapic);
2665 /* same as disableapic, for compatibility */
2666 static int __init setup_nolapic(char *arg)
2668 return setup_disableapic(arg);
2670 early_param("nolapic", setup_nolapic);
2672 static int __init parse_lapic_timer_c2_ok(char *arg)
2674 local_apic_timer_c2_ok = 1;
2677 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2679 static int __init parse_disable_apic_timer(char *arg)
2681 disable_apic_timer = 1;
2684 early_param("noapictimer", parse_disable_apic_timer);
2686 static int __init parse_nolapic_timer(char *arg)
2688 disable_apic_timer = 1;
2691 early_param("nolapic_timer", parse_nolapic_timer);
2693 static int __init apic_set_verbosity(char *arg)
2696 #ifdef CONFIG_X86_64
2697 skip_ioapic_setup = 0;
2703 if (strcmp("debug", arg) == 0)
2704 apic_verbosity = APIC_DEBUG;
2705 else if (strcmp("verbose", arg) == 0)
2706 apic_verbosity = APIC_VERBOSE;
2708 pr_warning("APIC Verbosity level %s not recognised"
2709 " use apic=verbose or apic=debug\n", arg);
2715 early_param("apic", apic_set_verbosity);
2717 static int __init lapic_insert_resource(void)
2722 /* Put local APIC into the resource map. */
2723 lapic_resource.start = apic_phys;
2724 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2725 insert_resource(&iomem_resource, &lapic_resource);
2731 * need call insert after e820__reserve_resources()
2732 * that is using request_resource
2734 late_initcall(lapic_insert_resource);
2736 static int __init apic_set_disabled_cpu_apicid(char *arg)
2738 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2743 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2745 static int __init apic_set_extnmi(char *arg)
2750 if (!strncmp("all", arg, 3))
2751 apic_extnmi = APIC_EXTNMI_ALL;
2752 else if (!strncmp("none", arg, 4))
2753 apic_extnmi = APIC_EXTNMI_NONE;
2754 else if (!strncmp("bsp", arg, 3))
2755 apic_extnmi = APIC_EXTNMI_BSP;
2757 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2763 early_param("apic_extnmi", apic_set_extnmi);