2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/perf_event.h>
40 #include <asm/x86_init.h>
41 #include <asm/pgalloc.h>
42 #include <linux/atomic.h>
43 #include <asm/mpspec.h>
44 #include <asm/i8259.h>
45 #include <asm/proto.h>
47 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
58 unsigned int num_processors;
60 unsigned disabled_cpus __cpuinitdata;
62 /* Processor that is doing the boot up */
63 unsigned int boot_cpu_physical_apicid = -1U;
66 * The highest APIC ID seen during enumeration.
68 unsigned int max_physical_apicid;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
79 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
86 * On x86_32, the mapping between cpu and logical apicid may vary
87 * depending on apic in use. The following early percpu variable is
88 * used for the mapping. This is where the behaviors of x86_64 and 32
89 * actually diverge. Let's keep it ugly for now.
91 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
93 /* Local APIC was disabled by the BIOS and enabled by the kernel */
94 static int enabled_via_apicbase;
97 * Handle interrupt mode configuration register (IMCR).
98 * This register controls whether the interrupt signals
99 * that reach the BSP come from the master PIC or from the
100 * local APIC. Before entering Symmetric I/O Mode, either
101 * the BIOS or the operating system must switch out of
102 * PIC Mode by changing the IMCR.
104 static inline void imcr_pic_to_apic(void)
106 /* select IMCR register */
108 /* NMI and 8259 INTR go through APIC */
112 static inline void imcr_apic_to_pic(void)
114 /* select IMCR register */
116 /* NMI and 8259 INTR go directly to BSP */
122 * Knob to control our willingness to enable the local APIC.
126 static int force_enable_local_apic __initdata;
128 * APIC command line parameters
130 static int __init parse_lapic(char *arg)
132 if (config_enabled(CONFIG_X86_32) && !arg)
133 force_enable_local_apic = 1;
134 else if (arg && !strncmp(arg, "notscdeadline", 13))
135 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
138 early_param("lapic", parse_lapic);
141 static int apic_calibrate_pmtmr __initdata;
142 static __init int setup_apicpmtimer(char *s)
144 apic_calibrate_pmtmr = 1;
148 __setup("apicpmtimer", setup_apicpmtimer);
152 #ifdef CONFIG_X86_X2APIC
153 /* x2apic enabled before OS handover */
154 int x2apic_preenabled;
155 static int x2apic_disabled;
157 static __init int setup_nox2apic(char *str)
159 if (x2apic_enabled()) {
160 int apicid = native_apic_msr_read(APIC_ID);
163 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
168 pr_warning("x2apic already enabled. will disable it\n");
170 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
176 early_param("nox2apic", setup_nox2apic);
179 unsigned long mp_lapic_addr;
181 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
182 static int disable_apic_timer __initdata;
183 /* Local APIC timer works in C2 */
184 int local_apic_timer_c2_ok;
185 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
187 int first_system_vector = 0xfe;
190 * Debug level, exported for io_apic.c
192 unsigned int apic_verbosity;
196 /* Have we found an MP table */
197 int smp_found_config;
199 static struct resource lapic_resource = {
200 .name = "Local APIC",
201 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
204 unsigned int lapic_timer_frequency = 0;
206 static void apic_pm_activate(void);
208 static unsigned long apic_phys;
211 * Get the LAPIC version
213 static inline int lapic_get_version(void)
215 return GET_APIC_VERSION(apic_read(APIC_LVR));
219 * Check, if the APIC is integrated or a separate chip
221 static inline int lapic_is_integrated(void)
226 return APIC_INTEGRATED(lapic_get_version());
231 * Check, whether this is a modern or a first generation APIC
233 static int modern_apic(void)
235 /* AMD systems use old APIC versions, so check the CPU */
236 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
237 boot_cpu_data.x86 >= 0xf)
239 return lapic_get_version() >= 0x14;
243 * right after this call apic become NOOP driven
244 * so apic->write/read doesn't do anything
246 static void __init apic_disable(void)
248 pr_info("APIC: switched to apic NOOP\n");
252 void native_apic_wait_icr_idle(void)
254 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
258 u32 native_safe_apic_wait_icr_idle(void)
265 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
268 inc_irq_stat(icr_read_retry_count);
270 } while (timeout++ < 1000);
275 void native_apic_icr_write(u32 low, u32 id)
277 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
278 apic_write(APIC_ICR, low);
281 u64 native_apic_icr_read(void)
285 icr2 = apic_read(APIC_ICR2);
286 icr1 = apic_read(APIC_ICR);
288 return icr1 | ((u64)icr2 << 32);
293 * get_physical_broadcast - Get number of physical broadcast IDs
295 int get_physical_broadcast(void)
297 return modern_apic() ? 0xff : 0xf;
302 * lapic_get_maxlvt - get the maximum number of local vector table entries
304 int lapic_get_maxlvt(void)
308 v = apic_read(APIC_LVR);
310 * - we always have APIC integrated on 64bit mode
311 * - 82489DXs do not report # of LVT entries
313 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
321 #define APIC_DIVISOR 16
322 #define TSC_DIVISOR 32
325 * This function sets up the local APIC timer, with a timeout of
326 * 'clocks' APIC bus clock. During calibration we actually call
327 * this function twice on the boot CPU, once with a bogus timeout
328 * value, second time for real. The other (noncalibrating) CPUs
329 * call this function only once, with the real, calibrated value.
331 * We do reads before writes even if unnecessary, to get around the
332 * P5 APIC double write bug.
334 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
336 unsigned int lvtt_value, tmp_value;
338 lvtt_value = LOCAL_TIMER_VECTOR;
340 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
341 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
342 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
344 if (!lapic_is_integrated())
345 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
348 lvtt_value |= APIC_LVT_MASKED;
350 apic_write(APIC_LVTT, lvtt_value);
352 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
353 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
360 tmp_value = apic_read(APIC_TDCR);
361 apic_write(APIC_TDCR,
362 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 * Setup extended LVT, AMD specific
372 * Software should use the LVT offsets the BIOS provides. The offsets
373 * are determined by the subsystems using it like those for MCE
374 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
375 * are supported. Beginning with family 10h at least 4 offsets are
378 * Since the offsets must be consistent for all cores, we keep track
379 * of the LVT offsets in software and reserve the offset for the same
380 * vector also to be used on other cores. An offset is freed by
381 * setting the entry to APIC_EILVT_MASKED.
383 * If the BIOS is right, there should be no conflicts. Otherwise a
384 * "[Firmware Bug]: ..." error message is generated. However, if
385 * software does not properly determines the offsets, it is not
386 * necessarily a BIOS bug.
389 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
391 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
393 return (old & APIC_EILVT_MASKED)
394 || (new == APIC_EILVT_MASKED)
395 || ((new & ~APIC_EILVT_MASKED) == old);
398 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
400 unsigned int rsvd, vector;
402 if (offset >= APIC_EILVT_NR_MAX)
405 rsvd = atomic_read(&eilvt_offsets[offset]);
407 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
408 if (vector && !eilvt_entry_is_changeable(vector, new))
409 /* may not change if vectors are different */
411 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
412 } while (rsvd != new);
414 rsvd &= ~APIC_EILVT_MASKED;
415 if (rsvd && rsvd != vector)
416 pr_info("LVT offset %d assigned for vector 0x%02x\n",
423 * If mask=1, the LVT entry does not generate interrupts while mask=0
424 * enables the vector. See also the BKDGs. Must be called with
425 * preemption disabled.
428 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
430 unsigned long reg = APIC_EILVTn(offset);
431 unsigned int new, old, reserved;
433 new = (mask << 16) | (msg_type << 8) | vector;
434 old = apic_read(reg);
435 reserved = reserve_eilvt_offset(offset, new);
437 if (reserved != new) {
438 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
439 "vector 0x%x, but the register is already in use for "
440 "vector 0x%x on another cpu\n",
441 smp_processor_id(), reg, offset, new, reserved);
445 if (!eilvt_entry_is_changeable(old, new)) {
446 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
447 "vector 0x%x, but the register is already in use for "
448 "vector 0x%x on this cpu\n",
449 smp_processor_id(), reg, offset, new, old);
453 apic_write(reg, new);
457 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
460 * Program the next event, relative to now
462 static int lapic_next_event(unsigned long delta,
463 struct clock_event_device *evt)
465 apic_write(APIC_TMICT, delta);
469 static int lapic_next_deadline(unsigned long delta,
470 struct clock_event_device *evt)
475 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
480 * Setup the lapic timer in periodic or oneshot mode
482 static void lapic_timer_setup(enum clock_event_mode mode,
483 struct clock_event_device *evt)
488 /* Lapic used as dummy for broadcast ? */
489 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
492 local_irq_save(flags);
495 case CLOCK_EVT_MODE_PERIODIC:
496 case CLOCK_EVT_MODE_ONESHOT:
497 __setup_APIC_LVTT(lapic_timer_frequency,
498 mode != CLOCK_EVT_MODE_PERIODIC, 1);
500 case CLOCK_EVT_MODE_UNUSED:
501 case CLOCK_EVT_MODE_SHUTDOWN:
502 v = apic_read(APIC_LVTT);
503 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
504 apic_write(APIC_LVTT, v);
505 apic_write(APIC_TMICT, 0);
507 case CLOCK_EVT_MODE_RESUME:
508 /* Nothing to do here */
512 local_irq_restore(flags);
516 * Local APIC timer broadcast function
518 static void lapic_timer_broadcast(const struct cpumask *mask)
521 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
527 * The local apic timer can be used for any function which is CPU local.
529 static struct clock_event_device lapic_clockevent = {
531 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
532 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
534 .set_mode = lapic_timer_setup,
535 .set_next_event = lapic_next_event,
536 .broadcast = lapic_timer_broadcast,
540 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
543 * Setup the local APIC timer for this CPU. Copy the initialized values
544 * of the boot CPU and register the clock event in the framework.
546 static void __cpuinit setup_APIC_timer(void)
548 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
550 if (this_cpu_has(X86_FEATURE_ARAT)) {
551 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
552 /* Make LAPIC timer preferrable over percpu HPET */
553 lapic_clockevent.rating = 150;
556 memcpy(levt, &lapic_clockevent, sizeof(*levt));
557 levt->cpumask = cpumask_of(smp_processor_id());
559 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
560 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
561 CLOCK_EVT_FEAT_DUMMY);
562 levt->set_next_event = lapic_next_deadline;
563 clockevents_config_and_register(levt,
564 (tsc_khz / TSC_DIVISOR) * 1000,
567 clockevents_register_device(levt);
571 * In this functions we calibrate APIC bus clocks to the external timer.
573 * We want to do the calibration only once since we want to have local timer
574 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
577 * This was previously done by reading the PIT/HPET and waiting for a wrap
578 * around to find out, that a tick has elapsed. I have a box, where the PIT
579 * readout is broken, so it never gets out of the wait loop again. This was
580 * also reported by others.
582 * Monitoring the jiffies value is inaccurate and the clockevents
583 * infrastructure allows us to do a simple substitution of the interrupt
586 * The calibration routine also uses the pm_timer when possible, as the PIT
587 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
588 * back to normal later in the boot process).
591 #define LAPIC_CAL_LOOPS (HZ/10)
593 static __initdata int lapic_cal_loops = -1;
594 static __initdata long lapic_cal_t1, lapic_cal_t2;
595 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
596 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
597 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
600 * Temporary interrupt handler.
602 static void __init lapic_cal_handler(struct clock_event_device *dev)
604 unsigned long long tsc = 0;
605 long tapic = apic_read(APIC_TMCCT);
606 unsigned long pm = acpi_pm_read_early();
611 switch (lapic_cal_loops++) {
613 lapic_cal_t1 = tapic;
614 lapic_cal_tsc1 = tsc;
616 lapic_cal_j1 = jiffies;
619 case LAPIC_CAL_LOOPS:
620 lapic_cal_t2 = tapic;
621 lapic_cal_tsc2 = tsc;
622 if (pm < lapic_cal_pm1)
623 pm += ACPI_PM_OVRRUN;
625 lapic_cal_j2 = jiffies;
631 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
633 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
634 const long pm_thresh = pm_100ms / 100;
638 #ifndef CONFIG_X86_PM_TIMER
642 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
644 /* Check, if the PM timer is available */
648 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
650 if (deltapm > (pm_100ms - pm_thresh) &&
651 deltapm < (pm_100ms + pm_thresh)) {
652 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
656 res = (((u64)deltapm) * mult) >> 22;
657 do_div(res, 1000000);
658 pr_warning("APIC calibration not consistent "
659 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
661 /* Correct the lapic counter value */
662 res = (((u64)(*delta)) * pm_100ms);
663 do_div(res, deltapm);
664 pr_info("APIC delta adjusted to PM-Timer: "
665 "%lu (%ld)\n", (unsigned long)res, *delta);
668 /* Correct the tsc counter value */
670 res = (((u64)(*deltatsc)) * pm_100ms);
671 do_div(res, deltapm);
672 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
673 "PM-Timer: %lu (%ld)\n",
674 (unsigned long)res, *deltatsc);
675 *deltatsc = (long)res;
681 static int __init calibrate_APIC_clock(void)
683 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
684 void (*real_handler)(struct clock_event_device *dev);
685 unsigned long deltaj;
686 long delta, deltatsc;
687 int pm_referenced = 0;
690 * check if lapic timer has already been calibrated by platform
691 * specific routine, such as tsc calibration code. if so, we just fill
692 * in the clockevent structure and return.
695 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
697 } else if (lapic_timer_frequency) {
698 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
699 lapic_timer_frequency);
700 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
701 TICK_NSEC, lapic_clockevent.shift);
702 lapic_clockevent.max_delta_ns =
703 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
704 lapic_clockevent.min_delta_ns =
705 clockevent_delta2ns(0xF, &lapic_clockevent);
706 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
710 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
711 "calibrating APIC timer ...\n");
715 /* Replace the global interrupt handler */
716 real_handler = global_clock_event->event_handler;
717 global_clock_event->event_handler = lapic_cal_handler;
720 * Setup the APIC counter to maximum. There is no way the lapic
721 * can underflow in the 100ms detection time frame
723 __setup_APIC_LVTT(0xffffffff, 0, 0);
725 /* Let the interrupts run */
728 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
733 /* Restore the real event handler */
734 global_clock_event->event_handler = real_handler;
736 /* Build delta t1-t2 as apic timer counts down */
737 delta = lapic_cal_t1 - lapic_cal_t2;
738 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
740 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
742 /* we trust the PM based calibration if possible */
743 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
746 /* Calculate the scaled math multiplication factor */
747 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
748 lapic_clockevent.shift);
749 lapic_clockevent.max_delta_ns =
750 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
751 lapic_clockevent.min_delta_ns =
752 clockevent_delta2ns(0xF, &lapic_clockevent);
754 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
756 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
757 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
758 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
759 lapic_timer_frequency);
762 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
764 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
765 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
768 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
770 lapic_timer_frequency / (1000000 / HZ),
771 lapic_timer_frequency % (1000000 / HZ));
774 * Do a sanity check on the APIC calibration result
776 if (lapic_timer_frequency < (1000000 / HZ)) {
778 pr_warning("APIC frequency too slow, disabling apic timer\n");
782 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
785 * PM timer calibration failed or not turned on
786 * so lets try APIC timer based calibration
788 if (!pm_referenced) {
789 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
792 * Setup the apic timer manually
794 levt->event_handler = lapic_cal_handler;
795 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
796 lapic_cal_loops = -1;
798 /* Let the interrupts run */
801 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
804 /* Stop the lapic timer */
805 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
808 deltaj = lapic_cal_j2 - lapic_cal_j1;
809 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
811 /* Check, if the jiffies result is consistent */
812 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
813 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
815 levt->features |= CLOCK_EVT_FEAT_DUMMY;
819 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
820 pr_warning("APIC timer disabled due to verification failure\n");
828 * Setup the boot APIC
830 * Calibrate and verify the result.
832 void __init setup_boot_APIC_clock(void)
835 * The local apic timer can be disabled via the kernel
836 * commandline or from the CPU detection code. Register the lapic
837 * timer as a dummy clock event source on SMP systems, so the
838 * broadcast mechanism is used. On UP systems simply ignore it.
840 if (disable_apic_timer) {
841 pr_info("Disabling APIC timer\n");
842 /* No broadcast on UP ! */
843 if (num_possible_cpus() > 1) {
844 lapic_clockevent.mult = 1;
850 if (calibrate_APIC_clock()) {
851 /* No broadcast on UP ! */
852 if (num_possible_cpus() > 1)
858 * If nmi_watchdog is set to IO_APIC, we need the
859 * PIT/HPET going. Otherwise register lapic as a dummy
862 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
864 /* Setup the lapic or request the broadcast */
868 void __cpuinit setup_secondary_APIC_clock(void)
874 * The guts of the apic timer interrupt
876 static void local_apic_timer_interrupt(void)
878 int cpu = smp_processor_id();
879 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
882 * Normally we should not be here till LAPIC has been initialized but
883 * in some cases like kdump, its possible that there is a pending LAPIC
884 * timer interrupt from previous kernel's context and is delivered in
885 * new kernel the moment interrupts are enabled.
887 * Interrupts are enabled early and LAPIC is setup much later, hence
888 * its possible that when we get here evt->event_handler is NULL.
889 * Check for event_handler being NULL and discard the interrupt as
892 if (!evt->event_handler) {
893 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
895 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
900 * the NMI deadlock-detector uses this.
902 inc_irq_stat(apic_timer_irqs);
904 evt->event_handler(evt);
908 * Local APIC timer interrupt. This is the most natural way for doing
909 * local interrupts, but local timer interrupts can be emulated by
910 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
912 * [ if a single-CPU system runs an SMP kernel then we call the local
913 * interrupt as well. Thus we cannot inline the local irq ... ]
915 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
917 struct pt_regs *old_regs = set_irq_regs(regs);
920 * NOTE! We'd better ACK the irq immediately,
921 * because timer handling can be slow.
923 * update_process_times() expects us to have done irq_enter().
924 * Besides, if we don't timer interrupts ignore the global
925 * interrupt lock, which is the WrongThing (tm) to do.
928 local_apic_timer_interrupt();
931 set_irq_regs(old_regs);
934 int setup_profiling_timer(unsigned int multiplier)
940 * Local APIC start and shutdown
944 * clear_local_APIC - shutdown the local APIC
946 * This is called, when a CPU is disabled and before rebooting, so the state of
947 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
948 * leftovers during boot.
950 void clear_local_APIC(void)
955 /* APIC hasn't been mapped yet */
956 if (!x2apic_mode && !apic_phys)
959 maxlvt = lapic_get_maxlvt();
961 * Masking an LVT entry can trigger a local APIC error
962 * if the vector is zero. Mask LVTERR first to prevent this.
965 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
966 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
969 * Careful: we have to set masks only first to deassert
970 * any level-triggered sources.
972 v = apic_read(APIC_LVTT);
973 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
974 v = apic_read(APIC_LVT0);
975 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
976 v = apic_read(APIC_LVT1);
977 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
979 v = apic_read(APIC_LVTPC);
980 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
983 /* lets not touch this if we didn't frob it */
984 #ifdef CONFIG_X86_THERMAL_VECTOR
986 v = apic_read(APIC_LVTTHMR);
987 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
990 #ifdef CONFIG_X86_MCE_INTEL
992 v = apic_read(APIC_LVTCMCI);
993 if (!(v & APIC_LVT_MASKED))
994 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
999 * Clean APIC state for other OSs:
1001 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1002 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1003 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1005 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1007 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1009 /* Integrated APIC (!82489DX) ? */
1010 if (lapic_is_integrated()) {
1012 /* Clear ESR due to Pentium errata 3AP and 11AP */
1013 apic_write(APIC_ESR, 0);
1014 apic_read(APIC_ESR);
1019 * disable_local_APIC - clear and disable the local APIC
1021 void disable_local_APIC(void)
1025 /* APIC hasn't been mapped yet */
1026 if (!x2apic_mode && !apic_phys)
1032 * Disable APIC (implies clearing of registers
1035 value = apic_read(APIC_SPIV);
1036 value &= ~APIC_SPIV_APIC_ENABLED;
1037 apic_write(APIC_SPIV, value);
1039 #ifdef CONFIG_X86_32
1041 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1042 * restore the disabled state.
1044 if (enabled_via_apicbase) {
1047 rdmsr(MSR_IA32_APICBASE, l, h);
1048 l &= ~MSR_IA32_APICBASE_ENABLE;
1049 wrmsr(MSR_IA32_APICBASE, l, h);
1055 * If Linux enabled the LAPIC against the BIOS default disable it down before
1056 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1057 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1058 * for the case where Linux didn't enable the LAPIC.
1060 void lapic_shutdown(void)
1062 unsigned long flags;
1064 if (!cpu_has_apic && !apic_from_smp_config())
1067 local_irq_save(flags);
1069 #ifdef CONFIG_X86_32
1070 if (!enabled_via_apicbase)
1074 disable_local_APIC();
1077 local_irq_restore(flags);
1081 * This is to verify that we're looking at a real local APIC.
1082 * Check these against your board if the CPUs aren't getting
1083 * started for no apparent reason.
1085 int __init verify_local_APIC(void)
1087 unsigned int reg0, reg1;
1090 * The version register is read-only in a real APIC.
1092 reg0 = apic_read(APIC_LVR);
1093 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1094 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1095 reg1 = apic_read(APIC_LVR);
1096 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1099 * The two version reads above should print the same
1100 * numbers. If the second one is different, then we
1101 * poke at a non-APIC.
1107 * Check if the version looks reasonably.
1109 reg1 = GET_APIC_VERSION(reg0);
1110 if (reg1 == 0x00 || reg1 == 0xff)
1112 reg1 = lapic_get_maxlvt();
1113 if (reg1 < 0x02 || reg1 == 0xff)
1117 * The ID register is read/write in a real APIC.
1119 reg0 = apic_read(APIC_ID);
1120 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1121 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1122 reg1 = apic_read(APIC_ID);
1123 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1124 apic_write(APIC_ID, reg0);
1125 if (reg1 != (reg0 ^ apic->apic_id_mask))
1129 * The next two are just to see if we have sane values.
1130 * They're only really relevant if we're in Virtual Wire
1131 * compatibility mode, but most boxes are anymore.
1133 reg0 = apic_read(APIC_LVT0);
1134 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1135 reg1 = apic_read(APIC_LVT1);
1136 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1142 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1144 void __init sync_Arb_IDs(void)
1147 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1150 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1156 apic_wait_icr_idle();
1158 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1159 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1160 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1164 * An initial setup of the virtual wire mode.
1166 void __init init_bsp_APIC(void)
1171 * Don't do the setup now if we have a SMP BIOS as the
1172 * through-I/O-APIC virtual wire mode might be active.
1174 if (smp_found_config || !cpu_has_apic)
1178 * Do not trust the local APIC being empty at bootup.
1185 value = apic_read(APIC_SPIV);
1186 value &= ~APIC_VECTOR_MASK;
1187 value |= APIC_SPIV_APIC_ENABLED;
1189 #ifdef CONFIG_X86_32
1190 /* This bit is reserved on P4/Xeon and should be cleared */
1191 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1192 (boot_cpu_data.x86 == 15))
1193 value &= ~APIC_SPIV_FOCUS_DISABLED;
1196 value |= APIC_SPIV_FOCUS_DISABLED;
1197 value |= SPURIOUS_APIC_VECTOR;
1198 apic_write(APIC_SPIV, value);
1201 * Set up the virtual wire mode.
1203 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1204 value = APIC_DM_NMI;
1205 if (!lapic_is_integrated()) /* 82489DX */
1206 value |= APIC_LVT_LEVEL_TRIGGER;
1207 apic_write(APIC_LVT1, value);
1210 static void __cpuinit lapic_setup_esr(void)
1212 unsigned int oldvalue, value, maxlvt;
1214 if (!lapic_is_integrated()) {
1215 pr_info("No ESR for 82489DX.\n");
1219 if (apic->disable_esr) {
1221 * Something untraceable is creating bad interrupts on
1222 * secondary quads ... for the moment, just leave the
1223 * ESR disabled - we can't do anything useful with the
1224 * errors anyway - mbligh
1226 pr_info("Leaving ESR disabled.\n");
1230 maxlvt = lapic_get_maxlvt();
1231 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1232 apic_write(APIC_ESR, 0);
1233 oldvalue = apic_read(APIC_ESR);
1235 /* enables sending errors */
1236 value = ERROR_APIC_VECTOR;
1237 apic_write(APIC_LVTERR, value);
1240 * spec says clear errors after enabling vector.
1243 apic_write(APIC_ESR, 0);
1244 value = apic_read(APIC_ESR);
1245 if (value != oldvalue)
1246 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1247 "vector: 0x%08x after: 0x%08x\n",
1252 * setup_local_APIC - setup the local APIC
1254 * Used to setup local APIC while initializing BSP or bringin up APs.
1255 * Always called with preemption disabled.
1257 void __cpuinit setup_local_APIC(void)
1259 int cpu = smp_processor_id();
1260 unsigned int value, queued;
1261 int i, j, acked = 0;
1262 unsigned long long tsc = 0, ntsc;
1263 long long max_loops = cpu_khz;
1269 disable_ioapic_support();
1273 #ifdef CONFIG_X86_32
1274 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1275 if (lapic_is_integrated() && apic->disable_esr) {
1276 apic_write(APIC_ESR, 0);
1277 apic_write(APIC_ESR, 0);
1278 apic_write(APIC_ESR, 0);
1279 apic_write(APIC_ESR, 0);
1282 perf_events_lapic_init();
1285 * Double-check whether this APIC is really registered.
1286 * This is meaningless in clustered apic mode, so we skip it.
1288 BUG_ON(!apic->apic_id_registered());
1291 * Intel recommends to set DFR, LDR and TPR before enabling
1292 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1293 * document number 292116). So here it goes...
1295 apic->init_apic_ldr();
1297 #ifdef CONFIG_X86_32
1299 * APIC LDR is initialized. If logical_apicid mapping was
1300 * initialized during get_smp_config(), make sure it matches the
1303 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1304 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1305 /* always use the value from LDR */
1306 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1307 logical_smp_processor_id();
1310 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1311 * node mapping during NUMA init. Now that logical apicid is
1312 * guaranteed to be known, give it another chance. This is already
1313 * a bit too late - percpu allocation has already happened without
1314 * proper NUMA affinity.
1316 if (apic->x86_32_numa_cpu_node)
1317 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1318 apic->x86_32_numa_cpu_node(cpu));
1322 * Set Task Priority to 'accept all'. We never change this
1325 value = apic_read(APIC_TASKPRI);
1326 value &= ~APIC_TPRI_MASK;
1327 apic_write(APIC_TASKPRI, value);
1330 * After a crash, we no longer service the interrupts and a pending
1331 * interrupt from previous kernel might still have ISR bit set.
1333 * Most probably by now CPU has serviced that pending interrupt and
1334 * it might not have done the ack_APIC_irq() because it thought,
1335 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1336 * does not clear the ISR bit and cpu thinks it has already serivced
1337 * the interrupt. Hence a vector might get locked. It was noticed
1338 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1342 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1343 queued |= apic_read(APIC_IRR + i*0x10);
1345 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1346 value = apic_read(APIC_ISR + i*0x10);
1347 for (j = 31; j >= 0; j--) {
1348 if (value & (1<<j)) {
1355 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1362 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1366 } while (queued && max_loops > 0);
1367 WARN_ON(max_loops <= 0);
1370 * Now that we are all set up, enable the APIC
1372 value = apic_read(APIC_SPIV);
1373 value &= ~APIC_VECTOR_MASK;
1377 value |= APIC_SPIV_APIC_ENABLED;
1379 #ifdef CONFIG_X86_32
1381 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1382 * certain networking cards. If high frequency interrupts are
1383 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1384 * entry is masked/unmasked at a high rate as well then sooner or
1385 * later IOAPIC line gets 'stuck', no more interrupts are received
1386 * from the device. If focus CPU is disabled then the hang goes
1389 * [ This bug can be reproduced easily with a level-triggered
1390 * PCI Ne2000 networking cards and PII/PIII processors, dual
1394 * Actually disabling the focus CPU check just makes the hang less
1395 * frequent as it makes the interrupt distributon model be more
1396 * like LRU than MRU (the short-term load is more even across CPUs).
1397 * See also the comment in end_level_ioapic_irq(). --macro
1401 * - enable focus processor (bit==0)
1402 * - 64bit mode always use processor focus
1403 * so no need to set it
1405 value &= ~APIC_SPIV_FOCUS_DISABLED;
1409 * Set spurious IRQ vector
1411 value |= SPURIOUS_APIC_VECTOR;
1412 apic_write(APIC_SPIV, value);
1415 * Set up LVT0, LVT1:
1417 * set up through-local-APIC on the BP's LINT0. This is not
1418 * strictly necessary in pure symmetric-IO mode, but sometimes
1419 * we delegate interrupts to the 8259A.
1422 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1424 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1425 if (!cpu && (pic_mode || !value)) {
1426 value = APIC_DM_EXTINT;
1427 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1429 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1430 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1432 apic_write(APIC_LVT0, value);
1435 * only the BP should see the LINT1 NMI signal, obviously.
1438 value = APIC_DM_NMI;
1440 value = APIC_DM_NMI | APIC_LVT_MASKED;
1441 if (!lapic_is_integrated()) /* 82489DX */
1442 value |= APIC_LVT_LEVEL_TRIGGER;
1443 apic_write(APIC_LVT1, value);
1445 #ifdef CONFIG_X86_MCE_INTEL
1446 /* Recheck CMCI information after local APIC is up on CPU #0 */
1452 void __cpuinit end_local_APIC_setup(void)
1456 #ifdef CONFIG_X86_32
1459 /* Disable the local apic timer */
1460 value = apic_read(APIC_LVTT);
1461 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1462 apic_write(APIC_LVTT, value);
1469 void __init bsp_end_local_APIC_setup(void)
1471 end_local_APIC_setup();
1474 * Now that local APIC setup is completed for BP, configure the fault
1475 * handling for interrupt remapping.
1477 irq_remap_enable_fault_handling();
1481 #ifdef CONFIG_X86_X2APIC
1483 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1485 static inline void __disable_x2apic(u64 msr)
1487 wrmsrl(MSR_IA32_APICBASE,
1488 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1489 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1492 static __init void disable_x2apic(void)
1496 if (!cpu_has_x2apic)
1499 rdmsrl(MSR_IA32_APICBASE, msr);
1500 if (msr & X2APIC_ENABLE) {
1501 u32 x2apic_id = read_apic_id();
1503 if (x2apic_id >= 255)
1504 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1506 pr_info("Disabling x2apic\n");
1507 __disable_x2apic(msr);
1510 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1511 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1514 x2apic_disabled = 1;
1517 register_lapic_address(mp_lapic_addr);
1521 void check_x2apic(void)
1523 if (x2apic_enabled()) {
1524 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1525 x2apic_preenabled = x2apic_mode = 1;
1529 void enable_x2apic(void)
1533 rdmsrl(MSR_IA32_APICBASE, msr);
1534 if (x2apic_disabled) {
1535 __disable_x2apic(msr);
1542 if (!(msr & X2APIC_ENABLE)) {
1543 printk_once(KERN_INFO "Enabling x2apic\n");
1544 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1547 #endif /* CONFIG_X86_X2APIC */
1549 int __init enable_IR(void)
1551 #ifdef CONFIG_IRQ_REMAP
1552 if (!irq_remapping_supported()) {
1553 pr_debug("intr-remapping not supported\n");
1557 if (!x2apic_preenabled && skip_ioapic_setup) {
1558 pr_info("Skipped enabling intr-remap because of skipping "
1563 return irq_remapping_enable();
1568 void __init enable_IR_x2apic(void)
1570 unsigned long flags;
1571 int ret, x2apic_enabled = 0;
1572 int hardware_init_ret;
1574 /* Make sure irq_remap_ops are initialized */
1575 setup_irq_remapping_ops();
1577 hardware_init_ret = irq_remapping_prepare();
1578 if (hardware_init_ret && !x2apic_supported())
1581 ret = save_ioapic_entries();
1583 pr_info("Saving IO-APIC state failed: %d\n", ret);
1587 local_irq_save(flags);
1588 legacy_pic->mask_all();
1589 mask_ioapic_entries();
1591 if (x2apic_preenabled && nox2apic)
1594 if (hardware_init_ret)
1599 if (!x2apic_supported())
1603 /* IR is required if there is APIC ID > 255 even when running
1606 if (max_physical_apicid > 255 ||
1607 !hypervisor_x2apic_available()) {
1608 if (x2apic_preenabled)
1613 * without IR all CPUs can be addressed by IOAPIC/MSI
1614 * only in physical mode
1616 x2apic_force_phys();
1619 if (ret == IRQ_REMAP_XAPIC_MODE) {
1620 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1626 if (x2apic_supported() && !x2apic_mode) {
1629 pr_info("Enabled x2apic\n");
1633 if (ret < 0) /* IR enabling failed */
1634 restore_ioapic_entries();
1635 legacy_pic->restore_mask();
1636 local_irq_restore(flags);
1639 #ifdef CONFIG_X86_64
1641 * Detect and enable local APICs on non-SMP boards.
1642 * Original code written by Keir Fraser.
1643 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1644 * not correctly set up (usually the APIC timer won't work etc.)
1646 static int __init detect_init_APIC(void)
1648 if (!cpu_has_apic) {
1649 pr_info("No local APIC present\n");
1653 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1658 static int __init apic_verify(void)
1663 * The APIC feature bit should now be enabled
1666 features = cpuid_edx(1);
1667 if (!(features & (1 << X86_FEATURE_APIC))) {
1668 pr_warning("Could not enable APIC!\n");
1671 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1672 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1674 /* The BIOS may have set up the APIC at some other address */
1675 if (boot_cpu_data.x86 >= 6) {
1676 rdmsr(MSR_IA32_APICBASE, l, h);
1677 if (l & MSR_IA32_APICBASE_ENABLE)
1678 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1681 pr_info("Found and enabled local APIC!\n");
1685 int __init apic_force_enable(unsigned long addr)
1693 * Some BIOSes disable the local APIC in the APIC_BASE
1694 * MSR. This can only be done in software for Intel P6 or later
1695 * and AMD K7 (Model > 1) or later.
1697 if (boot_cpu_data.x86 >= 6) {
1698 rdmsr(MSR_IA32_APICBASE, l, h);
1699 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1700 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1701 l &= ~MSR_IA32_APICBASE_BASE;
1702 l |= MSR_IA32_APICBASE_ENABLE | addr;
1703 wrmsr(MSR_IA32_APICBASE, l, h);
1704 enabled_via_apicbase = 1;
1707 return apic_verify();
1711 * Detect and initialize APIC
1713 static int __init detect_init_APIC(void)
1715 /* Disabled by kernel option? */
1719 switch (boot_cpu_data.x86_vendor) {
1720 case X86_VENDOR_AMD:
1721 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1722 (boot_cpu_data.x86 >= 15))
1725 case X86_VENDOR_INTEL:
1726 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1727 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1734 if (!cpu_has_apic) {
1736 * Over-ride BIOS and try to enable the local APIC only if
1737 * "lapic" specified.
1739 if (!force_enable_local_apic) {
1740 pr_info("Local APIC disabled by BIOS -- "
1741 "you can enable it with \"lapic\"\n");
1744 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1756 pr_info("No local APIC present or hardware disabled\n");
1762 * init_apic_mappings - initialize APIC mappings
1764 void __init init_apic_mappings(void)
1766 unsigned int new_apicid;
1769 boot_cpu_physical_apicid = read_apic_id();
1773 /* If no local APIC can be found return early */
1774 if (!smp_found_config && detect_init_APIC()) {
1775 /* lets NOP'ify apic operations */
1776 pr_info("APIC: disable apic facility\n");
1779 apic_phys = mp_lapic_addr;
1782 * acpi lapic path already maps that address in
1783 * acpi_register_lapic_address()
1785 if (!acpi_lapic && !smp_found_config)
1786 register_lapic_address(apic_phys);
1790 * Fetch the APIC ID of the BSP in case we have a
1791 * default configuration (or the MP table is broken).
1793 new_apicid = read_apic_id();
1794 if (boot_cpu_physical_apicid != new_apicid) {
1795 boot_cpu_physical_apicid = new_apicid;
1797 * yeah -- we lie about apic_version
1798 * in case if apic was disabled via boot option
1799 * but it's not a problem for SMP compiled kernel
1800 * since smp_sanity_check is prepared for such a case
1801 * and disable smp mode
1803 apic_version[new_apicid] =
1804 GET_APIC_VERSION(apic_read(APIC_LVR));
1808 void __init register_lapic_address(unsigned long address)
1810 mp_lapic_addr = address;
1813 set_fixmap_nocache(FIX_APIC_BASE, address);
1814 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1815 APIC_BASE, mp_lapic_addr);
1817 if (boot_cpu_physical_apicid == -1U) {
1818 boot_cpu_physical_apicid = read_apic_id();
1819 apic_version[boot_cpu_physical_apicid] =
1820 GET_APIC_VERSION(apic_read(APIC_LVR));
1825 * This initializes the IO-APIC and APIC hardware if this is
1828 int apic_version[MAX_LOCAL_APIC];
1830 int __init APIC_init_uniprocessor(void)
1833 pr_info("Apic disabled\n");
1836 #ifdef CONFIG_X86_64
1837 if (!cpu_has_apic) {
1839 pr_info("Apic disabled by BIOS\n");
1843 if (!smp_found_config && !cpu_has_apic)
1847 * Complain if the BIOS pretends there is one.
1849 if (!cpu_has_apic &&
1850 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1851 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1852 boot_cpu_physical_apicid);
1857 default_setup_apic_routing();
1859 verify_local_APIC();
1862 #ifdef CONFIG_X86_64
1863 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1866 * Hack: In case of kdump, after a crash, kernel might be booting
1867 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1868 * might be zero if read from MP tables. Get it from LAPIC.
1870 # ifdef CONFIG_CRASH_DUMP
1871 boot_cpu_physical_apicid = read_apic_id();
1874 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1877 #ifdef CONFIG_X86_IO_APIC
1879 * Now enable IO-APICs, actually call clear_IO_APIC
1880 * We need clear_IO_APIC before enabling error vector
1882 if (!skip_ioapic_setup && nr_ioapics)
1886 bsp_end_local_APIC_setup();
1888 #ifdef CONFIG_X86_IO_APIC
1889 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1896 x86_init.timers.setup_percpu_clockev();
1901 * Local APIC interrupts
1905 * This interrupt should _never_ happen with our APIC/SMP architecture
1907 static inline void __smp_spurious_interrupt(void)
1912 * Check if this really is a spurious interrupt and ACK it
1913 * if it is a vectored one. Just in case...
1914 * Spurious interrupts should not be ACKed.
1916 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1917 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1920 inc_irq_stat(irq_spurious_count);
1922 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1923 pr_info("spurious APIC interrupt on CPU#%d, "
1924 "should never happen.\n", smp_processor_id());
1927 void smp_spurious_interrupt(struct pt_regs *regs)
1930 __smp_spurious_interrupt();
1935 * This interrupt should never happen with our APIC/SMP architecture
1937 static inline void __smp_error_interrupt(struct pt_regs *regs)
1941 static const char * const error_interrupt_reason[] = {
1942 "Send CS error", /* APIC Error Bit 0 */
1943 "Receive CS error", /* APIC Error Bit 1 */
1944 "Send accept error", /* APIC Error Bit 2 */
1945 "Receive accept error", /* APIC Error Bit 3 */
1946 "Redirectable IPI", /* APIC Error Bit 4 */
1947 "Send illegal vector", /* APIC Error Bit 5 */
1948 "Received illegal vector", /* APIC Error Bit 6 */
1949 "Illegal register address", /* APIC Error Bit 7 */
1952 /* First tickle the hardware, only then report what went on. -- REW */
1953 v0 = apic_read(APIC_ESR);
1954 apic_write(APIC_ESR, 0);
1955 v1 = apic_read(APIC_ESR);
1957 atomic_inc(&irq_err_count);
1959 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1960 smp_processor_id(), v0 , v1);
1965 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1970 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1974 void smp_error_interrupt(struct pt_regs *regs)
1977 __smp_error_interrupt(regs);
1982 * connect_bsp_APIC - attach the APIC to the interrupt system
1984 void __init connect_bsp_APIC(void)
1986 #ifdef CONFIG_X86_32
1989 * Do not trust the local APIC being empty at bootup.
1993 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1994 * local APIC to INT and NMI lines.
1996 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1997 "enabling APIC mode.\n");
2001 if (apic->enable_apic_mode)
2002 apic->enable_apic_mode();
2006 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2007 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2009 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2012 void disconnect_bsp_APIC(int virt_wire_setup)
2016 #ifdef CONFIG_X86_32
2019 * Put the board back into PIC mode (has an effect only on
2020 * certain older boards). Note that APIC interrupts, including
2021 * IPIs, won't work beyond this point! The only exception are
2024 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2025 "entering PIC mode.\n");
2031 /* Go back to Virtual Wire compatibility mode */
2033 /* For the spurious interrupt use vector F, and enable it */
2034 value = apic_read(APIC_SPIV);
2035 value &= ~APIC_VECTOR_MASK;
2036 value |= APIC_SPIV_APIC_ENABLED;
2038 apic_write(APIC_SPIV, value);
2040 if (!virt_wire_setup) {
2042 * For LVT0 make it edge triggered, active high,
2043 * external and enabled
2045 value = apic_read(APIC_LVT0);
2046 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2047 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2048 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2049 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2050 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2051 apic_write(APIC_LVT0, value);
2054 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2058 * For LVT1 make it edge triggered, active high,
2061 value = apic_read(APIC_LVT1);
2062 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2063 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2064 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2065 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2066 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2067 apic_write(APIC_LVT1, value);
2070 void __cpuinit generic_processor_info(int apicid, int version)
2072 int cpu, max = nr_cpu_ids;
2073 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2074 phys_cpu_present_map);
2077 * If boot cpu has not been detected yet, then only allow upto
2078 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2080 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2081 apicid != boot_cpu_physical_apicid) {
2082 int thiscpu = max + disabled_cpus - 1;
2085 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2086 " reached. Keeping one slot for boot cpu."
2087 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2093 if (num_processors >= nr_cpu_ids) {
2094 int thiscpu = max + disabled_cpus;
2097 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2098 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2105 if (apicid == boot_cpu_physical_apicid) {
2107 * x86_bios_cpu_apicid is required to have processors listed
2108 * in same order as logical cpu numbers. Hence the first
2109 * entry is BSP, and so on.
2110 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2115 cpu = cpumask_next_zero(-1, cpu_present_mask);
2120 if (version == 0x0) {
2121 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2125 apic_version[apicid] = version;
2127 if (version != apic_version[boot_cpu_physical_apicid]) {
2128 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2129 apic_version[boot_cpu_physical_apicid], cpu, version);
2132 physid_set(apicid, phys_cpu_present_map);
2133 if (apicid > max_physical_apicid)
2134 max_physical_apicid = apicid;
2136 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2137 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2138 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2140 #ifdef CONFIG_X86_32
2141 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2142 apic->x86_32_early_logical_apicid(cpu);
2144 set_cpu_possible(cpu, true);
2145 set_cpu_present(cpu, true);
2148 int hard_smp_processor_id(void)
2150 return read_apic_id();
2153 void default_init_apic_ldr(void)
2157 apic_write(APIC_DFR, APIC_DFR_VALUE);
2158 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2159 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2160 apic_write(APIC_LDR, val);
2163 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2164 const struct cpumask *andmask,
2165 unsigned int *apicid)
2169 for_each_cpu_and(cpu, cpumask, andmask) {
2170 if (cpumask_test_cpu(cpu, cpu_online_mask))
2174 if (likely(cpu < nr_cpu_ids)) {
2175 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2183 * Override the generic EOI implementation with an optimized version.
2184 * Only called during early boot when only one CPU is active and with
2185 * interrupts disabled, so we know this does not race with actual APIC driver
2188 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2192 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2193 /* Should happen once for each apic */
2194 WARN_ON((*drv)->eoi_write == eoi_write);
2195 (*drv)->eoi_write = eoi_write;
2206 * 'active' is true if the local APIC was enabled by us and
2207 * not the BIOS; this signifies that we are also responsible
2208 * for disabling it before entering apm/acpi suspend
2211 /* r/w apic fields */
2212 unsigned int apic_id;
2213 unsigned int apic_taskpri;
2214 unsigned int apic_ldr;
2215 unsigned int apic_dfr;
2216 unsigned int apic_spiv;
2217 unsigned int apic_lvtt;
2218 unsigned int apic_lvtpc;
2219 unsigned int apic_lvt0;
2220 unsigned int apic_lvt1;
2221 unsigned int apic_lvterr;
2222 unsigned int apic_tmict;
2223 unsigned int apic_tdcr;
2224 unsigned int apic_thmr;
2227 static int lapic_suspend(void)
2229 unsigned long flags;
2232 if (!apic_pm_state.active)
2235 maxlvt = lapic_get_maxlvt();
2237 apic_pm_state.apic_id = apic_read(APIC_ID);
2238 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2239 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2240 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2241 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2242 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2244 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2245 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2246 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2247 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2248 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2249 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2250 #ifdef CONFIG_X86_THERMAL_VECTOR
2252 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2255 local_irq_save(flags);
2256 disable_local_APIC();
2258 irq_remapping_disable();
2260 local_irq_restore(flags);
2264 static void lapic_resume(void)
2267 unsigned long flags;
2270 if (!apic_pm_state.active)
2273 local_irq_save(flags);
2276 * IO-APIC and PIC have their own resume routines.
2277 * We just mask them here to make sure the interrupt
2278 * subsystem is completely quiet while we enable x2apic
2279 * and interrupt-remapping.
2281 mask_ioapic_entries();
2282 legacy_pic->mask_all();
2288 * Make sure the APICBASE points to the right address
2290 * FIXME! This will be wrong if we ever support suspend on
2291 * SMP! We'll need to do this as part of the CPU restore!
2293 if (boot_cpu_data.x86 >= 6) {
2294 rdmsr(MSR_IA32_APICBASE, l, h);
2295 l &= ~MSR_IA32_APICBASE_BASE;
2296 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2297 wrmsr(MSR_IA32_APICBASE, l, h);
2301 maxlvt = lapic_get_maxlvt();
2302 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2303 apic_write(APIC_ID, apic_pm_state.apic_id);
2304 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2305 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2306 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2307 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2308 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2309 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2310 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2312 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2315 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2316 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2317 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2318 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2319 apic_write(APIC_ESR, 0);
2320 apic_read(APIC_ESR);
2321 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2322 apic_write(APIC_ESR, 0);
2323 apic_read(APIC_ESR);
2325 irq_remapping_reenable(x2apic_mode);
2327 local_irq_restore(flags);
2331 * This device has no shutdown method - fully functioning local APICs
2332 * are needed on every CPU up until machine_halt/restart/poweroff.
2335 static struct syscore_ops lapic_syscore_ops = {
2336 .resume = lapic_resume,
2337 .suspend = lapic_suspend,
2340 static void __cpuinit apic_pm_activate(void)
2342 apic_pm_state.active = 1;
2345 static int __init init_lapic_sysfs(void)
2347 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2349 register_syscore_ops(&lapic_syscore_ops);
2354 /* local apic needs to resume before other devices access its registers. */
2355 core_initcall(init_lapic_sysfs);
2357 #else /* CONFIG_PM */
2359 static void apic_pm_activate(void) { }
2361 #endif /* CONFIG_PM */
2363 #ifdef CONFIG_X86_64
2365 static int __cpuinit apic_cluster_num(void)
2367 int i, clusters, zeros;
2369 u16 *bios_cpu_apicid;
2370 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2372 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2373 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2375 for (i = 0; i < nr_cpu_ids; i++) {
2376 /* are we being called early in kernel startup? */
2377 if (bios_cpu_apicid) {
2378 id = bios_cpu_apicid[i];
2379 } else if (i < nr_cpu_ids) {
2381 id = per_cpu(x86_bios_cpu_apicid, i);
2387 if (id != BAD_APICID)
2388 __set_bit(APIC_CLUSTERID(id), clustermap);
2391 /* Problem: Partially populated chassis may not have CPUs in some of
2392 * the APIC clusters they have been allocated. Only present CPUs have
2393 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2394 * Since clusters are allocated sequentially, count zeros only if
2395 * they are bounded by ones.
2399 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2400 if (test_bit(i, clustermap)) {
2401 clusters += 1 + zeros;
2410 static int __cpuinitdata multi_checked;
2411 static int __cpuinitdata multi;
2413 static int __cpuinit set_multi(const struct dmi_system_id *d)
2417 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2422 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2424 .callback = set_multi,
2425 .ident = "IBM System Summit2",
2427 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2428 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2434 static void __cpuinit dmi_check_multi(void)
2439 dmi_check_system(multi_dmi_table);
2444 * apic_is_clustered_box() -- Check if we can expect good TSC
2446 * Thus far, the major user of this is IBM's Summit2 series:
2447 * Clustered boxes may have unsynced TSC problems if they are
2449 * Use DMI to check them
2451 __cpuinit int apic_is_clustered_box(void)
2461 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2462 * not guaranteed to be synced between boards
2464 if (apic_cluster_num() > 1)
2472 * APIC command line parameters
2474 static int __init setup_disableapic(char *arg)
2477 setup_clear_cpu_cap(X86_FEATURE_APIC);
2480 early_param("disableapic", setup_disableapic);
2482 /* same as disableapic, for compatibility */
2483 static int __init setup_nolapic(char *arg)
2485 return setup_disableapic(arg);
2487 early_param("nolapic", setup_nolapic);
2489 static int __init parse_lapic_timer_c2_ok(char *arg)
2491 local_apic_timer_c2_ok = 1;
2494 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2496 static int __init parse_disable_apic_timer(char *arg)
2498 disable_apic_timer = 1;
2501 early_param("noapictimer", parse_disable_apic_timer);
2503 static int __init parse_nolapic_timer(char *arg)
2505 disable_apic_timer = 1;
2508 early_param("nolapic_timer", parse_nolapic_timer);
2510 static int __init apic_set_verbosity(char *arg)
2513 #ifdef CONFIG_X86_64
2514 skip_ioapic_setup = 0;
2520 if (strcmp("debug", arg) == 0)
2521 apic_verbosity = APIC_DEBUG;
2522 else if (strcmp("verbose", arg) == 0)
2523 apic_verbosity = APIC_VERBOSE;
2525 pr_warning("APIC Verbosity level %s not recognised"
2526 " use apic=verbose or apic=debug\n", arg);
2532 early_param("apic", apic_set_verbosity);
2534 static int __init lapic_insert_resource(void)
2539 /* Put local APIC into the resource map. */
2540 lapic_resource.start = apic_phys;
2541 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2542 insert_resource(&iomem_resource, &lapic_resource);
2548 * need call insert after e820_reserve_resources()
2549 * that is using request_resource
2551 late_initcall(lapic_insert_resource);