1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
4 #include <linux/module.h>
5 #include <linux/sched.h>
6 #include <linux/perf_event.h>
7 #include <linux/mutex.h>
8 #include <linux/list.h>
9 #include <linux/stringify.h>
10 #include <linux/highmem.h>
12 #include <linux/vmalloc.h>
13 #include <linux/memory.h>
14 #include <linux/stop_machine.h>
15 #include <linux/slab.h>
16 #include <linux/kdebug.h>
17 #include <linux/kprobes.h>
18 #include <linux/mmu_context.h>
19 #include <linux/bsearch.h>
20 #include <linux/sync_core.h>
21 #include <asm/text-patching.h>
22 #include <asm/alternative.h>
23 #include <asm/sections.h>
26 #include <asm/cacheflush.h>
27 #include <asm/tlbflush.h>
30 #include <asm/fixmap.h>
31 #include <asm/paravirt.h>
32 #include <asm/asm-prototypes.h>
34 int __read_mostly alternatives_patched;
36 EXPORT_SYMBOL_GPL(alternatives_patched);
38 #define MAX_PATCH_LEN (255-1)
40 static int __initdata_or_module debug_alternative;
42 static int __init debug_alt(char *str)
44 debug_alternative = 1;
47 __setup("debug-alternative", debug_alt);
49 static int noreplace_smp;
51 static int __init setup_noreplace_smp(char *str)
56 __setup("noreplace-smp", setup_noreplace_smp);
58 #define DPRINTK(fmt, args...) \
60 if (debug_alternative) \
61 printk(KERN_DEBUG pr_fmt(fmt) "\n", ##args); \
64 #define DUMP_BYTES(buf, len, fmt, args...) \
66 if (unlikely(debug_alternative)) { \
72 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
73 for (j = 0; j < (len) - 1; j++) \
74 printk(KERN_CONT "%02hhx ", buf[j]); \
75 printk(KERN_CONT "%02hhx\n", buf[j]); \
79 static const unsigned char x86nops[] =
91 const unsigned char * const x86_nops[ASM_NOP_MAX+1] =
98 x86nops + 1 + 2 + 3 + 4,
99 x86nops + 1 + 2 + 3 + 4 + 5,
100 x86nops + 1 + 2 + 3 + 4 + 5 + 6,
101 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
104 /* Use this to add nops to a buffer, then text_poke the whole buffer. */
105 static void __init_or_module add_nops(void *insns, unsigned int len)
108 unsigned int noplen = len;
109 if (noplen > ASM_NOP_MAX)
110 noplen = ASM_NOP_MAX;
111 memcpy(insns, x86_nops[noplen], noplen);
117 extern s32 __retpoline_sites[], __retpoline_sites_end[];
118 extern s32 __return_sites[], __return_sites_end[];
119 extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[];
120 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
121 extern s32 __smp_locks[], __smp_locks_end[];
122 void text_poke_early(void *addr, const void *opcode, size_t len);
125 * Are we looking at a near JMP with a 1 or 4-byte displacement.
127 static inline bool is_jmp(const u8 opcode)
129 return opcode == 0xeb || opcode == 0xe9;
132 static void __init_or_module
133 recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insn_buff)
135 u8 *next_rip, *tgt_rip;
139 if (a->replacementlen != 5)
142 o_dspl = *(s32 *)(insn_buff + 1);
144 /* next_rip of the replacement JMP */
145 next_rip = repl_insn + a->replacementlen;
146 /* target rip of the replacement JMP */
147 tgt_rip = next_rip + o_dspl;
148 n_dspl = tgt_rip - orig_insn;
150 DPRINTK("target RIP: %px, new_displ: 0x%x", tgt_rip, n_dspl);
152 if (tgt_rip - orig_insn >= 0) {
153 if (n_dspl - 2 <= 127)
157 /* negative offset */
159 if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
169 insn_buff[1] = (s8)n_dspl;
170 add_nops(insn_buff + 2, 3);
179 *(s32 *)&insn_buff[1] = n_dspl;
185 DPRINTK("final displ: 0x%08x, JMP 0x%lx",
186 n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
190 * optimize_nops_range() - Optimize a sequence of single byte NOPs (0x90)
192 * @instr: instruction byte stream
193 * @instrlen: length of the above
194 * @off: offset within @instr where the first NOP has been detected
196 * Return: number of NOPs found (and replaced).
198 static __always_inline int optimize_nops_range(u8 *instr, u8 instrlen, int off)
203 while (i < instrlen) {
204 if (instr[i] != 0x90)
215 local_irq_save(flags);
216 add_nops(instr + off, nnops);
217 local_irq_restore(flags);
219 DUMP_BYTES(instr, instrlen, "%px: [%d:%d) optimized NOPs: ", instr, off, i);
225 * "noinline" to cause control flow change and thus invalidate I$ and
226 * cause refetch after modification.
228 static void __init_or_module noinline optimize_nops(u8 *instr, size_t len)
234 * Jump over the non-NOP insns and optimize single-byte NOPs into bigger
238 if (insn_decode_kernel(&insn, &instr[i]))
242 * See if this and any potentially following NOPs can be
245 if (insn.length == 1 && insn.opcode.bytes[0] == 0x90)
246 i += optimize_nops_range(instr, len, i);
256 * Replace instructions with better alternatives for this CPU type. This runs
257 * before SMP is initialized to avoid SMP problems with self modifying code.
258 * This implies that asymmetric systems where APs have less capabilities than
259 * the boot processor are not handled. Tough. Make sure you disable such
262 * Marked "noinline" to cause control flow change and thus insn cache
263 * to refetch changed I$ lines.
265 void __init_or_module noinline apply_alternatives(struct alt_instr *start,
266 struct alt_instr *end)
269 u8 *instr, *replacement;
270 u8 insn_buff[MAX_PATCH_LEN];
272 DPRINTK("alt table %px, -> %px", start, end);
274 * The scan order should be from start to end. A later scanned
275 * alternative code can overwrite previously scanned alternative code.
276 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
279 * So be careful if you want to change the scan order to any other
282 for (a = start; a < end; a++) {
283 int insn_buff_sz = 0;
284 /* Mask away "NOT" flag bit for feature to test. */
285 u16 feature = a->cpuid & ~ALTINSTR_FLAG_INV;
287 instr = (u8 *)&a->instr_offset + a->instr_offset;
288 replacement = (u8 *)&a->repl_offset + a->repl_offset;
289 BUG_ON(a->instrlen > sizeof(insn_buff));
290 BUG_ON(feature >= (NCAPINTS + NBUGINTS) * 32);
294 * - feature is present
295 * - feature not present but ALTINSTR_FLAG_INV is set to mean,
296 * patch if feature is *NOT* present.
298 if (!boot_cpu_has(feature) == !(a->cpuid & ALTINSTR_FLAG_INV))
301 DPRINTK("feat: %s%d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d)",
302 (a->cpuid & ALTINSTR_FLAG_INV) ? "!" : "",
305 instr, instr, a->instrlen,
306 replacement, a->replacementlen);
308 DUMP_BYTES(instr, a->instrlen, "%px: old_insn: ", instr);
309 DUMP_BYTES(replacement, a->replacementlen, "%px: rpl_insn: ", replacement);
311 memcpy(insn_buff, replacement, a->replacementlen);
312 insn_buff_sz = a->replacementlen;
315 * 0xe8 is a relative jump; fix the offset.
317 * Instruction length is checked before the opcode to avoid
318 * accessing uninitialized bytes for zero-length replacements.
320 if (a->replacementlen == 5 && *insn_buff == 0xe8) {
321 *(s32 *)(insn_buff + 1) += replacement - instr;
322 DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
323 *(s32 *)(insn_buff + 1),
324 (unsigned long)instr + *(s32 *)(insn_buff + 1) + 5);
327 if (a->replacementlen && is_jmp(replacement[0]))
328 recompute_jump(a, instr, replacement, insn_buff);
330 for (; insn_buff_sz < a->instrlen; insn_buff_sz++)
331 insn_buff[insn_buff_sz] = 0x90;
333 DUMP_BYTES(insn_buff, insn_buff_sz, "%px: final_insn: ", instr);
335 text_poke_early(instr, insn_buff, insn_buff_sz);
338 optimize_nops(instr, a->instrlen);
342 static inline bool is_jcc32(struct insn *insn)
344 /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */
345 return insn->opcode.bytes[0] == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80;
348 #if defined(CONFIG_RETPOLINE) && defined(CONFIG_OBJTOOL)
353 static int emit_indirect(int op, int reg, u8 *bytes)
359 case CALL_INSN_OPCODE:
360 modrm = 0x10; /* Reg = 2; CALL r/m */
363 case JMP32_INSN_OPCODE:
364 modrm = 0x20; /* Reg = 4; JMP r/m */
373 bytes[i++] = 0x41; /* REX.B prefix */
377 modrm |= 0xc0; /* Mod = 3 */
380 bytes[i++] = 0xff; /* opcode */
387 * Rewrite the compiler generated retpoline thunk calls.
389 * For spectre_v2=off (!X86_FEATURE_RETPOLINE), rewrite them into immediate
390 * indirect instructions, avoiding the extra indirection.
392 * For example, convert:
394 * CALL __x86_indirect_thunk_\reg
400 * It also tries to inline spectre_v2=retpoline,lfence when size permits.
402 static int patch_retpoline(void *addr, struct insn *insn, u8 *bytes)
404 retpoline_thunk_t *target;
408 target = addr + insn->length + insn->immediate.value;
409 reg = target - __x86_indirect_thunk_array;
411 if (WARN_ON_ONCE(reg & ~0xf))
414 /* If anyone ever does: CALL/JMP *%rsp, we're in deep trouble. */
417 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) &&
418 !cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE))
421 op = insn->opcode.bytes[0];
426 * Jcc.d32 __x86_indirect_thunk_\reg
436 if (is_jcc32(insn)) {
437 cc = insn->opcode.bytes[1] & 0xf;
438 cc ^= 1; /* invert condition */
440 bytes[i++] = 0x70 + cc; /* Jcc.d8 */
441 bytes[i++] = insn->length - 2; /* sizeof(Jcc.d8) == 2 */
443 /* Continue as if: JMP.d32 __x86_indirect_thunk_\reg */
444 op = JMP32_INSN_OPCODE;
448 * For RETPOLINE_LFENCE: prepend the indirect CALL/JMP with an LFENCE.
450 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
453 bytes[i++] = 0xe8; /* LFENCE */
456 ret = emit_indirect(op, reg, bytes + i);
462 * The compiler is supposed to EMIT an INT3 after every unconditional
463 * JMP instruction due to AMD BTC. However, if the compiler is too old
464 * or SLS isn't enabled, we still need an INT3 after indirect JMPs
467 if (op == JMP32_INSN_OPCODE && i < insn->length)
468 bytes[i++] = INT3_INSN_OPCODE;
470 for (; i < insn->length;)
471 bytes[i++] = BYTES_NOP1;
477 * Generated by 'objtool --retpoline'.
479 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end)
483 for (s = start; s < end; s++) {
484 void *addr = (void *)s + *s;
490 ret = insn_decode_kernel(&insn, addr);
491 if (WARN_ON_ONCE(ret < 0))
494 op1 = insn.opcode.bytes[0];
495 op2 = insn.opcode.bytes[1];
498 case CALL_INSN_OPCODE:
499 case JMP32_INSN_OPCODE:
502 case 0x0f: /* escape */
503 if (op2 >= 0x80 && op2 <= 0x8f)
511 DPRINTK("retpoline at: %pS (%px) len: %d to: %pS",
512 addr, addr, insn.length,
513 addr + insn.length + insn.immediate.value);
515 len = patch_retpoline(addr, &insn, bytes);
516 if (len == insn.length) {
517 optimize_nops(bytes, len);
518 DUMP_BYTES(((u8*)addr), len, "%px: orig: ", addr);
519 DUMP_BYTES(((u8*)bytes), len, "%px: repl: ", addr);
520 text_poke_early(addr, bytes, len);
525 #ifdef CONFIG_RETHUNK
527 * Rewrite the compiler generated return thunk tail-calls.
529 * For example, convert:
531 * JMP __x86_return_thunk
537 static int patch_return(void *addr, struct insn *insn, u8 *bytes)
541 if (cpu_feature_enabled(X86_FEATURE_RETHUNK))
544 bytes[i++] = RET_INSN_OPCODE;
546 for (; i < insn->length;)
547 bytes[i++] = INT3_INSN_OPCODE;
552 void __init_or_module noinline apply_returns(s32 *start, s32 *end)
556 for (s = start; s < end; s++) {
557 void *dest = NULL, *addr = (void *)s + *s;
563 ret = insn_decode_kernel(&insn, addr);
564 if (WARN_ON_ONCE(ret < 0))
567 op = insn.opcode.bytes[0];
568 if (op == JMP32_INSN_OPCODE)
569 dest = addr + insn.length + insn.immediate.value;
571 if (__static_call_fixup(addr, op, dest) ||
572 WARN_ONCE(dest != &__x86_return_thunk,
573 "missing return thunk: %pS-%pS: %*ph",
574 addr, dest, 5, addr))
577 DPRINTK("return thunk at: %pS (%px) len: %d to: %pS",
578 addr, addr, insn.length,
579 addr + insn.length + insn.immediate.value);
581 len = patch_return(addr, &insn, bytes);
582 if (len == insn.length) {
583 DUMP_BYTES(((u8*)addr), len, "%px: orig: ", addr);
584 DUMP_BYTES(((u8*)bytes), len, "%px: repl: ", addr);
585 text_poke_early(addr, bytes, len);
590 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { }
591 #endif /* CONFIG_RETHUNK */
593 #else /* !CONFIG_RETPOLINE || !CONFIG_OBJTOOL */
595 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { }
596 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { }
598 #endif /* CONFIG_RETPOLINE && CONFIG_OBJTOOL */
600 #ifdef CONFIG_X86_KERNEL_IBT
603 * Generated by: objtool --ibt
605 void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end)
609 for (s = start; s < end; s++) {
610 u32 endbr, poison = gen_endbr_poison();
611 void *addr = (void *)s + *s;
613 if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr)))
616 if (WARN_ON_ONCE(!is_endbr(endbr)))
619 DPRINTK("ENDBR at: %pS (%px)", addr, addr);
622 * When we have IBT, the lack of ENDBR will trigger #CP
624 DUMP_BYTES(((u8*)addr), 4, "%px: orig: ", addr);
625 DUMP_BYTES(((u8*)&poison), 4, "%px: repl: ", addr);
626 text_poke_early(addr, &poison, 4);
632 void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end) { }
634 #endif /* CONFIG_X86_KERNEL_IBT */
637 static void alternatives_smp_lock(const s32 *start, const s32 *end,
638 u8 *text, u8 *text_end)
642 for (poff = start; poff < end; poff++) {
643 u8 *ptr = (u8 *)poff + *poff;
645 if (!*poff || ptr < text || ptr >= text_end)
647 /* turn DS segment override prefix into lock prefix */
649 text_poke(ptr, ((unsigned char []){0xf0}), 1);
653 static void alternatives_smp_unlock(const s32 *start, const s32 *end,
654 u8 *text, u8 *text_end)
658 for (poff = start; poff < end; poff++) {
659 u8 *ptr = (u8 *)poff + *poff;
661 if (!*poff || ptr < text || ptr >= text_end)
663 /* turn lock prefix into DS segment override prefix */
665 text_poke(ptr, ((unsigned char []){0x3E}), 1);
669 struct smp_alt_module {
670 /* what is this ??? */
674 /* ptrs to lock prefixes */
676 const s32 *locks_end;
678 /* .text segment, needed to avoid patching init code ;) */
682 struct list_head next;
684 static LIST_HEAD(smp_alt_modules);
685 static bool uniproc_patched = false; /* protected by text_mutex */
687 void __init_or_module alternatives_smp_module_add(struct module *mod,
689 void *locks, void *locks_end,
690 void *text, void *text_end)
692 struct smp_alt_module *smp;
694 mutex_lock(&text_mutex);
695 if (!uniproc_patched)
698 if (num_possible_cpus() == 1)
699 /* Don't bother remembering, we'll never have to undo it. */
702 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
704 /* we'll run the (safe but slow) SMP code then ... */
710 smp->locks_end = locks_end;
712 smp->text_end = text_end;
713 DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
714 smp->locks, smp->locks_end,
715 smp->text, smp->text_end, smp->name);
717 list_add_tail(&smp->next, &smp_alt_modules);
719 alternatives_smp_unlock(locks, locks_end, text, text_end);
721 mutex_unlock(&text_mutex);
724 void __init_or_module alternatives_smp_module_del(struct module *mod)
726 struct smp_alt_module *item;
728 mutex_lock(&text_mutex);
729 list_for_each_entry(item, &smp_alt_modules, next) {
730 if (mod != item->mod)
732 list_del(&item->next);
736 mutex_unlock(&text_mutex);
739 void alternatives_enable_smp(void)
741 struct smp_alt_module *mod;
743 /* Why bother if there are no other CPUs? */
744 BUG_ON(num_possible_cpus() == 1);
746 mutex_lock(&text_mutex);
748 if (uniproc_patched) {
749 pr_info("switching to SMP code\n");
750 BUG_ON(num_online_cpus() != 1);
751 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
752 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
753 list_for_each_entry(mod, &smp_alt_modules, next)
754 alternatives_smp_lock(mod->locks, mod->locks_end,
755 mod->text, mod->text_end);
756 uniproc_patched = false;
758 mutex_unlock(&text_mutex);
762 * Return 1 if the address range is reserved for SMP-alternatives.
763 * Must hold text_mutex.
765 int alternatives_text_reserved(void *start, void *end)
767 struct smp_alt_module *mod;
769 u8 *text_start = start;
772 lockdep_assert_held(&text_mutex);
774 list_for_each_entry(mod, &smp_alt_modules, next) {
775 if (mod->text > text_end || mod->text_end < text_start)
777 for (poff = mod->locks; poff < mod->locks_end; poff++) {
778 const u8 *ptr = (const u8 *)poff + *poff;
780 if (text_start <= ptr && text_end > ptr)
787 #endif /* CONFIG_SMP */
789 #ifdef CONFIG_PARAVIRT
790 void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
791 struct paravirt_patch_site *end)
793 struct paravirt_patch_site *p;
794 char insn_buff[MAX_PATCH_LEN];
796 for (p = start; p < end; p++) {
799 BUG_ON(p->len > MAX_PATCH_LEN);
800 /* prep the buffer with the original instructions */
801 memcpy(insn_buff, p->instr, p->len);
802 used = paravirt_patch(p->type, insn_buff, (unsigned long)p->instr, p->len);
804 BUG_ON(used > p->len);
806 /* Pad the rest with nops */
807 add_nops(insn_buff + used, p->len - used);
808 text_poke_early(p->instr, insn_buff, p->len);
811 extern struct paravirt_patch_site __start_parainstructions[],
812 __stop_parainstructions[];
813 #endif /* CONFIG_PARAVIRT */
816 * Self-test for the INT3 based CALL emulation code.
818 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
819 * properly and that there is a stack gap between the INT3 frame and the
820 * previous context. Without this gap doing a virtual PUSH on the interrupted
821 * stack would corrupt the INT3 IRET frame.
823 * See entry_{32,64}.S for more details.
827 * We define the int3_magic() function in assembly to control the calling
828 * convention such that we can 'call' it from assembly.
831 extern void int3_magic(unsigned int *ptr); /* defined in asm */
834 " .pushsection .init.text, \"ax\", @progbits\n"
835 " .type int3_magic, @function\n"
838 " movl $1, (%" _ASM_ARG1 ")\n"
840 " .size int3_magic, .-int3_magic\n"
844 extern void int3_selftest_ip(void); /* defined in asm below */
847 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
849 unsigned long selftest = (unsigned long)&int3_selftest_ip;
850 struct die_args *args = data;
851 struct pt_regs *regs = args->regs;
853 OPTIMIZER_HIDE_VAR(selftest);
855 if (!regs || user_mode(regs))
861 if (regs->ip - INT3_INSN_SIZE != selftest)
864 int3_emulate_call(regs, (unsigned long)&int3_magic);
868 /* Must be noinline to ensure uniqueness of int3_selftest_ip. */
869 static noinline void __init int3_selftest(void)
871 static __initdata struct notifier_block int3_exception_nb = {
872 .notifier_call = int3_exception_notify,
873 .priority = INT_MAX-1, /* last */
875 unsigned int val = 0;
877 BUG_ON(register_die_notifier(&int3_exception_nb));
880 * Basically: int3_magic(&val); but really complicated :-)
882 * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb
883 * notifier above will emulate CALL for us.
885 asm volatile ("int3_selftest_ip:\n\t"
887 " int3; nop; nop; nop; nop\n\t"
888 : ASM_CALL_CONSTRAINT
889 : __ASM_SEL_RAW(a, D) (&val)
894 unregister_die_notifier(&int3_exception_nb);
897 void __init alternative_instructions(void)
902 * The patching is not fully atomic, so try to avoid local
903 * interruptions that might execute the to be patched code.
904 * Other CPUs are not running.
909 * Don't stop machine check exceptions while patching.
910 * MCEs only happen when something got corrupted and in this
911 * case we must do something about the corruption.
912 * Ignoring it is worse than an unlikely patching race.
913 * Also machine checks tend to be broadcast and if one CPU
914 * goes into machine check the others follow quickly, so we don't
915 * expect a machine check to cause undue problems during to code
920 * Paravirt patching and alternative patching can be combined to
921 * replace a function call with a short direct code sequence (e.g.
922 * by setting a constant return value instead of doing that in an
923 * external function).
924 * In order to make this work the following sequence is required:
925 * 1. set (artificial) features depending on used paravirt
926 * functions which can later influence alternative patching
927 * 2. apply paravirt patching (generally replacing an indirect
928 * function call with a direct one)
929 * 3. apply alternative patching (e.g. replacing a direct function
930 * call with a custom code sequence)
931 * Doing paravirt patching after alternative patching would clobber
932 * the optimization of the custom code with a function call again.
937 * First patch paravirt functions, such that we overwrite the indirect
938 * call with the direct call.
940 apply_paravirt(__parainstructions, __parainstructions_end);
943 * Rewrite the retpolines, must be done before alternatives since
944 * those can rewrite the retpoline thunks.
946 apply_retpolines(__retpoline_sites, __retpoline_sites_end);
947 apply_returns(__return_sites, __return_sites_end);
950 * Then patch alternatives, such that those paravirt calls that are in
951 * alternatives can be overwritten by their immediate fragments.
953 apply_alternatives(__alt_instructions, __alt_instructions_end);
955 apply_ibt_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end);
958 /* Patch to UP if other cpus not imminent. */
959 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
960 uniproc_patched = true;
961 alternatives_smp_module_add(NULL, "core kernel",
962 __smp_locks, __smp_locks_end,
966 if (!uniproc_patched || num_possible_cpus() == 1) {
967 free_init_pages("SMP alternatives",
968 (unsigned long)__smp_locks,
969 (unsigned long)__smp_locks_end);
974 alternatives_patched = 1;
978 * text_poke_early - Update instructions on a live kernel at boot time
979 * @addr: address to modify
980 * @opcode: source of the copy
981 * @len: length to copy
983 * When you use this code to patch more than one byte of an instruction
984 * you need to make sure that other CPUs cannot execute this code in parallel.
985 * Also no thread must be currently preempted in the middle of these
986 * instructions. And on the local CPU you need to be protected against NMI or
987 * MCE handlers seeing an inconsistent instruction while you patch.
989 void __init_or_module text_poke_early(void *addr, const void *opcode,
994 if (boot_cpu_has(X86_FEATURE_NX) &&
995 is_module_text_address((unsigned long)addr)) {
997 * Modules text is marked initially as non-executable, so the
998 * code cannot be running and speculative code-fetches are
999 * prevented. Just change the code.
1001 memcpy(addr, opcode, len);
1003 local_irq_save(flags);
1004 memcpy(addr, opcode, len);
1005 local_irq_restore(flags);
1009 * Could also do a CLFLUSH here to speed up CPU recovery; but
1010 * that causes hangs on some VIA CPUs.
1016 struct mm_struct *mm;
1020 * Using a temporary mm allows to set temporary mappings that are not accessible
1021 * by other CPUs. Such mappings are needed to perform sensitive memory writes
1022 * that override the kernel memory protections (e.g., W^X), without exposing the
1023 * temporary page-table mappings that are required for these write operations to
1024 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the
1025 * mapping is torn down.
1027 * Context: The temporary mm needs to be used exclusively by a single core. To
1028 * harden security IRQs must be disabled while the temporary mm is
1029 * loaded, thereby preventing interrupt handler bugs from overriding
1030 * the kernel memory protection.
1032 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm)
1034 temp_mm_state_t temp_state;
1036 lockdep_assert_irqs_disabled();
1039 * Make sure not to be in TLB lazy mode, as otherwise we'll end up
1040 * with a stale address space WITHOUT being in lazy mode after
1041 * restoring the previous mm.
1043 if (this_cpu_read(cpu_tlbstate_shared.is_lazy))
1044 leave_mm(smp_processor_id());
1046 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1047 switch_mm_irqs_off(NULL, mm, current);
1050 * If breakpoints are enabled, disable them while the temporary mm is
1051 * used. Userspace might set up watchpoints on addresses that are used
1052 * in the temporary mm, which would lead to wrong signals being sent or
1055 * Note that breakpoints are not disabled selectively, which also causes
1056 * kernel breakpoints (e.g., perf's) to be disabled. This might be
1057 * undesirable, but still seems reasonable as the code that runs in the
1058 * temporary mm should be short.
1060 if (hw_breakpoint_active())
1061 hw_breakpoint_disable();
1066 static inline void unuse_temporary_mm(temp_mm_state_t prev_state)
1068 lockdep_assert_irqs_disabled();
1069 switch_mm_irqs_off(NULL, prev_state.mm, current);
1072 * Restore the breakpoints if they were disabled before the temporary mm
1075 if (hw_breakpoint_active())
1076 hw_breakpoint_restore();
1079 __ro_after_init struct mm_struct *poking_mm;
1080 __ro_after_init unsigned long poking_addr;
1082 static void text_poke_memcpy(void *dst, const void *src, size_t len)
1084 memcpy(dst, src, len);
1087 static void text_poke_memset(void *dst, const void *src, size_t len)
1089 int c = *(const int *)src;
1091 memset(dst, c, len);
1094 typedef void text_poke_f(void *dst, const void *src, size_t len);
1096 static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t len)
1098 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
1099 struct page *pages[2] = {NULL};
1100 temp_mm_state_t prev;
1101 unsigned long flags;
1107 * While boot memory allocator is running we cannot use struct pages as
1108 * they are not yet initialized. There is no way to recover.
1110 BUG_ON(!after_bootmem);
1112 if (!core_kernel_text((unsigned long)addr)) {
1113 pages[0] = vmalloc_to_page(addr);
1114 if (cross_page_boundary)
1115 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
1117 pages[0] = virt_to_page(addr);
1118 WARN_ON(!PageReserved(pages[0]));
1119 if (cross_page_boundary)
1120 pages[1] = virt_to_page(addr + PAGE_SIZE);
1123 * If something went wrong, crash and burn since recovery paths are not
1126 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1]));
1129 * Map the page without the global bit, as TLB flushing is done with
1130 * flush_tlb_mm_range(), which is intended for non-global PTEs.
1132 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL);
1135 * The lock is not really needed, but this allows to avoid open-coding.
1137 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
1140 * This must not fail; preallocated in poking_init().
1144 local_irq_save(flags);
1146 pte = mk_pte(pages[0], pgprot);
1147 set_pte_at(poking_mm, poking_addr, ptep, pte);
1149 if (cross_page_boundary) {
1150 pte = mk_pte(pages[1], pgprot);
1151 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
1155 * Loading the temporary mm behaves as a compiler barrier, which
1156 * guarantees that the PTE will be set at the time memcpy() is done.
1158 prev = use_temporary_mm(poking_mm);
1160 kasan_disable_current();
1161 func((u8 *)poking_addr + offset_in_page(addr), src, len);
1162 kasan_enable_current();
1165 * Ensure that the PTE is only cleared after the instructions of memcpy
1166 * were issued by using a compiler barrier.
1170 pte_clear(poking_mm, poking_addr, ptep);
1171 if (cross_page_boundary)
1172 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
1175 * Loading the previous page-table hierarchy requires a serializing
1176 * instruction that already allows the core to see the updated version.
1177 * Xen-PV is assumed to serialize execution in a similar manner.
1179 unuse_temporary_mm(prev);
1182 * Flushing the TLB might involve IPIs, which would require enabled
1183 * IRQs, but not if the mm is not used, as it is in this point.
1185 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr +
1186 (cross_page_boundary ? 2 : 1) * PAGE_SIZE,
1189 if (func == text_poke_memcpy) {
1191 * If the text does not match what we just wrote then something is
1192 * fundamentally screwy; there's nothing we can really do about that.
1194 BUG_ON(memcmp(addr, src, len));
1197 local_irq_restore(flags);
1198 pte_unmap_unlock(ptep, ptl);
1203 * text_poke - Update instructions on a live kernel
1204 * @addr: address to modify
1205 * @opcode: source of the copy
1206 * @len: length to copy
1208 * Only atomic text poke/set should be allowed when not doing early patching.
1209 * It means the size must be writable atomically and the address must be aligned
1210 * in a way that permits an atomic write. It also makes sure we fit on a single
1213 * Note that the caller must ensure that if the modified code is part of a
1214 * module, the module would not be removed during poking. This can be achieved
1215 * by registering a module notifier, and ordering module removal and patching
1218 void *text_poke(void *addr, const void *opcode, size_t len)
1220 lockdep_assert_held(&text_mutex);
1222 return __text_poke(text_poke_memcpy, addr, opcode, len);
1226 * text_poke_kgdb - Update instructions on a live kernel by kgdb
1227 * @addr: address to modify
1228 * @opcode: source of the copy
1229 * @len: length to copy
1231 * Only atomic text poke/set should be allowed when not doing early patching.
1232 * It means the size must be writable atomically and the address must be aligned
1233 * in a way that permits an atomic write. It also makes sure we fit on a single
1236 * Context: should only be used by kgdb, which ensures no other core is running,
1237 * despite the fact it does not hold the text_mutex.
1239 void *text_poke_kgdb(void *addr, const void *opcode, size_t len)
1241 return __text_poke(text_poke_memcpy, addr, opcode, len);
1245 * text_poke_copy - Copy instructions into (an unused part of) RX memory
1246 * @addr: address to modify
1247 * @opcode: source of the copy
1248 * @len: length to copy, could be more than 2x PAGE_SIZE
1250 * Not safe against concurrent execution; useful for JITs to dump
1251 * new code blocks into unused regions of RX memory. Can be used in
1252 * conjunction with synchronize_rcu_tasks() to wait for existing
1253 * execution to quiesce after having made sure no existing functions
1254 * pointers are live.
1256 void *text_poke_copy(void *addr, const void *opcode, size_t len)
1258 unsigned long start = (unsigned long)addr;
1261 if (WARN_ON_ONCE(core_kernel_text(start)))
1264 mutex_lock(&text_mutex);
1265 while (patched < len) {
1266 unsigned long ptr = start + patched;
1269 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
1271 __text_poke(text_poke_memcpy, (void *)ptr, opcode + patched, s);
1274 mutex_unlock(&text_mutex);
1279 * text_poke_set - memset into (an unused part of) RX memory
1280 * @addr: address to modify
1281 * @c: the byte to fill the area with
1282 * @len: length to copy, could be more than 2x PAGE_SIZE
1284 * This is useful to overwrite unused regions of RX memory with illegal
1287 void *text_poke_set(void *addr, int c, size_t len)
1289 unsigned long start = (unsigned long)addr;
1292 if (WARN_ON_ONCE(core_kernel_text(start)))
1295 mutex_lock(&text_mutex);
1296 while (patched < len) {
1297 unsigned long ptr = start + patched;
1300 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
1302 __text_poke(text_poke_memset, (void *)ptr, (void *)&c, s);
1305 mutex_unlock(&text_mutex);
1309 static void do_sync_core(void *info)
1314 void text_poke_sync(void)
1316 on_each_cpu(do_sync_core, NULL, 1);
1320 * NOTE: crazy scheme to allow patching Jcc.d32 but not increase the size of
1321 * this thing. When len == 6 everything is prefixed with 0x0f and we map
1322 * opcode to Jcc.d8, using len to distinguish.
1324 struct text_poke_loc {
1325 /* addr := _stext + rel_addr */
1330 const u8 text[POKE_MAX_OPCODE_SIZE];
1331 /* see text_poke_bp_batch() */
1335 struct bp_patching_desc {
1336 struct text_poke_loc *vec;
1341 static struct bp_patching_desc bp_desc;
1343 static __always_inline
1344 struct bp_patching_desc *try_get_desc(void)
1346 struct bp_patching_desc *desc = &bp_desc;
1348 if (!arch_atomic_inc_not_zero(&desc->refs))
1354 static __always_inline void put_desc(void)
1356 struct bp_patching_desc *desc = &bp_desc;
1358 smp_mb__before_atomic();
1359 arch_atomic_dec(&desc->refs);
1362 static __always_inline void *text_poke_addr(struct text_poke_loc *tp)
1364 return _stext + tp->rel_addr;
1367 static __always_inline int patch_cmp(const void *key, const void *elt)
1369 struct text_poke_loc *tp = (struct text_poke_loc *) elt;
1371 if (key < text_poke_addr(tp))
1373 if (key > text_poke_addr(tp))
1378 noinstr int poke_int3_handler(struct pt_regs *regs)
1380 struct bp_patching_desc *desc;
1381 struct text_poke_loc *tp;
1385 if (user_mode(regs))
1389 * Having observed our INT3 instruction, we now must observe
1390 * bp_desc with non-zero refcount:
1392 * bp_desc.refs = 1 INT3
1394 * write INT3 if (bp_desc.refs != 0)
1398 desc = try_get_desc();
1403 * Discount the INT3. See text_poke_bp_batch().
1405 ip = (void *) regs->ip - INT3_INSN_SIZE;
1408 * Skip the binary search if there is a single member in the vector.
1410 if (unlikely(desc->nr_entries > 1)) {
1411 tp = __inline_bsearch(ip, desc->vec, desc->nr_entries,
1412 sizeof(struct text_poke_loc),
1418 if (text_poke_addr(tp) != ip)
1424 switch (tp->opcode) {
1425 case INT3_INSN_OPCODE:
1427 * Someone poked an explicit INT3, they'll want to handle it,
1432 case RET_INSN_OPCODE:
1433 int3_emulate_ret(regs);
1436 case CALL_INSN_OPCODE:
1437 int3_emulate_call(regs, (long)ip + tp->disp);
1440 case JMP32_INSN_OPCODE:
1441 case JMP8_INSN_OPCODE:
1442 int3_emulate_jmp(regs, (long)ip + tp->disp);
1445 case 0x70 ... 0x7f: /* Jcc */
1446 int3_emulate_jcc(regs, tp->opcode & 0xf, (long)ip, tp->disp);
1460 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc))
1461 static struct text_poke_loc tp_vec[TP_VEC_MAX];
1462 static int tp_vec_nr;
1465 * text_poke_bp_batch() -- update instructions on live kernel on SMP
1466 * @tp: vector of instructions to patch
1467 * @nr_entries: number of entries in the vector
1469 * Modify multi-byte instruction by using int3 breakpoint on SMP.
1470 * We completely avoid stop_machine() here, and achieve the
1471 * synchronization using int3 breakpoint.
1473 * The way it is done:
1474 * - For each entry in the vector:
1475 * - add a int3 trap to the address that will be patched
1477 * - For each entry in the vector:
1478 * - update all but the first byte of the patched range
1480 * - For each entry in the vector:
1481 * - replace the first byte (int3) by the first byte of
1485 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries)
1487 unsigned char int3 = INT3_INSN_OPCODE;
1491 lockdep_assert_held(&text_mutex);
1494 bp_desc.nr_entries = nr_entries;
1497 * Corresponds to the implicit memory barrier in try_get_desc() to
1498 * ensure reading a non-zero refcount provides up to date bp_desc data.
1500 atomic_set_release(&bp_desc.refs, 1);
1503 * Corresponding read barrier in int3 notifier for making sure the
1504 * nr_entries and handler are correctly ordered wrt. patching.
1509 * First step: add a int3 trap to the address that will be patched.
1511 for (i = 0; i < nr_entries; i++) {
1512 tp[i].old = *(u8 *)text_poke_addr(&tp[i]);
1513 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE);
1519 * Second step: update all but the first byte of the patched range.
1521 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1522 u8 old[POKE_MAX_OPCODE_SIZE+1] = { tp[i].old, };
1523 u8 _new[POKE_MAX_OPCODE_SIZE+1];
1524 const u8 *new = tp[i].text;
1525 int len = tp[i].len;
1527 if (len - INT3_INSN_SIZE > 0) {
1528 memcpy(old + INT3_INSN_SIZE,
1529 text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
1530 len - INT3_INSN_SIZE);
1534 memcpy(_new + 1, new, 5);
1538 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
1539 new + INT3_INSN_SIZE,
1540 len - INT3_INSN_SIZE);
1546 * Emit a perf event to record the text poke, primarily to
1547 * support Intel PT decoding which must walk the executable code
1548 * to reconstruct the trace. The flow up to here is:
1551 * - write instruction tail
1552 * At this point the actual control flow will be through the
1553 * INT3 and handler and not hit the old or new instruction.
1554 * Intel PT outputs FUP/TIP packets for the INT3, so the flow
1555 * can still be decoded. Subsequently:
1556 * - emit RECORD_TEXT_POKE with the new instruction
1558 * - write first byte
1560 * So before the text poke event timestamp, the decoder will see
1561 * either the old instruction flow or FUP/TIP of INT3. After the
1562 * text poke event timestamp, the decoder will see either the
1563 * new instruction flow or FUP/TIP of INT3. Thus decoders can
1564 * use the timestamp as the point at which to modify the
1566 * The old instruction is recorded so that the event can be
1567 * processed forwards or backwards.
1569 perf_event_text_poke(text_poke_addr(&tp[i]), old, len, new, len);
1574 * According to Intel, this core syncing is very likely
1575 * not necessary and we'd be safe even without it. But
1576 * better safe than sorry (plus there's not only Intel).
1582 * Third step: replace the first byte (int3) by the first byte of
1585 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1586 u8 byte = tp[i].text[0];
1591 if (byte == INT3_INSN_OPCODE)
1594 text_poke(text_poke_addr(&tp[i]), &byte, INT3_INSN_SIZE);
1602 * Remove and wait for refs to be zero.
1604 if (!atomic_dec_and_test(&bp_desc.refs))
1605 atomic_cond_read_acquire(&bp_desc.refs, !VAL);
1608 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr,
1609 const void *opcode, size_t len, const void *emulate)
1616 memcpy((void *)tp->text, opcode+i, len-i);
1620 ret = insn_decode_kernel(&insn, emulate);
1623 tp->rel_addr = addr - (void *)_stext;
1625 tp->opcode = insn.opcode.bytes[0];
1627 if (is_jcc32(&insn)) {
1629 * Map Jcc.d32 onto Jcc.d8 and use len to distinguish.
1631 tp->opcode = insn.opcode.bytes[1] - 0x10;
1634 switch (tp->opcode) {
1635 case RET_INSN_OPCODE:
1636 case JMP32_INSN_OPCODE:
1637 case JMP8_INSN_OPCODE:
1639 * Control flow instructions without implied execution of the
1640 * next instruction can be padded with INT3.
1642 for (i = insn.length; i < len; i++)
1643 BUG_ON(tp->text[i] != INT3_INSN_OPCODE);
1647 BUG_ON(len != insn.length);
1650 switch (tp->opcode) {
1651 case INT3_INSN_OPCODE:
1652 case RET_INSN_OPCODE:
1655 case CALL_INSN_OPCODE:
1656 case JMP32_INSN_OPCODE:
1657 case JMP8_INSN_OPCODE:
1658 case 0x70 ... 0x7f: /* Jcc */
1659 tp->disp = insn.immediate.value;
1662 default: /* assume NOP */
1664 case 2: /* NOP2 -- emulate as JMP8+0 */
1665 BUG_ON(memcmp(emulate, x86_nops[len], len));
1666 tp->opcode = JMP8_INSN_OPCODE;
1670 case 5: /* NOP5 -- emulate as JMP32+0 */
1671 BUG_ON(memcmp(emulate, x86_nops[len], len));
1672 tp->opcode = JMP32_INSN_OPCODE;
1676 default: /* unknown instruction */
1684 * We hard rely on the tp_vec being ordered; ensure this is so by flushing
1687 static bool tp_order_fail(void *addr)
1689 struct text_poke_loc *tp;
1694 if (!addr) /* force */
1697 tp = &tp_vec[tp_vec_nr - 1];
1698 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr)
1704 static void text_poke_flush(void *addr)
1706 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) {
1707 text_poke_bp_batch(tp_vec, tp_vec_nr);
1712 void text_poke_finish(void)
1714 text_poke_flush(NULL);
1717 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate)
1719 struct text_poke_loc *tp;
1721 if (unlikely(system_state == SYSTEM_BOOTING)) {
1722 text_poke_early(addr, opcode, len);
1726 text_poke_flush(addr);
1728 tp = &tp_vec[tp_vec_nr++];
1729 text_poke_loc_init(tp, addr, opcode, len, emulate);
1733 * text_poke_bp() -- update instructions on live kernel on SMP
1734 * @addr: address to patch
1735 * @opcode: opcode of new instruction
1736 * @len: length to copy
1737 * @emulate: instruction to be emulated
1739 * Update a single instruction with the vector in the stack, avoiding
1740 * dynamically allocated memory. This function should be used when it is
1741 * not possible to allocate memory.
1743 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate)
1745 struct text_poke_loc tp;
1747 if (unlikely(system_state == SYSTEM_BOOTING)) {
1748 text_poke_early(addr, opcode, len);
1752 text_poke_loc_init(&tp, addr, opcode, len, emulate);
1753 text_poke_bp_batch(&tp, 1);