arch/x86/include/asm/uv/uv_mmrs.h

   1
   2 /*
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * SGI UV MMR definitions
   8  *
   9  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  10  */
  11
  12 #ifndef _ASM_X86_UV_UV_MMRS_H
  13 #define _ASM_X86_UV_UV_MMRS_H
  14
  15 #define UV_MMR_ENABLE           (1UL << 63)
  16
  17 /* ========================================================================= */
  18 /*                           UVH_BAU_DATA_CONFIG                             */
  19 /* ========================================================================= */
  20 #define UVH_BAU_DATA_CONFIG 0x61680UL
  21 #define UVH_BAU_DATA_CONFIG_32 0x0438
  22
  23 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
  24 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
  25 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8
  26 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
  27 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
  28 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
  29 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
  30 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
  31 #define UVH_BAU_DATA_CONFIG_P_SHFT 13
  32 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
  33 #define UVH_BAU_DATA_CONFIG_T_SHFT 15
  34 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
  35 #define UVH_BAU_DATA_CONFIG_M_SHFT 16
  36 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
  37 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
  38 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
  39
  40 union uvh_bau_data_config_u {
  41     unsigned long       v;
  42     struct uvh_bau_data_config_s {
  43         unsigned long   vector_  :  8;  /* RW */
  44         unsigned long   dm       :  3;  /* RW */
  45         unsigned long   destmode :  1;  /* RW */
  46         unsigned long   status   :  1;  /* RO */
  47         unsigned long   p        :  1;  /* RO */
  48         unsigned long   rsvd_14  :  1;  /*    */
  49         unsigned long   t        :  1;  /* RO */
  50         unsigned long   m        :  1;  /* RW */
  51         unsigned long   rsvd_17_31: 15;  /*    */
  52         unsigned long   apic_id  : 32;  /* RW */
  53     } s;
  54 };
  55
  56 /* ========================================================================= */
  57 /*                           UVH_EVENT_OCCURRED0                             */
  58 /* ========================================================================= */
  59 #define UVH_EVENT_OCCURRED0 0x70000UL
  60 #define UVH_EVENT_OCCURRED0_32 0x005e8
  61
  62 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
  63 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
  64 #define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
  65 #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
  66 #define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
  67 #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
  68 #define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
  69 #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
  70 #define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
  71 #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
  72 #define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
  73 #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
  74 #define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
  75 #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
  76 #define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
  77 #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
  78 #define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
  79 #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
  80 #define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
  81 #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
  82 #define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
  83 #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
  84 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
  85 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
  86 #define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
  87 #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
  88 #define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
  89 #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
  90 #define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
  91 #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
  92 #define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
  93 #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
  94 #define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
  95 #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
  96 #define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
  97 #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
  98 #define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
  99 #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
 100 #define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
 101 #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
 102 #define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
 103 #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
 104 #define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
 105 #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
 106 #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
 107 #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
 108 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
 109 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
 110 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
 111 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
 112 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
 113 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
 114 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
 115 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
 116 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
 117 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
 118 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
 119 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
 120 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
 121 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
 122 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
 123 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
 124 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
 125 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
 126 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
 127 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
 128 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
 129 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
 130 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
 131 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
 132 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
 133 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
 134 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
 135 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
 136 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
 137 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
 138 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
 139 #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
 140 #define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
 141 #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
 142 #define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
 143 #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
 144 #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
 145 #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
 146 #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
 147 #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
 148 #define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
 149 #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
 150 #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
 151 #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
 152 #define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
 153 #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
 154 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
 155 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
 156 #define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
 157 #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
 158 #define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
 159 #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
 160 #define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
 161 #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
 162 #define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
 163 #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
 164 #define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
 165 #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
 166 #define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
 167 #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
 168 #define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
 169 #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
 170 #define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
 171 #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
 172 #define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
 173 #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
 174 #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
 175 #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
 176 union uvh_event_occurred0_u {
 177     unsigned long       v;
 178     struct uvh_event_occurred0_s {
 179         unsigned long   lb_hcerr             :  1;  /* RW, W1C */
 180         unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
 181         unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
 182         unsigned long   lh_hcerr             :  1;  /* RW, W1C */
 183         unsigned long   rh_hcerr             :  1;  /* RW, W1C */
 184         unsigned long   xn_hcerr             :  1;  /* RW, W1C */
 185         unsigned long   si_hcerr             :  1;  /* RW, W1C */
 186         unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
 187         unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
 188         unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
 189         unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
 190         unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
 191         unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
 192         unsigned long   si_aoerr0            :  1;  /* RW, W1C */
 193         unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
 194         unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
 195         unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
 196         unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
 197         unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
 198         unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
 199         unsigned long   si_aoerr1            :  1;  /* RW, W1C */
 200         unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
 201         unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
 202         unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
 203         unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
 204         unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
 205         unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
 206         unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
 207         unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
 208         unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
 209         unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
 210         unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
 211         unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
 212         unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
 213         unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
 214         unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
 215         unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
 216         unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
 217         unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
 218         unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
 219         unsigned long   stop_clock           :  1;  /* RW, W1C */
 220         unsigned long   asic_to_l1           :  1;  /* RW, W1C */
 221         unsigned long   l1_to_asic           :  1;  /* RW, W1C */
 222         unsigned long   ltc_int              :  1;  /* RW, W1C */
 223         unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
 224         unsigned long   ipi_int              :  1;  /* RW, W1C */
 225         unsigned long   extio_int0           :  1;  /* RW, W1C */
 226         unsigned long   extio_int1           :  1;  /* RW, W1C */
 227         unsigned long   extio_int2           :  1;  /* RW, W1C */
 228         unsigned long   extio_int3           :  1;  /* RW, W1C */
 229         unsigned long   profile_int          :  1;  /* RW, W1C */
 230         unsigned long   rtc0                 :  1;  /* RW, W1C */
 231         unsigned long   rtc1                 :  1;  /* RW, W1C */
 232         unsigned long   rtc2                 :  1;  /* RW, W1C */
 233         unsigned long   rtc3                 :  1;  /* RW, W1C */
 234         unsigned long   bau_data             :  1;  /* RW, W1C */
 235         unsigned long   power_management_req :  1;  /* RW, W1C */
 236         unsigned long   rsvd_57_63           :  7;  /*    */
 237     } s;
 238 };
 239
 240 /* ========================================================================= */
 241 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 242 /* ========================================================================= */
 243 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
 244 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
 245
 246 /* ========================================================================= */
 247 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 248 /* ========================================================================= */
 249 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
 250
 251 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
 252 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 253 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
 254 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 255 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 256 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 257 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
 258 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 259 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
 260 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 261 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
 262 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 263 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
 264 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 265 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 266 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 267
 268 union uvh_gr0_tlb_int0_config_u {
 269     unsigned long       v;
 270     struct uvh_gr0_tlb_int0_config_s {
 271         unsigned long   vector_  :  8;  /* RW */
 272         unsigned long   dm       :  3;  /* RW */
 273         unsigned long   destmode :  1;  /* RW */
 274         unsigned long   status   :  1;  /* RO */
 275         unsigned long   p        :  1;  /* RO */
 276         unsigned long   rsvd_14  :  1;  /*    */
 277         unsigned long   t        :  1;  /* RO */
 278         unsigned long   m        :  1;  /* RW */
 279         unsigned long   rsvd_17_31: 15;  /*    */
 280         unsigned long   apic_id  : 32;  /* RW */
 281     } s;
 282 };
 283
 284 /* ========================================================================= */
 285 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 286 /* ========================================================================= */
 287 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
 288
 289 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
 290 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 291 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
 292 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 293 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 294 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 295 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
 296 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 297 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
 298 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 299 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
 300 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 301 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
 302 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 303 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 304 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 305
 306 union uvh_gr0_tlb_int1_config_u {
 307     unsigned long       v;
 308     struct uvh_gr0_tlb_int1_config_s {
 309         unsigned long   vector_  :  8;  /* RW */
 310         unsigned long   dm       :  3;  /* RW */
 311         unsigned long   destmode :  1;  /* RW */
 312         unsigned long   status   :  1;  /* RO */
 313         unsigned long   p        :  1;  /* RO */
 314         unsigned long   rsvd_14  :  1;  /*    */
 315         unsigned long   t        :  1;  /* RO */
 316         unsigned long   m        :  1;  /* RW */
 317         unsigned long   rsvd_17_31: 15;  /*    */
 318         unsigned long   apic_id  : 32;  /* RW */
 319     } s;
 320 };
 321
 322 /* ========================================================================= */
 323 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 324 /* ========================================================================= */
 325 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
 326
 327 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
 328 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 329 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
 330 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 331 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 332 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 333 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
 334 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 335 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
 336 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 337 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
 338 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 339 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
 340 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 341 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 342 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 343
 344 union uvh_gr1_tlb_int0_config_u {
 345     unsigned long       v;
 346     struct uvh_gr1_tlb_int0_config_s {
 347         unsigned long   vector_  :  8;  /* RW */
 348         unsigned long   dm       :  3;  /* RW */
 349         unsigned long   destmode :  1;  /* RW */
 350         unsigned long   status   :  1;  /* RO */
 351         unsigned long   p        :  1;  /* RO */
 352         unsigned long   rsvd_14  :  1;  /*    */
 353         unsigned long   t        :  1;  /* RO */
 354         unsigned long   m        :  1;  /* RW */
 355         unsigned long   rsvd_17_31: 15;  /*    */
 356         unsigned long   apic_id  : 32;  /* RW */
 357     } s;
 358 };
 359
 360 /* ========================================================================= */
 361 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 362 /* ========================================================================= */
 363 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
 364
 365 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
 366 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 367 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
 368 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 369 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 370 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 371 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
 372 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 373 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
 374 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 375 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
 376 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 377 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
 378 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 379 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 380 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 381
 382 union uvh_gr1_tlb_int1_config_u {
 383     unsigned long       v;
 384     struct uvh_gr1_tlb_int1_config_s {
 385         unsigned long   vector_  :  8;  /* RW */
 386         unsigned long   dm       :  3;  /* RW */
 387         unsigned long   destmode :  1;  /* RW */
 388         unsigned long   status   :  1;  /* RO */
 389         unsigned long   p        :  1;  /* RO */
 390         unsigned long   rsvd_14  :  1;  /*    */
 391         unsigned long   t        :  1;  /* RO */
 392         unsigned long   m        :  1;  /* RW */
 393         unsigned long   rsvd_17_31: 15;  /*    */
 394         unsigned long   apic_id  : 32;  /* RW */
 395     } s;
 396 };
 397
 398 /* ========================================================================= */
 399 /*                               UVH_INT_CMPB                                */
 400 /* ========================================================================= */
 401 #define UVH_INT_CMPB 0x22080UL
 402
 403 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
 404 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
 405
 406 union uvh_int_cmpb_u {
 407     unsigned long       v;
 408     struct uvh_int_cmpb_s {
 409         unsigned long   real_time_cmpb : 56;  /* RW */
 410         unsigned long   rsvd_56_63     :  8;  /*    */
 411     } s;
 412 };
 413
 414 /* ========================================================================= */
 415 /*                               UVH_INT_CMPC                                */
 416 /* ========================================================================= */
 417 #define UVH_INT_CMPC 0x22100UL
 418
 419 #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
 420 #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
 421
 422 union uvh_int_cmpc_u {
 423     unsigned long       v;
 424     struct uvh_int_cmpc_s {
 425         unsigned long   real_time_cmpc : 56;  /* RW */
 426         unsigned long   rsvd_56_63     :  8;  /*    */
 427     } s;
 428 };
 429
 430 /* ========================================================================= */
 431 /*                               UVH_INT_CMPD                                */
 432 /* ========================================================================= */
 433 #define UVH_INT_CMPD 0x22180UL
 434
 435 #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
 436 #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
 437
 438 union uvh_int_cmpd_u {
 439     unsigned long       v;
 440     struct uvh_int_cmpd_s {
 441         unsigned long   real_time_cmpd : 56;  /* RW */
 442         unsigned long   rsvd_56_63     :  8;  /*    */
 443     } s;
 444 };
 445
 446 /* ========================================================================= */
 447 /*                               UVH_IPI_INT                                 */
 448 /* ========================================================================= */
 449 #define UVH_IPI_INT 0x60500UL
 450 #define UVH_IPI_INT_32 0x0348
 451
 452 #define UVH_IPI_INT_VECTOR_SHFT 0
 453 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
 454 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
 455 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
 456 #define UVH_IPI_INT_DESTMODE_SHFT 11
 457 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
 458 #define UVH_IPI_INT_APIC_ID_SHFT 16
 459 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
 460 #define UVH_IPI_INT_SEND_SHFT 63
 461 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
 462
 463 union uvh_ipi_int_u {
 464     unsigned long       v;
 465     struct uvh_ipi_int_s {
 466         unsigned long   vector_       :  8;  /* RW */
 467         unsigned long   delivery_mode :  3;  /* RW */
 468         unsigned long   destmode      :  1;  /* RW */
 469         unsigned long   rsvd_12_15    :  4;  /*    */
 470         unsigned long   apic_id       : 32;  /* RW */
 471         unsigned long   rsvd_48_62    : 15;  /*    */
 472         unsigned long   send          :  1;  /* WP */
 473     } s;
 474 };
 475
 476 /* ========================================================================= */
 477 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 478 /* ========================================================================= */
 479 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
 480 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
 481
 482 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
 483 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
 484 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
 485 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
 486
 487 union uvh_lb_bau_intd_payload_queue_first_u {
 488     unsigned long       v;
 489     struct uvh_lb_bau_intd_payload_queue_first_s {
 490         unsigned long   rsvd_0_3:  4;  /*    */
 491         unsigned long   address : 39;  /* RW */
 492         unsigned long   rsvd_43_48:  6;  /*    */
 493         unsigned long   node_id : 14;  /* RW */
 494         unsigned long   rsvd_63 :  1;  /*    */
 495     } s;
 496 };
 497
 498 /* ========================================================================= */
 499 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 500 /* ========================================================================= */
 501 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
 502 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
 503
 504 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
 505 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
 506
 507 union uvh_lb_bau_intd_payload_queue_last_u {
 508     unsigned long       v;
 509     struct uvh_lb_bau_intd_payload_queue_last_s {
 510         unsigned long   rsvd_0_3:  4;  /*    */
 511         unsigned long   address : 39;  /* RW */
 512         unsigned long   rsvd_43_63: 21;  /*    */
 513     } s;
 514 };
 515
 516 /* ========================================================================= */
 517 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 518 /* ========================================================================= */
 519 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
 520 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
 521
 522 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
 523 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
 524
 525 union uvh_lb_bau_intd_payload_queue_tail_u {
 526     unsigned long       v;
 527     struct uvh_lb_bau_intd_payload_queue_tail_s {
 528         unsigned long   rsvd_0_3:  4;  /*    */
 529         unsigned long   address : 39;  /* RW */
 530         unsigned long   rsvd_43_63: 21;  /*    */
 531     } s;
 532 };
 533
 534 /* ========================================================================= */
 535 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 536 /* ========================================================================= */
 537 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
 538 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
 539
 540 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 541 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
 542 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
 543 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
 544 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
 545 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
 546 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
 547 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
 548 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
 549 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
 550 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
 551 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
 552 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
 553 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
 554 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
 555 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
 556 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
 557 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
 558 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
 559 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
 560 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
 561 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
 562 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
 563 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
 564 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
 565 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
 566 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
 567 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
 568 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
 569 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 570 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
 571 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
 572 union uvh_lb_bau_intd_software_acknowledge_u {
 573     unsigned long       v;
 574     struct uvh_lb_bau_intd_software_acknowledge_s {
 575         unsigned long   pending_0 :  1;  /* RW, W1C */
 576         unsigned long   pending_1 :  1;  /* RW, W1C */
 577         unsigned long   pending_2 :  1;  /* RW, W1C */
 578         unsigned long   pending_3 :  1;  /* RW, W1C */
 579         unsigned long   pending_4 :  1;  /* RW, W1C */
 580         unsigned long   pending_5 :  1;  /* RW, W1C */
 581         unsigned long   pending_6 :  1;  /* RW, W1C */
 582         unsigned long   pending_7 :  1;  /* RW, W1C */
 583         unsigned long   timeout_0 :  1;  /* RW, W1C */
 584         unsigned long   timeout_1 :  1;  /* RW, W1C */
 585         unsigned long   timeout_2 :  1;  /* RW, W1C */
 586         unsigned long   timeout_3 :  1;  /* RW, W1C */
 587         unsigned long   timeout_4 :  1;  /* RW, W1C */
 588         unsigned long   timeout_5 :  1;  /* RW, W1C */
 589         unsigned long   timeout_6 :  1;  /* RW, W1C */
 590         unsigned long   timeout_7 :  1;  /* RW, W1C */
 591         unsigned long   rsvd_16_63: 48;  /*    */
 592     } s;
 593 };
 594
 595 /* ========================================================================= */
 596 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 597 /* ========================================================================= */
 598 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
 599 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
 600
 601 /* ========================================================================= */
 602 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 603 /* ========================================================================= */
 604 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
 605 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
 606
 607 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
 608 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
 609 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
 610 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
 611 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
 612 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
 613
 614 union uvh_lb_bau_sb_activation_control_u {
 615     unsigned long       v;
 616     struct uvh_lb_bau_sb_activation_control_s {
 617         unsigned long   index :  6;  /* RW */
 618         unsigned long   rsvd_6_61: 56;  /*    */
 619         unsigned long   push  :  1;  /* WP */
 620         unsigned long   init  :  1;  /* WP */
 621     } s;
 622 };
 623
 624 /* ========================================================================= */
 625 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 626 /* ========================================================================= */
 627 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
 628 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
 629
 630 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
 631 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
 632
 633 union uvh_lb_bau_sb_activation_status_0_u {
 634     unsigned long       v;
 635     struct uvh_lb_bau_sb_activation_status_0_s {
 636         unsigned long   status : 64;  /* RW */
 637     } s;
 638 };
 639
 640 /* ========================================================================= */
 641 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 642 /* ========================================================================= */
 643 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
 644 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
 645
 646 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
 647 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
 648
 649 union uvh_lb_bau_sb_activation_status_1_u {
 650     unsigned long       v;
 651     struct uvh_lb_bau_sb_activation_status_1_s {
 652         unsigned long   status : 64;  /* RW */
 653     } s;
 654 };
 655
 656 /* ========================================================================= */
 657 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 658 /* ========================================================================= */
 659 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
 660 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
 661
 662 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 663 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
 664 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
 665 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
 666
 667 union uvh_lb_bau_sb_descriptor_base_u {
 668     unsigned long       v;
 669     struct uvh_lb_bau_sb_descriptor_base_s {
 670         unsigned long   rsvd_0_11    : 12;  /*    */
 671         unsigned long   page_address : 31;  /* RW */
 672         unsigned long   rsvd_43_48   :  6;  /*    */
 673         unsigned long   node_id      : 14;  /* RW */
 674         unsigned long   rsvd_63      :  1;  /*    */
 675     } s;
 676 };
 677
 678 /* ========================================================================= */
 679 /*                      UVH_LB_MCAST_AOERR0_RPT_ENABLE                       */
 680 /* ========================================================================= */
 681 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
 682
 683 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
 684 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
 685 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
 686 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
 687 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
 688 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
 689 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
 690 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
 691 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
 692 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
 693 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
 694 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
 695 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
 696 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
 697 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
 698 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
 699 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
 700 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
 701 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
 702 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
 703 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
 704 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
 705 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
 706 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
 707 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
 708 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
 709 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
 710 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
 711 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
 712 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
 713 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
 714 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
 715 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
 716 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
 717 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
 718 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
 719 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
 720 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
 721 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
 722 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
 723 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
 724 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
 725 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
 726 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
 727 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
 728 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
 729 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
 730 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
 731 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
 732 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
 733 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
 734 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
 735 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
 736 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
 737 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
 738 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
 739 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
 740 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
 741 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
 742 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
 743 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
 744 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
 745 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
 746 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
 747 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
 748 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
 749 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
 750 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
 751 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
 752 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
 753 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
 754 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
 755 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
 756 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
 757 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
 758 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
 759 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
 760 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
 761 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
 762 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
 763 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
 764 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
 765 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
 766 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
 767 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
 768 #define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
 769
 770 union uvh_lb_mcast_aoerr0_rpt_enable_u {
 771     unsigned long       v;
 772     struct uvh_lb_mcast_aoerr0_rpt_enable_s {
 773         unsigned long   mcast_obese_msg                         :  1;  /* RW */
 774         unsigned long   mcast_data_sb_err                       :  1;  /* RW */
 775         unsigned long   mcast_nack_buff_parity                  :  1;  /* RW */
 776         unsigned long   mcast_timeout                           :  1;  /* RW */
 777         unsigned long   mcast_inactive_reply                    :  1;  /* RW */
 778         unsigned long   mcast_upgrade_error                     :  1;  /* RW */
 779         unsigned long   mcast_reg_count_underflow               :  1;  /* RW */
 780         unsigned long   mcast_rep_obese_msg                     :  1;  /* RW */
 781         unsigned long   ucache_req_runt_msg                     :  1;  /* RW */
 782         unsigned long   ucache_req_obese_msg                    :  1;  /* RW */
 783         unsigned long   ucache_req_data_sb_err                  :  1;  /* RW */
 784         unsigned long   ucache_rep_runt_msg                     :  1;  /* RW */
 785         unsigned long   ucache_rep_obese_msg                    :  1;  /* RW */
 786         unsigned long   ucache_rep_data_sb_err                  :  1;  /* RW */
 787         unsigned long   ucache_rep_command_err                  :  1;  /* RW */
 788         unsigned long   ucache_pend_timeout                     :  1;  /* RW */
 789         unsigned long   macc_req_runt_msg                       :  1;  /* RW */
 790         unsigned long   macc_req_obese_msg                      :  1;  /* RW */
 791         unsigned long   macc_req_data_sb_err                    :  1;  /* RW */
 792         unsigned long   macc_rep_runt_msg                       :  1;  /* RW */
 793         unsigned long   macc_rep_obese_msg                      :  1;  /* RW */
 794         unsigned long   macc_rep_data_sb_err                    :  1;  /* RW */
 795         unsigned long   macc_amo_timeout                        :  1;  /* RW */
 796         unsigned long   macc_put_timeout                        :  1;  /* RW */
 797         unsigned long   macc_spurious_event                     :  1;  /* RW */
 798         unsigned long   ioh_destination_table_parity            :  1;  /* RW */
 799         unsigned long   get_had_error_reply                     :  1;  /* RW */
 800         unsigned long   get_timeout                             :  1;  /* RW */
 801         unsigned long   lock_manager_had_error_reply            :  1;  /* RW */
 802         unsigned long   put_had_error_reply                     :  1;  /* RW */
 803         unsigned long   put_timeout                             :  1;  /* RW */
 804         unsigned long   sb_activation_overrun                   :  1;  /* RW */
 805         unsigned long   completed_gb_activation_had_error_reply :  1;  /* RW */
 806         unsigned long   completed_gb_activation_timeout         :  1;  /* RW */
 807         unsigned long   descriptor_buffer_0_parity              :  1;  /* RW */
 808         unsigned long   descriptor_buffer_1_parity              :  1;  /* RW */
 809         unsigned long   socket_destination_table_parity         :  1;  /* RW */
 810         unsigned long   bau_reply_payload_corruption            :  1;  /* RW */
 811         unsigned long   io_port_destination_table_parity        :  1;  /* RW */
 812         unsigned long   intd_soft_ack_timeout                   :  1;  /* RW */
 813         unsigned long   int_rep_obese_msg                       :  1;  /* RW */
 814         unsigned long   int_rep_command_err                     :  1;  /* RW */
 815         unsigned long   int_timeout                             :  1;  /* RW */
 816         unsigned long   rsvd_43_63                              : 21;  /*    */
 817     } s;
 818 };
 819
 820 /* ========================================================================= */
 821 /*                          UVH_LOCAL_INT0_CONFIG                            */
 822 /* ========================================================================= */
 823 #define UVH_LOCAL_INT0_CONFIG 0x61000UL
 824
 825 #define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
 826 #define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 827 #define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
 828 #define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 829 #define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
 830 #define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 831 #define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
 832 #define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 833 #define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
 834 #define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
 835 #define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
 836 #define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
 837 #define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
 838 #define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
 839 #define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
 840 #define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 841
 842 union uvh_local_int0_config_u {
 843     unsigned long       v;
 844     struct uvh_local_int0_config_s {
 845         unsigned long   vector_  :  8;  /* RW */
 846         unsigned long   dm       :  3;  /* RW */
 847         unsigned long   destmode :  1;  /* RW */
 848         unsigned long   status   :  1;  /* RO */
 849         unsigned long   p        :  1;  /* RO */
 850         unsigned long   rsvd_14  :  1;  /*    */
 851         unsigned long   t        :  1;  /* RO */
 852         unsigned long   m        :  1;  /* RW */
 853         unsigned long   rsvd_17_31: 15;  /*    */
 854         unsigned long   apic_id  : 32;  /* RW */
 855     } s;
 856 };
 857
 858 /* ========================================================================= */
 859 /*                          UVH_LOCAL_INT0_ENABLE                            */
 860 /* ========================================================================= */
 861 #define UVH_LOCAL_INT0_ENABLE 0x65000UL
 862
 863 #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
 864 #define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
 865 #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
 866 #define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
 867 #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
 868 #define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
 869 #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
 870 #define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
 871 #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
 872 #define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
 873 #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
 874 #define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
 875 #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
 876 #define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
 877 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
 878 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
 879 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
 880 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
 881 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
 882 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
 883 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
 884 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
 885 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
 886 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
 887 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
 888 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
 889 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
 890 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
 891 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
 892 #define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
 893 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
 894 #define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
 895 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
 896 #define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
 897 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
 898 #define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
 899 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
 900 #define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
 901 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
 902 #define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
 903 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
 904 #define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
 905 #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
 906 #define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
 907 #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
 908 #define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
 909 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
 910 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
 911 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
 912 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
 913 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
 914 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
 915 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
 916 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
 917 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
 918 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
 919 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
 920 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
 921 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
 922 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
 923 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
 924 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
 925 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
 926 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
 927 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
 928 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
 929 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
 930 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
 931 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
 932 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
 933 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
 934 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
 935 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
 936 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
 937 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
 938 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
 939 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
 940 #define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
 941 #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
 942 #define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
 943 #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
 944 #define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
 945 #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
 946 #define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
 947 #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
 948 #define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
 949 #define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
 950 #define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
 951 #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
 952 #define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
 953
 954 union uvh_local_int0_enable_u {
 955     unsigned long       v;
 956     struct uvh_local_int0_enable_s {
 957         unsigned long   lb_hcerr            :  1;  /* RW */
 958         unsigned long   gr0_hcerr           :  1;  /* RW */
 959         unsigned long   gr1_hcerr           :  1;  /* RW */
 960         unsigned long   lh_hcerr            :  1;  /* RW */
 961         unsigned long   rh_hcerr            :  1;  /* RW */
 962         unsigned long   xn_hcerr            :  1;  /* RW */
 963         unsigned long   si_hcerr            :  1;  /* RW */
 964         unsigned long   lb_aoerr0           :  1;  /* RW */
 965         unsigned long   gr0_aoerr0          :  1;  /* RW */
 966         unsigned long   gr1_aoerr0          :  1;  /* RW */
 967         unsigned long   lh_aoerr0           :  1;  /* RW */
 968         unsigned long   rh_aoerr0           :  1;  /* RW */
 969         unsigned long   xn_aoerr0           :  1;  /* RW */
 970         unsigned long   si_aoerr0           :  1;  /* RW */
 971         unsigned long   lb_aoerr1           :  1;  /* RW */
 972         unsigned long   gr0_aoerr1          :  1;  /* RW */
 973         unsigned long   gr1_aoerr1          :  1;  /* RW */
 974         unsigned long   lh_aoerr1           :  1;  /* RW */
 975         unsigned long   rh_aoerr1           :  1;  /* RW */
 976         unsigned long   xn_aoerr1           :  1;  /* RW */
 977         unsigned long   si_aoerr1           :  1;  /* RW */
 978         unsigned long   rh_vpi_int          :  1;  /* RW */
 979         unsigned long   system_shutdown_int :  1;  /* RW */
 980         unsigned long   lb_irq_int_0        :  1;  /* RW */
 981         unsigned long   lb_irq_int_1        :  1;  /* RW */
 982         unsigned long   lb_irq_int_2        :  1;  /* RW */
 983         unsigned long   lb_irq_int_3        :  1;  /* RW */
 984         unsigned long   lb_irq_int_4        :  1;  /* RW */
 985         unsigned long   lb_irq_int_5        :  1;  /* RW */
 986         unsigned long   lb_irq_int_6        :  1;  /* RW */
 987         unsigned long   lb_irq_int_7        :  1;  /* RW */
 988         unsigned long   lb_irq_int_8        :  1;  /* RW */
 989         unsigned long   lb_irq_int_9        :  1;  /* RW */
 990         unsigned long   lb_irq_int_10       :  1;  /* RW */
 991         unsigned long   lb_irq_int_11       :  1;  /* RW */
 992         unsigned long   lb_irq_int_12       :  1;  /* RW */
 993         unsigned long   lb_irq_int_13       :  1;  /* RW */
 994         unsigned long   lb_irq_int_14       :  1;  /* RW */
 995         unsigned long   lb_irq_int_15       :  1;  /* RW */
 996         unsigned long   l1_nmi_int          :  1;  /* RW */
 997         unsigned long   stop_clock          :  1;  /* RW */
 998         unsigned long   asic_to_l1          :  1;  /* RW */
 999         unsigned long   l1_to_asic          :  1;  /* RW */
1000         unsigned long   ltc_int             :  1;  /* RW */
1001         unsigned long   la_seq_trigger      :  1;  /* RW */
1002         unsigned long   rsvd_45_63          : 19;  /*    */
1003     } s;
1004 };
1005
1006 /* ========================================================================= */
1007 /*                               UVH_NODE_ID                                 */
1008 /* ========================================================================= */
1009 #define UVH_NODE_ID 0x0UL
1010
1011 #define UVH_NODE_ID_FORCE1_SHFT 0
1012 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1013 #define UVH_NODE_ID_MANUFACTURER_SHFT 1
1014 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1015 #define UVH_NODE_ID_PART_NUMBER_SHFT 12
1016 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1017 #define UVH_NODE_ID_REVISION_SHFT 28
1018 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1019 #define UVH_NODE_ID_NODE_ID_SHFT 32
1020 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1021 #define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
1022 #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1023 #define UVH_NODE_ID_NI_PORT_SHFT 56
1024 #define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1025
1026 union uvh_node_id_u {
1027     unsigned long       v;
1028     struct uvh_node_id_s {
1029         unsigned long   force1        :  1;  /* RO */
1030         unsigned long   manufacturer  : 11;  /* RO */
1031         unsigned long   part_number   : 16;  /* RO */
1032         unsigned long   revision      :  4;  /* RO */
1033         unsigned long   node_id       : 15;  /* RW */
1034         unsigned long   rsvd_47       :  1;  /*    */
1035         unsigned long   nodes_per_bit :  7;  /* RW */
1036         unsigned long   rsvd_55       :  1;  /*    */
1037         unsigned long   ni_port       :  4;  /* RO */
1038         unsigned long   rsvd_60_63    :  4;  /*    */
1039     } s;
1040 };
1041
1042 /* ========================================================================= */
1043 /*                          UVH_NODE_PRESENT_TABLE                           */
1044 /* ========================================================================= */
1045 #define UVH_NODE_PRESENT_TABLE 0x1400UL
1046 #define UVH_NODE_PRESENT_TABLE_DEPTH 16
1047
1048 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1049 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1050
1051 union uvh_node_present_table_u {
1052     unsigned long       v;
1053     struct uvh_node_present_table_s {
1054         unsigned long   nodes : 64;  /* RW */
1055     } s;
1056 };
1057
1058 /* ========================================================================= */
1059 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
1060 /* ========================================================================= */
1061 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1062
1063 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1064 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1065
1066 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1067     unsigned long       v;
1068     struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1069         unsigned long   rsvd_0_23 : 24;  /*    */
1070         unsigned long   dest_base : 22;  /* RW */
1071         unsigned long   rsvd_46_63: 18;  /*    */
1072     } s;
1073 };
1074
1075 /* ========================================================================= */
1076 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
1077 /* ========================================================================= */
1078 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1079
1080 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1081 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1082
1083 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1084     unsigned long       v;
1085     struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1086         unsigned long   rsvd_0_23 : 24;  /*    */
1087         unsigned long   dest_base : 22;  /* RW */
1088         unsigned long   rsvd_46_63: 18;  /*    */
1089     } s;
1090 };
1091
1092 /* ========================================================================= */
1093 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
1094 /* ========================================================================= */
1095 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1096
1097 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1098 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1099
1100 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1101     unsigned long       v;
1102     struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1103         unsigned long   rsvd_0_23 : 24;  /*    */
1104         unsigned long   dest_base : 22;  /* RW */
1105         unsigned long   rsvd_46_63: 18;  /*    */
1106     } s;
1107 };
1108
1109 /* ========================================================================= */
1110 /*                    UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR                      */
1111 /* ========================================================================= */
1112 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
1113
1114 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1115 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1116 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1117 #define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1118
1119 union uvh_rh_gam_cfg_overlay_config_mmr_u {
1120     unsigned long       v;
1121     struct uvh_rh_gam_cfg_overlay_config_mmr_s {
1122         unsigned long   rsvd_0_25: 26;  /*    */
1123         unsigned long   base   : 20;  /* RW */
1124         unsigned long   rsvd_46_62: 17;  /*    */
1125         unsigned long   enable :  1;  /* RW */
1126     } s;
1127 };
1128
1129 /* ========================================================================= */
1130 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
1131 /* ========================================================================= */
1132 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1133
1134 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1135 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1136 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1137 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1138 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1139 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1140 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1141 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1142
1143 union uvh_rh_gam_gru_overlay_config_mmr_u {
1144     unsigned long       v;
1145     struct uvh_rh_gam_gru_overlay_config_mmr_s {
1146         unsigned long   rsvd_0_27: 28;  /*    */
1147         unsigned long   base   : 18;  /* RW */
1148         unsigned long   rsvd_46_47:  2;  /*    */
1149         unsigned long   gr4    :  1;  /* RW */
1150         unsigned long   rsvd_49_51:  3;  /*    */
1151         unsigned long   n_gru  :  4;  /* RW */
1152         unsigned long   rsvd_56_62:  7;  /*    */
1153         unsigned long   enable :  1;  /* RW */
1154     } s;
1155 };
1156
1157 /* ========================================================================= */
1158 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
1159 /* ========================================================================= */
1160 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1161
1162 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1163 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1164 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1165 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1166 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1167 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1168 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1169 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1170
1171 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1172     unsigned long       v;
1173     struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
1174         unsigned long   rsvd_0_29: 30;  /*    */
1175         unsigned long   base   : 16;  /* RW */
1176         unsigned long   m_io   :  6;  /* RW */
1177         unsigned long   n_io   :  4;  /* RW */
1178         unsigned long   rsvd_56_62:  7;  /*    */
1179         unsigned long   enable :  1;  /* RW */
1180     } s;
1181 };
1182
1183 /* ========================================================================= */
1184 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
1185 /* ========================================================================= */
1186 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1187
1188 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1189 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1190 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1191 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1192 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1193 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1194
1195 union uvh_rh_gam_mmr_overlay_config_mmr_u {
1196     unsigned long       v;
1197     struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1198         unsigned long   rsvd_0_25: 26;  /*    */
1199         unsigned long   base     : 20;  /* RW */
1200         unsigned long   dual_hub :  1;  /* RW */
1201         unsigned long   rsvd_47_62: 16;  /*    */
1202         unsigned long   enable   :  1;  /* RW */
1203     } s;
1204 };
1205
1206 /* ========================================================================= */
1207 /*                                 UVH_RTC                                   */
1208 /* ========================================================================= */
1209 #define UVH_RTC 0x340000UL
1210
1211 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1212 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1213
1214 union uvh_rtc_u {
1215     unsigned long       v;
1216     struct uvh_rtc_s {
1217         unsigned long   real_time_clock : 56;  /* RW */
1218         unsigned long   rsvd_56_63      :  8;  /*    */
1219     } s;
1220 };
1221
1222 /* ========================================================================= */
1223 /*                           UVH_RTC1_INT_CONFIG                             */
1224 /* ========================================================================= */
1225 #define UVH_RTC1_INT_CONFIG 0x615c0UL
1226
1227 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1228 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1229 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1230 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1231 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1232 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1233 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1234 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1235 #define UVH_RTC1_INT_CONFIG_P_SHFT 13
1236 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1237 #define UVH_RTC1_INT_CONFIG_T_SHFT 15
1238 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1239 #define UVH_RTC1_INT_CONFIG_M_SHFT 16
1240 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1241 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1242 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1243
1244 union uvh_rtc1_int_config_u {
1245     unsigned long       v;
1246     struct uvh_rtc1_int_config_s {
1247         unsigned long   vector_  :  8;  /* RW */
1248         unsigned long   dm       :  3;  /* RW */
1249         unsigned long   destmode :  1;  /* RW */
1250         unsigned long   status   :  1;  /* RO */
1251         unsigned long   p        :  1;  /* RO */
1252         unsigned long   rsvd_14  :  1;  /*    */
1253         unsigned long   t        :  1;  /* RO */
1254         unsigned long   m        :  1;  /* RW */
1255         unsigned long   rsvd_17_31: 15;  /*    */
1256         unsigned long   apic_id  : 32;  /* RW */
1257     } s;
1258 };
1259
1260 /* ========================================================================= */
1261 /*                           UVH_RTC2_INT_CONFIG                             */
1262 /* ========================================================================= */
1263 #define UVH_RTC2_INT_CONFIG 0x61600UL
1264
1265 #define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
1266 #define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1267 #define UVH_RTC2_INT_CONFIG_DM_SHFT 8
1268 #define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
1269 #define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
1270 #define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1271 #define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
1272 #define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1273 #define UVH_RTC2_INT_CONFIG_P_SHFT 13
1274 #define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
1275 #define UVH_RTC2_INT_CONFIG_T_SHFT 15
1276 #define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
1277 #define UVH_RTC2_INT_CONFIG_M_SHFT 16
1278 #define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
1279 #define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
1280 #define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1281
1282 union uvh_rtc2_int_config_u {
1283     unsigned long       v;
1284     struct uvh_rtc2_int_config_s {
1285         unsigned long   vector_  :  8;  /* RW */
1286         unsigned long   dm       :  3;  /* RW */
1287         unsigned long   destmode :  1;  /* RW */
1288         unsigned long   status   :  1;  /* RO */
1289         unsigned long   p        :  1;  /* RO */
1290         unsigned long   rsvd_14  :  1;  /*    */
1291         unsigned long   t        :  1;  /* RO */
1292         unsigned long   m        :  1;  /* RW */
1293         unsigned long   rsvd_17_31: 15;  /*    */
1294         unsigned long   apic_id  : 32;  /* RW */
1295     } s;
1296 };
1297
1298 /* ========================================================================= */
1299 /*                           UVH_RTC3_INT_CONFIG                             */
1300 /* ========================================================================= */
1301 #define UVH_RTC3_INT_CONFIG 0x61640UL
1302
1303 #define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
1304 #define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1305 #define UVH_RTC3_INT_CONFIG_DM_SHFT 8
1306 #define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
1307 #define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
1308 #define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1309 #define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
1310 #define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1311 #define UVH_RTC3_INT_CONFIG_P_SHFT 13
1312 #define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
1313 #define UVH_RTC3_INT_CONFIG_T_SHFT 15
1314 #define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
1315 #define UVH_RTC3_INT_CONFIG_M_SHFT 16
1316 #define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
1317 #define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
1318 #define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1319
1320 union uvh_rtc3_int_config_u {
1321     unsigned long       v;
1322     struct uvh_rtc3_int_config_s {
1323         unsigned long   vector_  :  8;  /* RW */
1324         unsigned long   dm       :  3;  /* RW */
1325         unsigned long   destmode :  1;  /* RW */
1326         unsigned long   status   :  1;  /* RO */
1327         unsigned long   p        :  1;  /* RO */
1328         unsigned long   rsvd_14  :  1;  /*    */
1329         unsigned long   t        :  1;  /* RO */
1330         unsigned long   m        :  1;  /* RW */
1331         unsigned long   rsvd_17_31: 15;  /*    */
1332         unsigned long   apic_id  : 32;  /* RW */
1333     } s;
1334 };
1335
1336 /* ========================================================================= */
1337 /*                            UVH_RTC_INC_RATIO                              */
1338 /* ========================================================================= */
1339 #define UVH_RTC_INC_RATIO 0x350000UL
1340
1341 #define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
1342 #define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
1343 #define UVH_RTC_INC_RATIO_RATIO_SHFT 20
1344 #define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
1345
1346 union uvh_rtc_inc_ratio_u {
1347     unsigned long       v;
1348     struct uvh_rtc_inc_ratio_s {
1349         unsigned long   fraction : 20;  /* RW */
1350         unsigned long   ratio    :  3;  /* RW */
1351         unsigned long   rsvd_23_63: 41;  /*    */
1352     } s;
1353 };
1354
1355 /* ========================================================================= */
1356 /*                          UVH_SI_ADDR_MAP_CONFIG                           */
1357 /* ========================================================================= */
1358 #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
1359
1360 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
1361 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
1362 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
1363 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
1364
1365 union uvh_si_addr_map_config_u {
1366     unsigned long       v;
1367     struct uvh_si_addr_map_config_s {
1368         unsigned long   m_skt :  6;  /* RW */
1369         unsigned long   rsvd_6_7:  2;  /*    */
1370         unsigned long   n_skt :  4;  /* RW */
1371         unsigned long   rsvd_12_63: 52;  /*    */
1372     } s;
1373 };
1374
1375 /* ========================================================================= */
1376 /*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */
1377 /* ========================================================================= */
1378 #define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
1379
1380 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
1381 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1382 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1383 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1384 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
1385 #define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1386
1387 union uvh_si_alias0_overlay_config_u {
1388     unsigned long       v;
1389     struct uvh_si_alias0_overlay_config_s {
1390         unsigned long   rsvd_0_23: 24;  /*    */
1391         unsigned long   base    :  8;  /* RW */
1392         unsigned long   rsvd_32_47: 16;  /*    */
1393         unsigned long   m_alias :  5;  /* RW */
1394         unsigned long   rsvd_53_62: 10;  /*    */
1395         unsigned long   enable  :  1;  /* RW */
1396     } s;
1397 };
1398
1399 /* ========================================================================= */
1400 /*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */
1401 /* ========================================================================= */
1402 #define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
1403
1404 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
1405 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1406 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1407 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1408 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
1409 #define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1410
1411 union uvh_si_alias1_overlay_config_u {
1412     unsigned long       v;
1413     struct uvh_si_alias1_overlay_config_s {
1414         unsigned long   rsvd_0_23: 24;  /*    */
1415         unsigned long   base    :  8;  /* RW */
1416         unsigned long   rsvd_32_47: 16;  /*    */
1417         unsigned long   m_alias :  5;  /* RW */
1418         unsigned long   rsvd_53_62: 10;  /*    */
1419         unsigned long   enable  :  1;  /* RW */
1420     } s;
1421 };
1422
1423 /* ========================================================================= */
1424 /*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */
1425 /* ========================================================================= */
1426 #define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
1427
1428 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
1429 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1430 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1431 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1432 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
1433 #define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1434
1435 union uvh_si_alias2_overlay_config_u {
1436     unsigned long       v;
1437     struct uvh_si_alias2_overlay_config_s {
1438         unsigned long   rsvd_0_23: 24;  /*    */
1439         unsigned long   base    :  8;  /* RW */
1440         unsigned long   rsvd_32_47: 16;  /*    */
1441         unsigned long   m_alias :  5;  /* RW */
1442         unsigned long   rsvd_53_62: 10;  /*    */
1443         unsigned long   enable  :  1;  /* RW */
1444     } s;
1445 };
1446
1447
1448 #endif /* _ASM_X86_UV_UV_MMRS_H */