arch/x86/include/asm/uv/uv_mmrs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV MMR definitions
   7  *
   8  * Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef _ASM_X86_UV_UV_MMRS_H
  12 #define _ASM_X86_UV_UV_MMRS_H
  13
  14 /*
  15  * This file contains MMR definitions for both UV1 & UV2 hubs.
  16  *
  17  * In general, MMR addresses and structures are identical on both hubs.
  18  * These MMRs are identified as:
  19  *      #define UVH_xxx         <address>
  20  *      union uvh_xxx {
  21  *              unsigned long       v;
  22  *              struct uvh_int_cmpd_s {
  23  *              } s;
  24  *      };
  25  *
  26  * If the MMR exists on both hub type but has different addresses or
  27  * contents, the MMR definition is similar to:
  28  *      #define UV1H_xxx        <uv1 address>
  29  *      #define UV2H_xxx        <uv2address>
  30  *      #define UVH_xxx         (is_uv1_hub() ? UV1H_xxx : UV2H_xxx)
  31  *      union uvh_xxx {
  32  *              unsigned long       v;
  33  *              struct uv1h_int_cmpd_s {         (Common fields only)
  34  *              } s;
  35  *              struct uv1h_int_cmpd_s {         (Full UV1 definition)
  36  *              } s1;
  37  *              struct uv2h_int_cmpd_s {         (Full UV2 definition)
  38  *              } s2;
  39  *      };
  40  *
  41  * Only essential difference are enumerated. For example, if the address is
  42  * the same for both UV1 & UV2, only a single #define is generated. Likewise,
  43  * if the contents is the same for both hubs, only the "s" structure is
  44  * generated.
  45  *
  46  * If the MMR exists on ONLY 1 type of hub, no generic definition is
  47  * generated:
  48  *      #define UVnH_xxx        <uvn address>
  49  *      union uvnh_xxx {
  50  *              unsigned long       v;
  51  *              struct uvh_int_cmpd_s {
  52  *              } sn;
  53  *      };
  54  */
  55
  56 #define UV_MMR_ENABLE           (1UL << 63)
  57
  58 #define UV1_HUB_PART_NUMBER     0x88a5
  59 #define UV2_HUB_PART_NUMBER     0x8eb8
  60
  61 /* Compat: if this #define is present, UV headers support UV2 */
  62 #define UV2_HUB_IS_SUPPORTED    1
  63
  64 /* KABI compat: if this #define is present, KABI hacks are present */
  65 #define UV2_HUB_KABI_HACKS      1
  66
  67 /* ========================================================================= */
  68 /*                          UVH_BAU_DATA_BROADCAST                           */
  69 /* ========================================================================= */
  70 #define UVH_BAU_DATA_BROADCAST 0x61688UL
  71 #define UVH_BAU_DATA_BROADCAST_32 0x440
  72
  73 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
  74 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
  75
  76 union uvh_bau_data_broadcast_u {
  77     unsigned long       v;
  78     struct uvh_bau_data_broadcast_s {
  79         unsigned long   enable :  1;  /* RW */
  80         unsigned long   rsvd_1_63: 63;  /*    */
  81     } s;
  82 };
  83
  84 /* ========================================================================= */
  85 /*                           UVH_BAU_DATA_CONFIG                             */
  86 /* ========================================================================= */
  87 #define UVH_BAU_DATA_CONFIG 0x61680UL
  88 #define UVH_BAU_DATA_CONFIG_32 0x438
  89
  90 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
  91 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
  92 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8
  93 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
  94 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
  95 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
  96 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
  97 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
  98 #define UVH_BAU_DATA_CONFIG_P_SHFT 13
  99 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
 100 #define UVH_BAU_DATA_CONFIG_T_SHFT 15
 101 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
 102 #define UVH_BAU_DATA_CONFIG_M_SHFT 16
 103 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
 104 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
 105 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 106
 107 union uvh_bau_data_config_u {
 108     unsigned long       v;
 109     struct uvh_bau_data_config_s {
 110         unsigned long   vector_  :  8;  /* RW */
 111         unsigned long   dm       :  3;  /* RW */
 112         unsigned long   destmode :  1;  /* RW */
 113         unsigned long   status   :  1;  /* RO */
 114         unsigned long   p        :  1;  /* RO */
 115         unsigned long   rsvd_14  :  1;  /*    */
 116         unsigned long   t        :  1;  /* RO */
 117         unsigned long   m        :  1;  /* RW */
 118         unsigned long   rsvd_17_31: 15;  /*    */
 119         unsigned long   apic_id  : 32;  /* RW */
 120     } s;
 121 };
 122
 123 /* ========================================================================= */
 124 /*                           UVH_EVENT_OCCURRED0                             */
 125 /* ========================================================================= */
 126 #define UVH_EVENT_OCCURRED0 0x70000UL
 127 #define UVH_EVENT_OCCURRED0_32 0x5e8
 128
 129 #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
 130 #define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
 131 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
 132 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
 133 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
 134 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
 135 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
 136 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
 137 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
 138 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
 139 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
 140 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
 141 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
 142 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
 143 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
 144 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
 145 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
 146 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
 147 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
 148 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
 149 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
 150 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
 151 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
 152 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
 153 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
 154 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
 155 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
 156 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
 157 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
 158 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
 159 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
 160 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
 161 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
 162 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
 163 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
 164 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
 165 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
 166 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
 167 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
 168 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
 169 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
 170 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
 171 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
 172 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
 173 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
 174 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
 175 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
 176 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
 177 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
 178 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
 179 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
 180 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
 181 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
 182 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
 183 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
 184 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
 185 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
 186 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
 187 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
 188 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
 189 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
 190 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
 191 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
 192 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
 193 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
 194 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
 195 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
 196 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
 197 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
 198 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
 199 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
 200 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
 201 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
 202 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
 203 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
 204 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
 205 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
 206 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
 207 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
 208 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
 209 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
 210 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
 211 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
 212 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
 213 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
 214 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
 215 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
 216 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
 217 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
 218 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
 219 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
 220 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
 221 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
 222 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
 223 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
 224 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
 225 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
 226 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
 227 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
 228 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
 229 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
 230 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
 231 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
 232 #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
 233 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
 234 #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
 235 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
 236 #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
 237 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
 238 #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
 239 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
 240 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
 241 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
 242 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
 243
 244 #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
 245 #define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
 246 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
 247 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
 248 #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
 249 #define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
 250 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
 251 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
 252 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
 253 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
 254 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
 255 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
 256 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
 257 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
 258 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
 259 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
 260 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
 261 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
 262 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
 263 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
 264 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
 265 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
 266 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
 267 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
 268 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
 269 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
 270 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
 271 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
 272 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
 273 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
 274 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
 275 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
 276 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
 277 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
 278 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
 279 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
 280 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
 281 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
 282 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
 283 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
 284 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
 285 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
 286 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
 287 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
 288 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
 289 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
 290 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
 291 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
 292 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
 293 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
 294 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
 295 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
 296 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
 297 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
 298 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
 299 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
 300 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
 301 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
 302 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
 303 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
 304 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
 305 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
 306 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
 307 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
 308 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
 309 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
 310 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
 311 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
 312 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
 313 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
 314 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
 315 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
 316 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
 317 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
 318 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
 319 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
 320 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
 321 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
 322 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
 323 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
 324 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
 325 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
 326 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
 327 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
 328 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
 329 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
 330 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
 331 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
 332 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
 333 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
 334 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
 335 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
 336 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
 337 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
 338 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
 339 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
 340 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
 341 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
 342 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
 343 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
 344 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
 345 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
 346 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
 347 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
 348 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
 349 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
 350 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
 351 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
 352 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
 353 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
 354 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
 355 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
 356 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
 357 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
 358 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
 359 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
 360 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
 361 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
 362
 363 union uvh_event_occurred0_u {
 364     unsigned long       v;
 365     struct uv1h_event_occurred0_s {
 366         unsigned long   lb_hcerr             :  1;  /* RW, W1C */
 367         unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
 368         unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
 369         unsigned long   lh_hcerr             :  1;  /* RW, W1C */
 370         unsigned long   rh_hcerr             :  1;  /* RW, W1C */
 371         unsigned long   xn_hcerr             :  1;  /* RW, W1C */
 372         unsigned long   si_hcerr             :  1;  /* RW, W1C */
 373         unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
 374         unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
 375         unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
 376         unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
 377         unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
 378         unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
 379         unsigned long   si_aoerr0            :  1;  /* RW, W1C */
 380         unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
 381         unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
 382         unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
 383         unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
 384         unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
 385         unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
 386         unsigned long   si_aoerr1            :  1;  /* RW, W1C */
 387         unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
 388         unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
 389         unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
 390         unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
 391         unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
 392         unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
 393         unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
 394         unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
 395         unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
 396         unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
 397         unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
 398         unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
 399         unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
 400         unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
 401         unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
 402         unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
 403         unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
 404         unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
 405         unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
 406         unsigned long   stop_clock           :  1;  /* RW, W1C */
 407         unsigned long   asic_to_l1           :  1;  /* RW, W1C */
 408         unsigned long   l1_to_asic           :  1;  /* RW, W1C */
 409         unsigned long   ltc_int              :  1;  /* RW, W1C */
 410         unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
 411         unsigned long   ipi_int              :  1;  /* RW, W1C */
 412         unsigned long   extio_int0           :  1;  /* RW, W1C */
 413         unsigned long   extio_int1           :  1;  /* RW, W1C */
 414         unsigned long   extio_int2           :  1;  /* RW, W1C */
 415         unsigned long   extio_int3           :  1;  /* RW, W1C */
 416         unsigned long   profile_int          :  1;  /* RW, W1C */
 417         unsigned long   rtc0                 :  1;  /* RW, W1C */
 418         unsigned long   rtc1                 :  1;  /* RW, W1C */
 419         unsigned long   rtc2                 :  1;  /* RW, W1C */
 420         unsigned long   rtc3                 :  1;  /* RW, W1C */
 421         unsigned long   bau_data             :  1;  /* RW, W1C */
 422         unsigned long   power_management_req :  1;  /* RW, W1C */
 423         unsigned long   rsvd_57_63           :  7;  /*    */
 424     } s1;
 425     struct uv2h_event_occurred0_s {
 426         unsigned long   lb_hcerr            :  1;  /* RW */
 427         unsigned long   qp_hcerr            :  1;  /* RW */
 428         unsigned long   rh_hcerr            :  1;  /* RW */
 429         unsigned long   lh0_hcerr           :  1;  /* RW */
 430         unsigned long   lh1_hcerr           :  1;  /* RW */
 431         unsigned long   gr0_hcerr           :  1;  /* RW */
 432         unsigned long   gr1_hcerr           :  1;  /* RW */
 433         unsigned long   ni0_hcerr           :  1;  /* RW */
 434         unsigned long   ni1_hcerr           :  1;  /* RW */
 435         unsigned long   lb_aoerr0           :  1;  /* RW */
 436         unsigned long   qp_aoerr0           :  1;  /* RW */
 437         unsigned long   rh_aoerr0           :  1;  /* RW */
 438         unsigned long   lh0_aoerr0          :  1;  /* RW */
 439         unsigned long   lh1_aoerr0          :  1;  /* RW */
 440         unsigned long   gr0_aoerr0          :  1;  /* RW */
 441         unsigned long   gr1_aoerr0          :  1;  /* RW */
 442         unsigned long   xb_aoerr0           :  1;  /* RW */
 443         unsigned long   rt_aoerr0           :  1;  /* RW */
 444         unsigned long   ni0_aoerr0          :  1;  /* RW */
 445         unsigned long   ni1_aoerr0          :  1;  /* RW */
 446         unsigned long   lb_aoerr1           :  1;  /* RW */
 447         unsigned long   qp_aoerr1           :  1;  /* RW */
 448         unsigned long   rh_aoerr1           :  1;  /* RW */
 449         unsigned long   lh0_aoerr1          :  1;  /* RW */
 450         unsigned long   lh1_aoerr1          :  1;  /* RW */
 451         unsigned long   gr0_aoerr1          :  1;  /* RW */
 452         unsigned long   gr1_aoerr1          :  1;  /* RW */
 453         unsigned long   xb_aoerr1           :  1;  /* RW */
 454         unsigned long   rt_aoerr1           :  1;  /* RW */
 455         unsigned long   ni0_aoerr1          :  1;  /* RW */
 456         unsigned long   ni1_aoerr1          :  1;  /* RW */
 457         unsigned long   system_shutdown_int :  1;  /* RW */
 458         unsigned long   lb_irq_int_0        :  1;  /* RW */
 459         unsigned long   lb_irq_int_1        :  1;  /* RW */
 460         unsigned long   lb_irq_int_2        :  1;  /* RW */
 461         unsigned long   lb_irq_int_3        :  1;  /* RW */
 462         unsigned long   lb_irq_int_4        :  1;  /* RW */
 463         unsigned long   lb_irq_int_5        :  1;  /* RW */
 464         unsigned long   lb_irq_int_6        :  1;  /* RW */
 465         unsigned long   lb_irq_int_7        :  1;  /* RW */
 466         unsigned long   lb_irq_int_8        :  1;  /* RW */
 467         unsigned long   lb_irq_int_9        :  1;  /* RW */
 468         unsigned long   lb_irq_int_10       :  1;  /* RW */
 469         unsigned long   lb_irq_int_11       :  1;  /* RW */
 470         unsigned long   lb_irq_int_12       :  1;  /* RW */
 471         unsigned long   lb_irq_int_13       :  1;  /* RW */
 472         unsigned long   lb_irq_int_14       :  1;  /* RW */
 473         unsigned long   lb_irq_int_15       :  1;  /* RW */
 474         unsigned long   l1_nmi_int          :  1;  /* RW */
 475         unsigned long   stop_clock          :  1;  /* RW */
 476         unsigned long   asic_to_l1          :  1;  /* RW */
 477         unsigned long   l1_to_asic          :  1;  /* RW */
 478         unsigned long   la_seq_trigger      :  1;  /* RW */
 479         unsigned long   ipi_int             :  1;  /* RW */
 480         unsigned long   extio_int0          :  1;  /* RW */
 481         unsigned long   extio_int1          :  1;  /* RW */
 482         unsigned long   extio_int2          :  1;  /* RW */
 483         unsigned long   extio_int3          :  1;  /* RW */
 484         unsigned long   profile_int         :  1;  /* RW */
 485         unsigned long   rsvd_59_63          :  5;  /*    */
 486     } s2;
 487 };
 488
 489 /* ========================================================================= */
 490 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 491 /* ========================================================================= */
 492 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
 493 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
 494
 495 /* ========================================================================= */
 496 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
 497 /* ========================================================================= */
 498 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
 499
 500 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
 501 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 502 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
 503 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 504 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 505 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 506 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
 507 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 508 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
 509 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 510 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
 511 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 512 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
 513 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 514 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 515 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 516
 517 union uvh_gr0_tlb_int0_config_u {
 518     unsigned long       v;
 519     struct uvh_gr0_tlb_int0_config_s {
 520         unsigned long   vector_  :  8;  /* RW */
 521         unsigned long   dm       :  3;  /* RW */
 522         unsigned long   destmode :  1;  /* RW */
 523         unsigned long   status   :  1;  /* RO */
 524         unsigned long   p        :  1;  /* RO */
 525         unsigned long   rsvd_14  :  1;  /*    */
 526         unsigned long   t        :  1;  /* RO */
 527         unsigned long   m        :  1;  /* RW */
 528         unsigned long   rsvd_17_31: 15;  /*    */
 529         unsigned long   apic_id  : 32;  /* RW */
 530     } s;
 531 };
 532
 533 /* ========================================================================= */
 534 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
 535 /* ========================================================================= */
 536 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
 537
 538 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
 539 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 540 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
 541 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 542 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 543 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 544 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
 545 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 546 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
 547 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 548 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
 549 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 550 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
 551 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 552 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 553 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 554
 555 union uvh_gr0_tlb_int1_config_u {
 556     unsigned long       v;
 557     struct uvh_gr0_tlb_int1_config_s {
 558         unsigned long   vector_  :  8;  /* RW */
 559         unsigned long   dm       :  3;  /* RW */
 560         unsigned long   destmode :  1;  /* RW */
 561         unsigned long   status   :  1;  /* RO */
 562         unsigned long   p        :  1;  /* RO */
 563         unsigned long   rsvd_14  :  1;  /*    */
 564         unsigned long   t        :  1;  /* RO */
 565         unsigned long   m        :  1;  /* RW */
 566         unsigned long   rsvd_17_31: 15;  /*    */
 567         unsigned long   apic_id  : 32;  /* RW */
 568     } s;
 569 };
 570
 571 /* ========================================================================= */
 572 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
 573 /* ========================================================================= */
 574 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
 575
 576 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
 577 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 578 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
 579 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
 580 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
 581 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 582 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
 583 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
 584 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
 585 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
 586 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
 587 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
 588 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
 589 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
 590 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
 591 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 592
 593 union uvh_gr1_tlb_int0_config_u {
 594     unsigned long       v;
 595     struct uvh_gr1_tlb_int0_config_s {
 596         unsigned long   vector_  :  8;  /* RW */
 597         unsigned long   dm       :  3;  /* RW */
 598         unsigned long   destmode :  1;  /* RW */
 599         unsigned long   status   :  1;  /* RO */
 600         unsigned long   p        :  1;  /* RO */
 601         unsigned long   rsvd_14  :  1;  /*    */
 602         unsigned long   t        :  1;  /* RO */
 603         unsigned long   m        :  1;  /* RW */
 604         unsigned long   rsvd_17_31: 15;  /*    */
 605         unsigned long   apic_id  : 32;  /* RW */
 606     } s;
 607 };
 608
 609 /* ========================================================================= */
 610 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
 611 /* ========================================================================= */
 612 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
 613
 614 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
 615 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
 616 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
 617 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
 618 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
 619 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
 620 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
 621 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
 622 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
 623 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
 624 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
 625 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
 626 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
 627 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
 628 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
 629 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
 630
 631 union uvh_gr1_tlb_int1_config_u {
 632     unsigned long       v;
 633     struct uvh_gr1_tlb_int1_config_s {
 634         unsigned long   vector_  :  8;  /* RW */
 635         unsigned long   dm       :  3;  /* RW */
 636         unsigned long   destmode :  1;  /* RW */
 637         unsigned long   status   :  1;  /* RO */
 638         unsigned long   p        :  1;  /* RO */
 639         unsigned long   rsvd_14  :  1;  /*    */
 640         unsigned long   t        :  1;  /* RO */
 641         unsigned long   m        :  1;  /* RW */
 642         unsigned long   rsvd_17_31: 15;  /*    */
 643         unsigned long   apic_id  : 32;  /* RW */
 644     } s;
 645 };
 646
 647 /* ========================================================================= */
 648 /*                               UVH_INT_CMPB                                */
 649 /* ========================================================================= */
 650 #define UVH_INT_CMPB 0x22080UL
 651
 652 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
 653 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
 654
 655 union uvh_int_cmpb_u {
 656     unsigned long       v;
 657     struct uvh_int_cmpb_s {
 658         unsigned long   real_time_cmpb : 56;  /* RW */
 659         unsigned long   rsvd_56_63     :  8;  /*    */
 660     } s;
 661 };
 662
 663 /* ========================================================================= */
 664 /*                               UVH_INT_CMPC                                */
 665 /* ========================================================================= */
 666 #define UVH_INT_CMPC 0x22100UL
 667
 668 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
 669 #define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
 670 #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT        (is_uv1_hub() ?         \
 671                         UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT :     \
 672                         UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
 673 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
 674 #define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
 675 #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK        (is_uv1_hub() ?         \
 676                         UV1H_INT_CMPC_REAL_TIME_CMPC_MASK :     \
 677                         UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
 678
 679 union uvh_int_cmpc_u {
 680     unsigned long       v;
 681     struct uvh_int_cmpc_s {
 682         unsigned long   real_time_cmpc : 56;  /* RW */
 683         unsigned long   rsvd_56_63     :  8;  /*    */
 684     } s;
 685 };
 686
 687 /* ========================================================================= */
 688 /*                               UVH_INT_CMPD                                */
 689 /* ========================================================================= */
 690 #define UVH_INT_CMPD 0x22180UL
 691
 692 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
 693 #define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
 694 #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT        (is_uv1_hub() ?         \
 695                         UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT :     \
 696                         UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
 697 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
 698 #define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
 699 #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK        (is_uv1_hub() ?         \
 700                         UV1H_INT_CMPD_REAL_TIME_CMPD_MASK :     \
 701                         UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
 702
 703 union uvh_int_cmpd_u {
 704     unsigned long       v;
 705     struct uvh_int_cmpd_s {
 706         unsigned long   real_time_cmpd : 56;  /* RW */
 707         unsigned long   rsvd_56_63     :  8;  /*    */
 708     } s;
 709 };
 710
 711 /* ========================================================================= */
 712 /*                               UVH_IPI_INT                                 */
 713 /* ========================================================================= */
 714 #define UVH_IPI_INT 0x60500UL
 715 #define UVH_IPI_INT_32 0x348
 716
 717 #define UVH_IPI_INT_VECTOR_SHFT 0
 718 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
 719 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
 720 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
 721 #define UVH_IPI_INT_DESTMODE_SHFT 11
 722 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
 723 #define UVH_IPI_INT_APIC_ID_SHFT 16
 724 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
 725 #define UVH_IPI_INT_SEND_SHFT 63
 726 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
 727
 728 union uvh_ipi_int_u {
 729     unsigned long       v;
 730     struct uvh_ipi_int_s {
 731         unsigned long   vector_       :  8;  /* RW */
 732         unsigned long   delivery_mode :  3;  /* RW */
 733         unsigned long   destmode      :  1;  /* RW */
 734         unsigned long   rsvd_12_15    :  4;  /*    */
 735         unsigned long   apic_id       : 32;  /* RW */
 736         unsigned long   rsvd_48_62    : 15;  /*    */
 737         unsigned long   send          :  1;  /* WP */
 738     } s;
 739 };
 740
 741 /* ========================================================================= */
 742 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 743 /* ========================================================================= */
 744 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
 745 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
 746
 747 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
 748 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
 749 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
 750 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
 751
 752 union uvh_lb_bau_intd_payload_queue_first_u {
 753     unsigned long       v;
 754     struct uvh_lb_bau_intd_payload_queue_first_s {
 755         unsigned long   rsvd_0_3:  4;  /*    */
 756         unsigned long   address : 39;  /* RW */
 757         unsigned long   rsvd_43_48:  6;  /*    */
 758         unsigned long   node_id : 14;  /* RW */
 759         unsigned long   rsvd_63 :  1;  /*    */
 760     } s;
 761 };
 762
 763 /* ========================================================================= */
 764 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 765 /* ========================================================================= */
 766 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
 767 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
 768
 769 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
 770 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
 771
 772 union uvh_lb_bau_intd_payload_queue_last_u {
 773     unsigned long       v;
 774     struct uvh_lb_bau_intd_payload_queue_last_s {
 775         unsigned long   rsvd_0_3:  4;  /*    */
 776         unsigned long   address : 39;  /* RW */
 777         unsigned long   rsvd_43_63: 21;  /*    */
 778     } s;
 779 };
 780
 781 /* ========================================================================= */
 782 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 783 /* ========================================================================= */
 784 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
 785 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
 786
 787 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
 788 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
 789
 790 union uvh_lb_bau_intd_payload_queue_tail_u {
 791     unsigned long       v;
 792     struct uvh_lb_bau_intd_payload_queue_tail_s {
 793         unsigned long   rsvd_0_3:  4;  /*    */
 794         unsigned long   address : 39;  /* RW */
 795         unsigned long   rsvd_43_63: 21;  /*    */
 796     } s;
 797 };
 798
 799 /* ========================================================================= */
 800 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 801 /* ========================================================================= */
 802 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
 803 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
 804
 805 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 806 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
 807 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
 808 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
 809 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
 810 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
 811 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
 812 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
 813 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
 814 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
 815 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
 816 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
 817 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
 818 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
 819 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
 820 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
 821 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
 822 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
 823 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
 824 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
 825 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
 826 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
 827 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
 828 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
 829 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
 830 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
 831 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
 832 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
 833 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
 834 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 835 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
 836 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
 837
 838 union uvh_lb_bau_intd_software_acknowledge_u {
 839     unsigned long       v;
 840     struct uvh_lb_bau_intd_software_acknowledge_s {
 841         unsigned long   pending_0 :  1;  /* RW, W1C */
 842         unsigned long   pending_1 :  1;  /* RW, W1C */
 843         unsigned long   pending_2 :  1;  /* RW, W1C */
 844         unsigned long   pending_3 :  1;  /* RW, W1C */
 845         unsigned long   pending_4 :  1;  /* RW, W1C */
 846         unsigned long   pending_5 :  1;  /* RW, W1C */
 847         unsigned long   pending_6 :  1;  /* RW, W1C */
 848         unsigned long   pending_7 :  1;  /* RW, W1C */
 849         unsigned long   timeout_0 :  1;  /* RW, W1C */
 850         unsigned long   timeout_1 :  1;  /* RW, W1C */
 851         unsigned long   timeout_2 :  1;  /* RW, W1C */
 852         unsigned long   timeout_3 :  1;  /* RW, W1C */
 853         unsigned long   timeout_4 :  1;  /* RW, W1C */
 854         unsigned long   timeout_5 :  1;  /* RW, W1C */
 855         unsigned long   timeout_6 :  1;  /* RW, W1C */
 856         unsigned long   timeout_7 :  1;  /* RW, W1C */
 857         unsigned long   rsvd_16_63: 48;  /*    */
 858     } s;
 859 };
 860
 861 /* ========================================================================= */
 862 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 863 /* ========================================================================= */
 864 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
 865 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
 866
 867 /* ========================================================================= */
 868 /*                         UVH_LB_BAU_MISC_CONTROL                           */
 869 /* ========================================================================= */
 870 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL
 871 #define UVH_LB_BAU_MISC_CONTROL_32 0xa10
 872
 873 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
 874 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
 875 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
 876 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
 877 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
 878 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
 879 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
 880 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
 881 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
 882 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 883 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
 884 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 885 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
 886 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 887 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
 888 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 889 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
 890 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 891 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
 892 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 893 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
 894 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 895 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
 896 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 897 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
 898 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 899 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
 900 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 901 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
 902 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
 903
 904 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
 905 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
 906 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
 907 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
 908 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
 909 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
 910 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
 911 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
 912 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
 913 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 914 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
 915 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 916 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
 917 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 918 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
 919 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 920 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
 921 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 922 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
 923 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 924 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
 925 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 926 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
 927 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 928 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
 929 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 930 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
 931 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 932 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
 933 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
 934 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
 935 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
 936
 937 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
 938 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
 939 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
 940 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
 941 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
 942 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
 943 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
 944 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
 945 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
 946 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 947 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
 948 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 949 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
 950 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
 951 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
 952 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
 953 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
 954 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
 955 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
 956 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
 957 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
 958 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
 959 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
 960 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
 961 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
 962 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
 963 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
 964 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 965 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
 966 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
 967 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
 968 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
 969 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
 970 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
 971 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
 972 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
 973 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
 974 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
 975 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
 976 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
 977 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
 978 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
 979 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
 980 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
 981 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
 982 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
 983
 984 union uvh_lb_bau_misc_control_u {
 985     unsigned long       v;
 986     struct uvh_lb_bau_misc_control_s {
 987         unsigned long   rejection_delay                    :  8;  /* RW */
 988         unsigned long   apic_mode                          :  1;  /* RW */
 989         unsigned long   force_broadcast                    :  1;  /* RW */
 990         unsigned long   force_lock_nop                     :  1;  /* RW */
 991         unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
 992         unsigned long   descriptor_fetch_mode              :  1;  /* RW */
 993         unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
 994         unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
 995         unsigned long   enable_dual_mapping_mode           :  1;  /* RW */
 996         unsigned long   vga_io_port_decode_enable          :  1;  /* RW */
 997         unsigned long   vga_io_port_16_bit_decode          :  1;  /* RW */
 998         unsigned long   suppress_dest_registration         :  1;  /* RW */
 999         unsigned long   programmed_initial_priority        :  3;  /* RW */
1000         unsigned long   use_incoming_priority              :  1;  /* RW */
1001         unsigned long   enable_programmed_initial_priority :  1;  /* RW */
1002         unsigned long   rsvd_29_63    : 35;
1003     } s;
1004     struct uv1h_lb_bau_misc_control_s {
1005         unsigned long   rejection_delay                    :  8;  /* RW */
1006         unsigned long   apic_mode                          :  1;  /* RW */
1007         unsigned long   force_broadcast                    :  1;  /* RW */
1008         unsigned long   force_lock_nop                     :  1;  /* RW */
1009         unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
1010         unsigned long   descriptor_fetch_mode              :  1;  /* RW */
1011         unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
1012         unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
1013         unsigned long   enable_dual_mapping_mode           :  1;  /* RW */
1014         unsigned long   vga_io_port_decode_enable          :  1;  /* RW */
1015         unsigned long   vga_io_port_16_bit_decode          :  1;  /* RW */
1016         unsigned long   suppress_dest_registration         :  1;  /* RW */
1017         unsigned long   programmed_initial_priority        :  3;  /* RW */
1018         unsigned long   use_incoming_priority              :  1;  /* RW */
1019         unsigned long   enable_programmed_initial_priority :  1;  /* RW */
1020         unsigned long   rsvd_29_47                         : 19;  /*    */
1021         unsigned long   fun                                : 16;  /* RW */
1022     } s1;
1023     struct uv2h_lb_bau_misc_control_s {
1024         unsigned long   rejection_delay                      :  8;  /* RW */
1025         unsigned long   apic_mode                            :  1;  /* RW */
1026         unsigned long   force_broadcast                      :  1;  /* RW */
1027         unsigned long   force_lock_nop                       :  1;  /* RW */
1028         unsigned long   qpi_agent_presence_vector            :  3;  /* RW */
1029         unsigned long   descriptor_fetch_mode                :  1;  /* RW */
1030         unsigned long   enable_intd_soft_ack_mode            :  1;  /* RW */
1031         unsigned long   intd_soft_ack_timeout_period         :  4;  /* RW */
1032         unsigned long   enable_dual_mapping_mode             :  1;  /* RW */
1033         unsigned long   vga_io_port_decode_enable            :  1;  /* RW */
1034         unsigned long   vga_io_port_16_bit_decode            :  1;  /* RW */
1035         unsigned long   suppress_dest_registration           :  1;  /* RW */
1036         unsigned long   programmed_initial_priority          :  3;  /* RW */
1037         unsigned long   use_incoming_priority                :  1;  /* RW */
1038         unsigned long   enable_programmed_initial_priority   :  1;  /* RW */
1039         unsigned long   enable_automatic_apic_mode_selection :  1;  /* RW */
1040         unsigned long   apic_mode_status                     :  1;  /* RO */
1041         unsigned long   suppress_interrupts_to_self          :  1;  /* RW */
1042         unsigned long   enable_lock_based_system_flush       :  1;  /* RW */
1043         unsigned long   enable_extended_sb_status            :  1;  /* RW */
1044         unsigned long   suppress_int_prio_udt_to_self        :  1;  /* RW */
1045         unsigned long   use_legacy_descriptor_formats        :  1;  /* RW */
1046         unsigned long   rsvd_36_47                           : 12;  /*    */
1047         unsigned long   fun                                  : 16;  /* RW */
1048     } s2;
1049 };
1050
1051 /* ========================================================================= */
1052 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
1053 /* ========================================================================= */
1054 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1055 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
1056
1057 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
1058 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
1059 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
1060 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
1061 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
1062 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
1063
1064 union uvh_lb_bau_sb_activation_control_u {
1065     unsigned long       v;
1066     struct uvh_lb_bau_sb_activation_control_s {
1067         unsigned long   index :  6;  /* RW */
1068         unsigned long   rsvd_6_61: 56;  /*    */
1069         unsigned long   push  :  1;  /* WP */
1070         unsigned long   init  :  1;  /* WP */
1071     } s;
1072 };
1073
1074 /* ========================================================================= */
1075 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
1076 /* ========================================================================= */
1077 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1078 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
1079
1080 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
1081 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
1082
1083 union uvh_lb_bau_sb_activation_status_0_u {
1084     unsigned long       v;
1085     struct uvh_lb_bau_sb_activation_status_0_s {
1086         unsigned long   status : 64;  /* RW */
1087     } s;
1088 };
1089
1090 /* ========================================================================= */
1091 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
1092 /* ========================================================================= */
1093 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1094 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
1095
1096 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
1097 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
1098
1099 union uvh_lb_bau_sb_activation_status_1_u {
1100     unsigned long       v;
1101     struct uvh_lb_bau_sb_activation_status_1_s {
1102         unsigned long   status : 64;  /* RW */
1103     } s;
1104 };
1105
1106 /* ========================================================================= */
1107 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
1108 /* ========================================================================= */
1109 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1110 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
1111
1112 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1113 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1114 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
1115 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
1116
1117 union uvh_lb_bau_sb_descriptor_base_u {
1118     unsigned long       v;
1119     struct uvh_lb_bau_sb_descriptor_base_s {
1120         unsigned long   rsvd_0_11    : 12;  /*    */
1121         unsigned long   page_address : 31;  /* RW */
1122         unsigned long   rsvd_43_48   :  6;  /*    */
1123         unsigned long   node_id      : 14;  /* RW */
1124         unsigned long   rsvd_63      :  1;  /*    */
1125     } s;
1126 };
1127
1128 /* ========================================================================= */
1129 /*                               UVH_NODE_ID                                 */
1130 /* ========================================================================= */
1131 #define UVH_NODE_ID 0x0UL
1132
1133 #define UVH_NODE_ID_FORCE1_SHFT 0
1134 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1135 #define UVH_NODE_ID_MANUFACTURER_SHFT 1
1136 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1137 #define UVH_NODE_ID_PART_NUMBER_SHFT 12
1138 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1139 #define UVH_NODE_ID_REVISION_SHFT 28
1140 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1141 #define UVH_NODE_ID_NODE_ID_SHFT 32
1142 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1143
1144 #define UV1H_NODE_ID_FORCE1_SHFT 0
1145 #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1146 #define UV1H_NODE_ID_MANUFACTURER_SHFT 1
1147 #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1148 #define UV1H_NODE_ID_PART_NUMBER_SHFT 12
1149 #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1150 #define UV1H_NODE_ID_REVISION_SHFT 28
1151 #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1152 #define UV1H_NODE_ID_NODE_ID_SHFT 32
1153 #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1154 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
1155 #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1156 #define UV1H_NODE_ID_NI_PORT_SHFT 56
1157 #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1158
1159 #define UV2H_NODE_ID_FORCE1_SHFT 0
1160 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1161 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1
1162 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1163 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12
1164 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1165 #define UV2H_NODE_ID_REVISION_SHFT 28
1166 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1167 #define UV2H_NODE_ID_NODE_ID_SHFT 32
1168 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1169 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
1170 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
1171 #define UV2H_NODE_ID_NI_PORT_SHFT 57
1172 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
1173
1174 union uvh_node_id_u {
1175     unsigned long       v;
1176     struct uvh_node_id_s {
1177         unsigned long   force1        :  1;  /* RO */
1178         unsigned long   manufacturer  : 11;  /* RO */
1179         unsigned long   part_number   : 16;  /* RO */
1180         unsigned long   revision      :  4;  /* RO */
1181         unsigned long   node_id       : 15;  /* RW */
1182         unsigned long   rsvd_47_63    : 17;
1183     } s;
1184     struct uv1h_node_id_s {
1185         unsigned long   force1        :  1;  /* RO */
1186         unsigned long   manufacturer  : 11;  /* RO */
1187         unsigned long   part_number   : 16;  /* RO */
1188         unsigned long   revision      :  4;  /* RO */
1189         unsigned long   node_id       : 15;  /* RW */
1190         unsigned long   rsvd_47       :  1;  /*    */
1191         unsigned long   nodes_per_bit :  7;  /* RW */
1192         unsigned long   rsvd_55       :  1;  /*    */
1193         unsigned long   ni_port       :  4;  /* RO */
1194         unsigned long   rsvd_60_63    :  4;  /*    */
1195     } s1;
1196     struct uv2h_node_id_s {
1197         unsigned long   force1        :  1;  /* RO */
1198         unsigned long   manufacturer  : 11;  /* RO */
1199         unsigned long   part_number   : 16;  /* RO */
1200         unsigned long   revision      :  4;  /* RO */
1201         unsigned long   node_id       : 15;  /* RW */
1202         unsigned long   rsvd_47_49    :  3;  /*    */
1203         unsigned long   nodes_per_bit :  7;  /* RO */
1204         unsigned long   ni_port       :  5;  /* RO */
1205         unsigned long   rsvd_62_63    :  2;  /*    */
1206     } s2;
1207 };
1208
1209 /* ========================================================================= */
1210 /*                          UVH_NODE_PRESENT_TABLE                           */
1211 /* ========================================================================= */
1212 #define UVH_NODE_PRESENT_TABLE 0x1400UL
1213 #define UVH_NODE_PRESENT_TABLE_DEPTH 16
1214
1215 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1216 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1217
1218 union uvh_node_present_table_u {
1219     unsigned long       v;
1220     struct uvh_node_present_table_s {
1221         unsigned long   nodes : 64;  /* RW */
1222     } s;
1223 };
1224
1225 /* ========================================================================= */
1226 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
1227 /* ========================================================================= */
1228 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
1229
1230 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
1231 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1232 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
1233 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1234 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
1235 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
1236
1237 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
1238     unsigned long       v;
1239     struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
1240         unsigned long   rsvd_0_23: 24;  /*    */
1241         unsigned long   base    :  8;  /* RW */
1242         unsigned long   rsvd_32_47: 16;  /*    */
1243         unsigned long   m_alias :  5;  /* RW */
1244         unsigned long   rsvd_53_62: 10;  /*    */
1245         unsigned long   enable  :  1;  /* RW */
1246     } s;
1247 };
1248
1249 /* ========================================================================= */
1250 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
1251 /* ========================================================================= */
1252 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
1253
1254 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
1255 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1256 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
1257 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1258 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
1259 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
1260
1261 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
1262     unsigned long       v;
1263     struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
1264         unsigned long   rsvd_0_23: 24;  /*    */
1265         unsigned long   base    :  8;  /* RW */
1266         unsigned long   rsvd_32_47: 16;  /*    */
1267         unsigned long   m_alias :  5;  /* RW */
1268         unsigned long   rsvd_53_62: 10;  /*    */
1269         unsigned long   enable  :  1;  /* RW */
1270     } s;
1271 };
1272
1273 /* ========================================================================= */
1274 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
1275 /* ========================================================================= */
1276 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
1277
1278 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
1279 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1280 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
1281 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1282 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
1283 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
1284
1285 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
1286     unsigned long       v;
1287     struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
1288         unsigned long   rsvd_0_23: 24;  /*    */
1289         unsigned long   base    :  8;  /* RW */
1290         unsigned long   rsvd_32_47: 16;  /*    */
1291         unsigned long   m_alias :  5;  /* RW */
1292         unsigned long   rsvd_53_62: 10;  /*    */
1293         unsigned long   enable  :  1;  /* RW */
1294     } s;
1295 };
1296
1297 /* ========================================================================= */
1298 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
1299 /* ========================================================================= */
1300 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1301
1302 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1303 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1304
1305 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1306     unsigned long       v;
1307     struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1308         unsigned long   rsvd_0_23 : 24;  /*    */
1309         unsigned long   dest_base : 22;  /* RW */
1310         unsigned long   rsvd_46_63: 18;  /*    */
1311     } s;
1312 };
1313
1314 /* ========================================================================= */
1315 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
1316 /* ========================================================================= */
1317 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1318
1319 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1320 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1321
1322 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1323     unsigned long       v;
1324     struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1325         unsigned long   rsvd_0_23 : 24;  /*    */
1326         unsigned long   dest_base : 22;  /* RW */
1327         unsigned long   rsvd_46_63: 18;  /*    */
1328     } s;
1329 };
1330
1331 /* ========================================================================= */
1332 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
1333 /* ========================================================================= */
1334 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1335
1336 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1337 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1338
1339 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1340     unsigned long       v;
1341     struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1342         unsigned long   rsvd_0_23 : 24;  /*    */
1343         unsigned long   dest_base : 22;  /* RW */
1344         unsigned long   rsvd_46_63: 18;  /*    */
1345     } s;
1346 };
1347
1348 /* ========================================================================= */
1349 /*                          UVH_RH_GAM_CONFIG_MMR                            */
1350 /* ========================================================================= */
1351 #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
1352
1353 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1354 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1355 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1356 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1357
1358 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1359 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1360 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1361 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1362 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
1363 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
1364
1365 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1366 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1367 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1368 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1369
1370 union uvh_rh_gam_config_mmr_u {
1371     unsigned long       v;
1372     struct uvh_rh_gam_config_mmr_s {
1373         unsigned long   m_skt     :  6;  /* RW */
1374         unsigned long   n_skt     :  4;  /* RW */
1375         unsigned long   rsvd_10_63    : 54;
1376     } s;
1377     struct uv1h_rh_gam_config_mmr_s {
1378         unsigned long   m_skt     :  6;  /* RW */
1379         unsigned long   n_skt     :  4;  /* RW */
1380         unsigned long   rsvd_10_11:  2;  /*    */
1381         unsigned long   mmiol_cfg :  1;  /* RW */
1382         unsigned long   rsvd_13_63: 51;  /*    */
1383     } s1;
1384     struct uv2h_rh_gam_config_mmr_s {
1385         unsigned long   m_skt :  6;  /* RW */
1386         unsigned long   n_skt :  4;  /* RW */
1387         unsigned long   rsvd_10_63: 54;  /*    */
1388     } s2;
1389 };
1390
1391 /* ========================================================================= */
1392 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
1393 /* ========================================================================= */
1394 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1395
1396 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1397 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1398
1399 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1400 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1401 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1402 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1403 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1404 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1405 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1406 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1407
1408 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1409 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1410 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1411 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1412 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1413 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1414
1415 union uvh_rh_gam_gru_overlay_config_mmr_u {
1416     unsigned long       v;
1417     struct uvh_rh_gam_gru_overlay_config_mmr_s {
1418         unsigned long   rsvd_0_27: 28;  /*    */
1419         unsigned long   base   : 18;  /* RW */
1420         unsigned long   rsvd_46_62    : 17;
1421         unsigned long   enable :  1;  /* RW */
1422     } s;
1423     struct uv1h_rh_gam_gru_overlay_config_mmr_s {
1424         unsigned long   rsvd_0_27: 28;  /*    */
1425         unsigned long   base   : 18;  /* RW */
1426         unsigned long   rsvd_46_47:  2;  /*    */
1427         unsigned long   gr4    :  1;  /* RW */
1428         unsigned long   rsvd_49_51:  3;  /*    */
1429         unsigned long   n_gru  :  4;  /* RW */
1430         unsigned long   rsvd_56_62:  7;  /*    */
1431         unsigned long   enable :  1;  /* RW */
1432     } s1;
1433     struct uv2h_rh_gam_gru_overlay_config_mmr_s {
1434         unsigned long   rsvd_0_27: 28;  /*    */
1435         unsigned long   base   : 18;  /* RW */
1436         unsigned long   rsvd_46_51:  6;  /*    */
1437         unsigned long   n_gru  :  4;  /* RW */
1438         unsigned long   rsvd_56_62:  7;  /*    */
1439         unsigned long   enable :  1;  /* RW */
1440     } s2;
1441 };
1442
1443 /* ========================================================================= */
1444 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
1445 /* ========================================================================= */
1446 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1447
1448 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1449 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1450 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1451 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1452 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1453 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1454 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1455 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1456
1457 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
1458 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
1459 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1460 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1461 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1462 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1463 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1464 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1465
1466 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1467     unsigned long       v;
1468     struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
1469         unsigned long   rsvd_0_29: 30;  /*    */
1470         unsigned long   base   : 16;  /* RW */
1471         unsigned long   m_io   :  6;  /* RW */
1472         unsigned long   n_io   :  4;  /* RW */
1473         unsigned long   rsvd_56_62:  7;  /*    */
1474         unsigned long   enable :  1;  /* RW */
1475     } s1;
1476     struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
1477         unsigned long   rsvd_0_26: 27;  /*    */
1478         unsigned long   base   : 19;  /* RW */
1479         unsigned long   m_io   :  6;  /* RW */
1480         unsigned long   n_io   :  4;  /* RW */
1481         unsigned long   rsvd_56_62:  7;  /*    */
1482         unsigned long   enable :  1;  /* RW */
1483     } s2;
1484 };
1485
1486 /* ========================================================================= */
1487 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
1488 /* ========================================================================= */
1489 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1490
1491 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1492 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1493
1494 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1495 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1496 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1497 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1498 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1499 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1500
1501 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1502 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1503 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1504 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1505
1506 union uvh_rh_gam_mmr_overlay_config_mmr_u {
1507     unsigned long       v;
1508     struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1509         unsigned long   rsvd_0_25: 26;  /*    */
1510         unsigned long   base     : 20;  /* RW */
1511         unsigned long   rsvd_46_62    : 17;
1512         unsigned long   enable   :  1;  /* RW */
1513     } s;
1514     struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
1515         unsigned long   rsvd_0_25: 26;  /*    */
1516         unsigned long   base     : 20;  /* RW */
1517         unsigned long   dual_hub :  1;  /* RW */
1518         unsigned long   rsvd_47_62: 16;  /*    */
1519         unsigned long   enable   :  1;  /* RW */
1520     } s1;
1521     struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
1522         unsigned long   rsvd_0_25: 26;  /*    */
1523         unsigned long   base   : 20;  /* RW */
1524         unsigned long   rsvd_46_62: 17;  /*    */
1525         unsigned long   enable :  1;  /* RW */
1526     } s2;
1527 };
1528
1529 /* ========================================================================= */
1530 /*                                 UVH_RTC                                   */
1531 /* ========================================================================= */
1532 #define UVH_RTC 0x340000UL
1533
1534 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1535 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1536
1537 union uvh_rtc_u {
1538     unsigned long       v;
1539     struct uvh_rtc_s {
1540         unsigned long   real_time_clock : 56;  /* RW */
1541         unsigned long   rsvd_56_63      :  8;  /*    */
1542     } s;
1543 };
1544
1545 /* ========================================================================= */
1546 /*                           UVH_RTC1_INT_CONFIG                             */
1547 /* ========================================================================= */
1548 #define UVH_RTC1_INT_CONFIG 0x615c0UL
1549
1550 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1551 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1552 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1553 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1554 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1555 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1556 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1557 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1558 #define UVH_RTC1_INT_CONFIG_P_SHFT 13
1559 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1560 #define UVH_RTC1_INT_CONFIG_T_SHFT 15
1561 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1562 #define UVH_RTC1_INT_CONFIG_M_SHFT 16
1563 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1564 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1565 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1566
1567 union uvh_rtc1_int_config_u {
1568     unsigned long       v;
1569     struct uvh_rtc1_int_config_s {
1570         unsigned long   vector_  :  8;  /* RW */
1571         unsigned long   dm       :  3;  /* RW */
1572         unsigned long   destmode :  1;  /* RW */
1573         unsigned long   status   :  1;  /* RO */
1574         unsigned long   p        :  1;  /* RO */
1575         unsigned long   rsvd_14  :  1;  /*    */
1576         unsigned long   t        :  1;  /* RO */
1577         unsigned long   m        :  1;  /* RW */
1578         unsigned long   rsvd_17_31: 15;  /*    */
1579         unsigned long   apic_id  : 32;  /* RW */
1580     } s;
1581 };
1582
1583 /* ========================================================================= */
1584 /*                               UVH_SCRATCH5                                */
1585 /* ========================================================================= */
1586 #define UVH_SCRATCH5 0x2d0200UL
1587 #define UVH_SCRATCH5_32 0x778
1588
1589 #define UVH_SCRATCH5_SCRATCH5_SHFT 0
1590 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1591
1592 union uvh_scratch5_u {
1593     unsigned long       v;
1594     struct uvh_scratch5_s {
1595         unsigned long   scratch5 : 64;  /* RW, W1CS */
1596     } s;
1597 };
1598
1599 /* ========================================================================= */
1600 /*                           UV2H_EVENT_OCCURRED2                            */
1601 /* ========================================================================= */
1602 #define UV2H_EVENT_OCCURRED2 0x70100UL
1603 #define UV2H_EVENT_OCCURRED2_32 0xb68
1604
1605 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1606 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1607 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
1608 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1609 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
1610 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1611 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
1612 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1613 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
1614 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1615 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
1616 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1617 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
1618 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1619 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
1620 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1621 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
1622 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1623 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
1624 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1625 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
1626 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1627 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
1628 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1629 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
1630 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1631 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
1632 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1633 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
1634 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1635 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
1636 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1637 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
1638 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1639 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
1640 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1641 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
1642 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1643 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
1644 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1645 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
1646 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1647 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
1648 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1649 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
1650 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1651 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
1652 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1653 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
1654 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1655 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
1656 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1657 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
1658 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1659 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
1660 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1661 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
1662 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1663 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
1664 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1665 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
1666 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1667 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
1668 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1669
1670 union uv2h_event_occurred2_u {
1671     unsigned long       v;
1672     struct uv2h_event_occurred2_s {
1673         unsigned long   rtc_0  :  1;  /* RW */
1674         unsigned long   rtc_1  :  1;  /* RW */
1675         unsigned long   rtc_2  :  1;  /* RW */
1676         unsigned long   rtc_3  :  1;  /* RW */
1677         unsigned long   rtc_4  :  1;  /* RW */
1678         unsigned long   rtc_5  :  1;  /* RW */
1679         unsigned long   rtc_6  :  1;  /* RW */
1680         unsigned long   rtc_7  :  1;  /* RW */
1681         unsigned long   rtc_8  :  1;  /* RW */
1682         unsigned long   rtc_9  :  1;  /* RW */
1683         unsigned long   rtc_10 :  1;  /* RW */
1684         unsigned long   rtc_11 :  1;  /* RW */
1685         unsigned long   rtc_12 :  1;  /* RW */
1686         unsigned long   rtc_13 :  1;  /* RW */
1687         unsigned long   rtc_14 :  1;  /* RW */
1688         unsigned long   rtc_15 :  1;  /* RW */
1689         unsigned long   rtc_16 :  1;  /* RW */
1690         unsigned long   rtc_17 :  1;  /* RW */
1691         unsigned long   rtc_18 :  1;  /* RW */
1692         unsigned long   rtc_19 :  1;  /* RW */
1693         unsigned long   rtc_20 :  1;  /* RW */
1694         unsigned long   rtc_21 :  1;  /* RW */
1695         unsigned long   rtc_22 :  1;  /* RW */
1696         unsigned long   rtc_23 :  1;  /* RW */
1697         unsigned long   rtc_24 :  1;  /* RW */
1698         unsigned long   rtc_25 :  1;  /* RW */
1699         unsigned long   rtc_26 :  1;  /* RW */
1700         unsigned long   rtc_27 :  1;  /* RW */
1701         unsigned long   rtc_28 :  1;  /* RW */
1702         unsigned long   rtc_29 :  1;  /* RW */
1703         unsigned long   rtc_30 :  1;  /* RW */
1704         unsigned long   rtc_31 :  1;  /* RW */
1705         unsigned long   rsvd_32_63: 32;  /*    */
1706     } s1;
1707 };
1708
1709 /* ========================================================================= */
1710 /*                        UV2H_EVENT_OCCURRED2_ALIAS                         */
1711 /* ========================================================================= */
1712 #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
1713 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
1714
1715 /* ========================================================================= */
1716 /*                    UV2H_LB_BAU_SB_ACTIVATION_STATUS_2                     */
1717 /* ========================================================================= */
1718 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
1719 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
1720
1721 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
1722 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
1723
1724 union uv2h_lb_bau_sb_activation_status_2_u {
1725     unsigned long       v;
1726     struct uv2h_lb_bau_sb_activation_status_2_s {
1727         unsigned long   aux_error : 64;  /* RW */
1728     } s1;
1729 };
1730
1731 /* ========================================================================= */
1732 /*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
1733 /* ========================================================================= */
1734 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
1735 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
1736
1737 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
1738 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
1739
1740 union uv1h_lb_target_physical_apic_id_mask_u {
1741     unsigned long       v;
1742     struct uv1h_lb_target_physical_apic_id_mask_s {
1743         unsigned long   bit_enables : 32;  /* RW */
1744         unsigned long   rsvd_32_63  : 32;  /*    */
1745     } s1;
1746 };
1747
1748
1749 #endif /* __ASM_UV_MMRS_X86_H__ */