1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
8 #include <asm/hyperv-tlfs.h>
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
15 enum intercept_words {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
44 INTERCEPT_DR0_WRITE = 48,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
60 INTERCEPT_SELECTIVE_CR0,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
100 INTERCEPT_MWAIT_COND,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
122 struct __attribute__ ((__packed__)) vmcb_control_area {
123 u32 intercepts[MAX_INTERCEPT];
124 u32 reserved_1[15 - MAX_INTERCEPT];
125 u16 pause_filter_thresh;
126 u16 pause_filter_count;
142 u32 exit_int_info_err;
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
160 u64 vmsa_pa; /* Used for an SEV-ES guest */
163 * Offset 0x3e0, 32 bytes reserved
164 * for use by hypervisor/software.
167 struct hv_vmcb_enlightenments hv_enlightenments;
173 #define TLB_CONTROL_DO_NOTHING 0
174 #define TLB_CONTROL_FLUSH_ALL_ASID 1
175 #define TLB_CONTROL_FLUSH_ASID 3
176 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
178 #define V_TPR_MASK 0x0f
180 #define V_IRQ_SHIFT 8
181 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
183 #define V_GIF_SHIFT 9
184 #define V_GIF_MASK (1 << V_GIF_SHIFT)
186 #define V_NMI_PENDING_SHIFT 11
187 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
189 #define V_NMI_BLOCKING_SHIFT 12
190 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
192 #define V_INTR_PRIO_SHIFT 16
193 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
195 #define V_IGN_TPR_SHIFT 20
196 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
198 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
200 #define V_INTR_MASKING_SHIFT 24
201 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
203 #define V_GIF_ENABLE_SHIFT 25
204 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
206 #define V_NMI_ENABLE_SHIFT 26
207 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
209 #define AVIC_ENABLE_SHIFT 31
210 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
212 #define X2APIC_MODE_SHIFT 30
213 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
215 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
216 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
218 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
219 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
221 #define SVM_IOIO_STR_SHIFT 2
222 #define SVM_IOIO_REP_SHIFT 3
223 #define SVM_IOIO_SIZE_SHIFT 4
224 #define SVM_IOIO_ASIZE_SHIFT 7
226 #define SVM_IOIO_TYPE_MASK 1
227 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
228 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
229 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
230 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
232 #define SVM_VM_CR_VALID_MASK 0x001fULL
233 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
234 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
236 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
237 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
238 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
241 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
242 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
243 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
244 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
248 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
249 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
250 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
252 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
253 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
254 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
255 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
256 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
258 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
260 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
262 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
263 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
264 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
266 enum avic_ipi_failure_cause {
267 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
268 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
269 AVIC_IPI_FAILURE_INVALID_TARGET,
270 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
273 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0)
276 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
277 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
279 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
282 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
284 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
286 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
287 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
289 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
291 #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5)
300 /* Save area definition for legacy and SEV-MEM guests */
301 struct vmcb_save_area {
308 struct vmcb_seg gdtr;
309 struct vmcb_seg ldtr;
310 struct vmcb_seg idtr;
312 /* Reserved fields are named following their struct offset */
313 u8 reserved_0xa0[42];
318 u8 reserved_0xd8[112];
326 u8 reserved_0x180[88];
341 u8 reserved_0x248[32];
348 u8 reserved_0x298[72];
349 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
352 /* Save area definition for SEV-ES and SEV-SNP guests */
353 struct sev_es_save_area {
360 struct vmcb_seg gdtr;
361 struct vmcb_seg ldtr;
362 struct vmcb_seg idtr;
374 u8 reserved_0xd8[104];
391 u8 reserved_0x1c0[24];
406 u8 reserved_0x248[32];
413 u8 reserved_0x298[80];
416 u8 reserved_0x2f0[24];
420 u64 reserved_0x320; /* rsp already available at 0x01d8 */
432 u8 reserved_0x380[16];
433 u64 guest_exit_info_1;
434 u64 guest_exit_info_2;
435 u64 guest_exit_int_info;
445 u8 reserved_0x3f0[16];
447 /* Floating point area */
462 struct ghcb_save_area {
463 u8 reserved_0x0[203];
465 u8 reserved_0xcc[116];
467 u8 reserved_0x148[24];
469 u8 reserved_0x168[16];
471 u8 reserved_0x180[88];
473 u8 reserved_0x1e0[24];
475 u8 reserved_0x200[264];
479 u8 reserved_0x320[8];
491 u8 reserved_0x380[16];
496 u8 reserved_0x3b0[56];
502 #define GHCB_SHARED_BUF_SIZE 2032
505 struct ghcb_save_area save;
506 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
508 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
510 u8 reserved_0xff0[10];
511 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
516 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744
517 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
518 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
519 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
520 #define EXPECTED_GHCB_SIZE PAGE_SIZE
522 #define BUILD_BUG_RESERVED_OFFSET(x, y) \
523 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
525 static inline void __unused_size_checks(void)
527 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
528 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
529 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
530 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
531 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
533 /* Check offsets of reserved fields */
535 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
536 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
537 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
538 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
539 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
540 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
542 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
543 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
544 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
545 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
546 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
547 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
548 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x2f0);
549 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
550 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
551 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
553 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
554 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
555 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
556 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
557 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
558 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
559 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
560 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
561 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
562 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
564 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
568 struct vmcb_control_area control;
569 struct vmcb_save_area save;
572 #define SVM_CPUID_FUNC 0x8000000a
574 #define SVM_VM_CR_SVM_DISABLE 4
576 #define SVM_SELECTOR_S_SHIFT 4
577 #define SVM_SELECTOR_DPL_SHIFT 5
578 #define SVM_SELECTOR_P_SHIFT 7
579 #define SVM_SELECTOR_AVL_SHIFT 8
580 #define SVM_SELECTOR_L_SHIFT 9
581 #define SVM_SELECTOR_DB_SHIFT 10
582 #define SVM_SELECTOR_G_SHIFT 11
584 #define SVM_SELECTOR_TYPE_MASK (0xf)
585 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
586 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
587 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
588 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
589 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
590 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
591 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
593 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
594 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
595 #define SVM_SELECTOR_CODE_MASK (1 << 3)
597 #define SVM_EVTINJ_VEC_MASK 0xff
599 #define SVM_EVTINJ_TYPE_SHIFT 8
600 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
602 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
603 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
604 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
605 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
607 #define SVM_EVTINJ_VALID (1 << 31)
608 #define SVM_EVTINJ_VALID_ERR (1 << 11)
610 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
611 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
613 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
614 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
615 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
616 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
618 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
619 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
621 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
622 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
623 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
625 #define SVM_EXITINFO_REG_MASK 0x0F
627 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
629 /* GHCB Accessor functions */
631 #define GHCB_BITMAP_IDX(field) \
632 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
634 #define DEFINE_GHCB_ACCESSORS(field) \
635 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
637 return test_bit(GHCB_BITMAP_IDX(field), \
638 (unsigned long *)&ghcb->save.valid_bitmap); \
641 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
643 return ghcb->save.field; \
646 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
648 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
651 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
653 __set_bit(GHCB_BITMAP_IDX(field), \
654 (unsigned long *)&ghcb->save.valid_bitmap); \
655 ghcb->save.field = value; \
658 DEFINE_GHCB_ACCESSORS(cpl)
659 DEFINE_GHCB_ACCESSORS(rip)
660 DEFINE_GHCB_ACCESSORS(rsp)
661 DEFINE_GHCB_ACCESSORS(rax)
662 DEFINE_GHCB_ACCESSORS(rcx)
663 DEFINE_GHCB_ACCESSORS(rdx)
664 DEFINE_GHCB_ACCESSORS(rbx)
665 DEFINE_GHCB_ACCESSORS(rbp)
666 DEFINE_GHCB_ACCESSORS(rsi)
667 DEFINE_GHCB_ACCESSORS(rdi)
668 DEFINE_GHCB_ACCESSORS(r8)
669 DEFINE_GHCB_ACCESSORS(r9)
670 DEFINE_GHCB_ACCESSORS(r10)
671 DEFINE_GHCB_ACCESSORS(r11)
672 DEFINE_GHCB_ACCESSORS(r12)
673 DEFINE_GHCB_ACCESSORS(r13)
674 DEFINE_GHCB_ACCESSORS(r14)
675 DEFINE_GHCB_ACCESSORS(r15)
676 DEFINE_GHCB_ACCESSORS(sw_exit_code)
677 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
678 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
679 DEFINE_GHCB_ACCESSORS(sw_scratch)
680 DEFINE_GHCB_ACCESSORS(xcr0)