1 #ifndef _ASM_X86_SPINLOCK_H
2 #define _ASM_X86_SPINLOCK_H
4 #include <linux/atomic.h>
6 #include <asm/processor.h>
7 #include <linux/compiler.h>
8 #include <asm/paravirt.h>
10 * Your basic SMP spinlocks, allowing only a single CPU anywhere
12 * Simple spin lock operations. There are two variants, one clears IRQ's
13 * on the local processor, one does not.
15 * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
17 * (the type definitions are in asm/spinlock_types.h)
21 # define LOCK_PTR_REG "a"
23 # define LOCK_PTR_REG "D"
26 #if defined(CONFIG_X86_32) && \
27 (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
29 * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
30 * (PPro errata 66, 92)
32 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
34 # define UNLOCK_LOCK_PREFIX
37 /* How long a lock should spin before we consider blocking */
38 #define SPIN_THRESHOLD (1 << 15)
40 #ifndef CONFIG_PARAVIRT_SPINLOCKS
42 static __always_inline void __ticket_lock_spinning(struct arch_spinlock *lock,
47 static __always_inline void ____ticket_unlock_kick(struct arch_spinlock *lock,
52 #endif /* CONFIG_PARAVIRT_SPINLOCKS */
56 * If a spinlock has someone waiting on it, then kick the appropriate
59 static __always_inline void __ticket_unlock_kick(struct arch_spinlock *lock,
62 if (unlikely(lock->tickets.tail != next))
63 ____ticket_unlock_kick(lock, next);
67 * Ticket locks are conceptually two parts, one indicating the current head of
68 * the queue, and the other indicating the current tail. The lock is acquired
69 * by atomically noting the tail and incrementing it by one (thus adding
70 * ourself to the queue and noting our position), then waiting until the head
71 * becomes equal to the the initial value of the tail.
73 * We use an xadd covering *both* parts of the lock, to increment the tail and
74 * also load the position of the head, which takes care of memory ordering
75 * issues and should be optimal for the uncontended case. Note the tail must be
76 * in the high part, because a wide xadd increment of the low part would carry
77 * up and contaminate the high part.
79 static __always_inline void arch_spin_lock(struct arch_spinlock *lock)
81 register struct __raw_tickets inc = { .tail = 1 };
83 inc = xadd(&lock->tickets, inc);
86 unsigned count = SPIN_THRESHOLD;
89 if (inc.head == inc.tail)
92 inc.head = ACCESS_ONCE(lock->tickets.head);
94 __ticket_lock_spinning(lock, inc.tail);
96 out: barrier(); /* make sure nothing creeps before the lock is taken */
99 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
101 arch_spinlock_t old, new;
103 old.tickets = ACCESS_ONCE(lock->tickets);
104 if (old.tickets.head != old.tickets.tail)
107 new.head_tail = old.head_tail + (1 << TICKET_SHIFT);
109 /* cmpxchg is a full barrier, so nothing can move before it */
110 return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
113 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
115 __ticket_t next = lock->tickets.head + 1;
117 __add(&lock->tickets.head, 1, UNLOCK_LOCK_PREFIX);
118 __ticket_unlock_kick(lock, next);
121 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
123 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
125 return tmp.tail != tmp.head;
128 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
130 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
132 return (__ticket_t)(tmp.tail - tmp.head) > 1;
134 #define arch_spin_is_contended arch_spin_is_contended
136 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
139 arch_spin_lock(lock);
142 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
144 while (arch_spin_is_locked(lock))
149 * Read-write spinlocks, allowing multiple readers
150 * but only one writer.
152 * NOTE! it is quite common to have readers in interrupts
153 * but no interrupt writers. For those circumstances we
154 * can "mix" irq-safe locks - any writer needs to get a
155 * irq-safe write-lock, but readers can get non-irqsafe
158 * On x86, we implement read-write locks as a 32-bit counter
159 * with the high bit (sign) being the "contended" bit.
163 * read_can_lock - would read_trylock() succeed?
164 * @lock: the rwlock in question.
166 static inline int arch_read_can_lock(arch_rwlock_t *lock)
168 return lock->lock > 0;
172 * write_can_lock - would write_trylock() succeed?
173 * @lock: the rwlock in question.
175 static inline int arch_write_can_lock(arch_rwlock_t *lock)
177 return lock->write == WRITE_LOCK_CMP;
180 static inline void arch_read_lock(arch_rwlock_t *rw)
182 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
184 "call __read_lock_failed\n\t"
186 ::LOCK_PTR_REG (rw) : "memory");
189 static inline void arch_write_lock(arch_rwlock_t *rw)
191 asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
193 "call __write_lock_failed\n\t"
195 ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
199 static inline int arch_read_trylock(arch_rwlock_t *lock)
201 READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
203 if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
205 READ_LOCK_ATOMIC(inc)(count);
209 static inline int arch_write_trylock(arch_rwlock_t *lock)
211 atomic_t *count = (atomic_t *)&lock->write;
213 if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
215 atomic_add(WRITE_LOCK_CMP, count);
219 static inline void arch_read_unlock(arch_rwlock_t *rw)
221 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
222 :"+m" (rw->lock) : : "memory");
225 static inline void arch_write_unlock(arch_rwlock_t *rw)
227 asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
228 : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
231 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
232 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
234 #undef READ_LOCK_SIZE
235 #undef READ_LOCK_ATOMIC
236 #undef WRITE_LOCK_ADD
237 #undef WRITE_LOCK_SUB
238 #undef WRITE_LOCK_CMP
240 #define arch_spin_relax(lock) cpu_relax()
241 #define arch_read_relax(lock) cpu_relax()
242 #define arch_write_relax(lock) cpu_relax()
244 /* The {read|write|spin}_lock() on x86 are full memory barriers. */
245 static inline void smp_mb__after_lock(void) { }
246 #define ARCH_HAS_SMP_MB_AFTER_LOCK
248 #endif /* _ASM_X86_SPINLOCK_H */