1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
38 * Based on this we disable the IP header alignment in network drivers.
40 #define NET_IP_ALIGN 0
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
47 static inline void *current_text_addr(void)
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
89 char wp_works_ok; /* It doesn't on 386's */
91 /* Problems on some 486Dx4's and old 386's: */
98 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
103 /* CPUID returned core id bits: */
104 __u8 x86_coreid_bits;
105 /* Max extended CPUID function supported: */
106 __u32 extended_cpuid_level;
107 /* Maximum supported CPUID level, -1=no CPUID: */
109 __u32 x86_capability[NCAPINTS + NBUGINTS];
110 char x86_vendor_id[16];
111 char x86_model_id[64];
112 /* in KB - valid for CPUS which support this call: */
114 int x86_cache_alignment; /* In bytes */
116 unsigned long loops_per_jiffy;
117 /* cpuid returned max cores value: */
121 u16 x86_clflush_size;
122 /* number of cores as seen by the OS: */
124 /* Physical processor id: */
128 /* Compute unit id */
130 /* Index into per_cpu list: */
133 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
135 #define X86_VENDOR_INTEL 0
136 #define X86_VENDOR_CYRIX 1
137 #define X86_VENDOR_AMD 2
138 #define X86_VENDOR_UMC 3
139 #define X86_VENDOR_CENTAUR 5
140 #define X86_VENDOR_TRANSMETA 7
141 #define X86_VENDOR_NSC 8
142 #define X86_VENDOR_NUM 9
144 #define X86_VENDOR_UNKNOWN 0xff
147 * capabilities of CPUs
149 extern struct cpuinfo_x86 boot_cpu_data;
150 extern struct cpuinfo_x86 new_cpu_data;
152 extern struct tss_struct doublefault_tss;
153 extern __u32 cpu_caps_cleared[NCAPINTS];
154 extern __u32 cpu_caps_set[NCAPINTS];
157 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
158 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
160 #define cpu_info boot_cpu_data
161 #define cpu_data(cpu) boot_cpu_data
164 extern const struct seq_operations cpuinfo_op;
166 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
168 extern void cpu_detect(struct cpuinfo_x86 *c);
170 extern void early_cpu_init(void);
171 extern void identify_boot_cpu(void);
172 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
173 extern void print_cpu_info(struct cpuinfo_x86 *);
174 void print_cpu_msr(struct cpuinfo_x86 *);
175 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
176 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
177 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
179 extern void detect_extended_topology(struct cpuinfo_x86 *c);
180 extern void detect_ht(struct cpuinfo_x86 *c);
183 extern int have_cpuid_p(void);
185 static inline int have_cpuid_p(void)
190 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
191 unsigned int *ecx, unsigned int *edx)
193 /* ecx is often an input as well as an output. */
199 : "0" (*eax), "2" (*ecx)
203 static inline void load_cr3(pgd_t *pgdir)
205 write_cr3(__pa(pgdir));
209 /* This is the TSS defined by the hardware. */
211 unsigned short back_link, __blh;
213 unsigned short ss0, __ss0h;
215 /* ss1 caches MSR_IA32_SYSENTER_CS: */
216 unsigned short ss1, __ss1h;
218 unsigned short ss2, __ss2h;
230 unsigned short es, __esh;
231 unsigned short cs, __csh;
232 unsigned short ss, __ssh;
233 unsigned short ds, __dsh;
234 unsigned short fs, __fsh;
235 unsigned short gs, __gsh;
236 unsigned short ldt, __ldth;
237 unsigned short trace;
238 unsigned short io_bitmap_base;
240 } __attribute__((packed));
254 } __attribute__((packed)) ____cacheline_aligned;
260 #define IO_BITMAP_BITS 65536
261 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
262 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
263 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
264 #define INVALID_IO_BITMAP_OFFSET 0x8000
268 * The hardware state:
270 struct x86_hw_tss x86_tss;
273 * The extra 1 is there because the CPU will access an
274 * additional byte beyond the end of the IO permission
275 * bitmap. The extra byte must be all 1 bits, and must
276 * be within the limit.
278 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
281 * .. and then another 0x100 bytes for the emergency kernel stack:
283 unsigned long stack[64];
285 } ____cacheline_aligned;
287 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
290 * Save the original ist values for checking stack pointers during debugging
293 unsigned long ist[7];
296 #define MXCSR_DEFAULT 0x1f80
298 struct i387_fsave_struct {
299 u32 cwd; /* FPU Control Word */
300 u32 swd; /* FPU Status Word */
301 u32 twd; /* FPU Tag Word */
302 u32 fip; /* FPU IP Offset */
303 u32 fcs; /* FPU IP Selector */
304 u32 foo; /* FPU Operand Pointer Offset */
305 u32 fos; /* FPU Operand Pointer Selector */
307 /* 8*10 bytes for each FP-reg = 80 bytes: */
310 /* Software status information [not touched by FSAVE ]: */
314 struct i387_fxsave_struct {
315 u16 cwd; /* Control Word */
316 u16 swd; /* Status Word */
317 u16 twd; /* Tag Word */
318 u16 fop; /* Last Instruction Opcode */
321 u64 rip; /* Instruction Pointer */
322 u64 rdp; /* Data Pointer */
325 u32 fip; /* FPU IP Offset */
326 u32 fcs; /* FPU IP Selector */
327 u32 foo; /* FPU Operand Offset */
328 u32 fos; /* FPU Operand Selector */
331 u32 mxcsr; /* MXCSR Register State */
332 u32 mxcsr_mask; /* MXCSR Mask */
334 /* 8*16 bytes for each FP-reg = 128 bytes: */
337 /* 16*16 bytes for each XMM-reg = 256 bytes: */
347 } __attribute__((aligned(16)));
349 struct i387_soft_struct {
357 /* 8*10 bytes for each FP-reg = 80 bytes: */
365 struct math_emu_info *info;
370 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
374 struct xsave_hdr_struct {
378 } __attribute__((packed));
380 struct xsave_struct {
381 struct i387_fxsave_struct i387;
382 struct xsave_hdr_struct xsave_hdr;
383 struct ymmh_struct ymmh;
384 /* new processor state extensions will go here */
385 } __attribute__ ((packed, aligned (64)));
387 union thread_xstate {
388 struct i387_fsave_struct fsave;
389 struct i387_fxsave_struct fxsave;
390 struct i387_soft_struct soft;
391 struct xsave_struct xsave;
395 unsigned int last_cpu;
396 unsigned int has_fpu;
397 union thread_xstate *state;
401 DECLARE_PER_CPU(struct orig_ist, orig_ist);
403 union irq_stack_union {
404 char irq_stack[IRQ_STACK_SIZE];
406 * GCC hardcodes the stack canary as %gs:40. Since the
407 * irq_stack is the object at %gs:0, we reserve the bottom
408 * 48 bytes of the irq stack for the canary.
412 unsigned long stack_canary;
416 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
417 DECLARE_INIT_PER_CPU(irq_stack_union);
419 DECLARE_PER_CPU(char *, irq_stack_ptr);
420 DECLARE_PER_CPU(unsigned int, irq_count);
421 extern asmlinkage void ignore_sysret(void);
423 #ifdef CONFIG_CC_STACKPROTECTOR
425 * Make sure stack canary segment base is cached-aligned:
426 * "For Intel Atom processors, avoid non zero segment base address
427 * that is not aligned to cache line boundary at all cost."
428 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
430 struct stack_canary {
431 char __pad[20]; /* canary at %gs:20 */
432 unsigned long canary;
434 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
438 extern unsigned int xstate_size;
439 extern void free_thread_xstate(struct task_struct *);
440 extern struct kmem_cache *task_xstate_cachep;
444 struct thread_struct {
445 /* Cached TLS descriptors: */
446 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
450 unsigned long sysenter_cs;
452 unsigned long usersp; /* Copy from PDA */
455 unsigned short fsindex;
456 unsigned short gsindex;
465 /* Save middle states of ptrace breakpoints */
466 struct perf_event *ptrace_bps[HBP_NUM];
467 /* Debug status used for traps, single steps, etc... */
468 unsigned long debugreg6;
469 /* Keep track of the exact dr7 value set by the user */
470 unsigned long ptrace_dr7;
473 unsigned long trap_nr;
474 unsigned long error_code;
475 /* floating point and extended processor state */
478 /* Virtual 86 mode info */
479 struct vm86_struct __user *vm86_info;
480 unsigned long screen_bitmap;
481 unsigned long v86flags;
482 unsigned long v86mask;
483 unsigned long saved_sp0;
484 unsigned int saved_fs;
485 unsigned int saved_gs;
487 /* IO permissions: */
488 unsigned long *io_bitmap_ptr;
490 /* Max allowed port in the bitmap, in bytes: */
491 unsigned io_bitmap_max;
495 * Set IOPL bits in EFLAGS from given mask
497 static inline void native_set_iopl_mask(unsigned mask)
502 asm volatile ("pushfl;"
509 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
514 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
516 tss->x86_tss.sp0 = thread->sp0;
518 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
519 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
520 tss->x86_tss.ss1 = thread->sysenter_cs;
521 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
526 static inline void native_swapgs(void)
529 asm volatile("swapgs" ::: "memory");
533 #ifdef CONFIG_PARAVIRT
534 #include <asm/paravirt.h>
536 #define __cpuid native_cpuid
537 #define paravirt_enabled() 0
539 static inline void load_sp0(struct tss_struct *tss,
540 struct thread_struct *thread)
542 native_load_sp0(tss, thread);
545 #define set_iopl_mask native_set_iopl_mask
546 #endif /* CONFIG_PARAVIRT */
549 * Save the cr4 feature set we're using (ie
550 * Pentium 4MB enable and PPro Global page
551 * enable), so that any CPU's that boot up
552 * after us can get the correct flags.
554 extern unsigned long mmu_cr4_features;
555 extern u32 *trampoline_cr4_features;
557 static inline void set_in_cr4(unsigned long mask)
561 mmu_cr4_features |= mask;
562 if (trampoline_cr4_features)
563 *trampoline_cr4_features = mmu_cr4_features;
569 static inline void clear_in_cr4(unsigned long mask)
573 mmu_cr4_features &= ~mask;
574 if (trampoline_cr4_features)
575 *trampoline_cr4_features = mmu_cr4_features;
586 /* Free all resources held by a thread. */
587 extern void release_thread(struct task_struct *);
589 unsigned long get_wchan(struct task_struct *p);
592 * Generic CPUID function
593 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
594 * resulting in stale register contents being returned.
596 static inline void cpuid(unsigned int op,
597 unsigned int *eax, unsigned int *ebx,
598 unsigned int *ecx, unsigned int *edx)
602 __cpuid(eax, ebx, ecx, edx);
605 /* Some CPUID calls want 'count' to be placed in ecx */
606 static inline void cpuid_count(unsigned int op, int count,
607 unsigned int *eax, unsigned int *ebx,
608 unsigned int *ecx, unsigned int *edx)
612 __cpuid(eax, ebx, ecx, edx);
616 * CPUID functions returning a single datum
618 static inline unsigned int cpuid_eax(unsigned int op)
620 unsigned int eax, ebx, ecx, edx;
622 cpuid(op, &eax, &ebx, &ecx, &edx);
627 static inline unsigned int cpuid_ebx(unsigned int op)
629 unsigned int eax, ebx, ecx, edx;
631 cpuid(op, &eax, &ebx, &ecx, &edx);
636 static inline unsigned int cpuid_ecx(unsigned int op)
638 unsigned int eax, ebx, ecx, edx;
640 cpuid(op, &eax, &ebx, &ecx, &edx);
645 static inline unsigned int cpuid_edx(unsigned int op)
647 unsigned int eax, ebx, ecx, edx;
649 cpuid(op, &eax, &ebx, &ecx, &edx);
654 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
655 static inline void rep_nop(void)
657 asm volatile("rep; nop" ::: "memory");
660 static inline void cpu_relax(void)
665 /* Stop speculative execution and prefetching of modified code. */
666 static inline void sync_core(void)
672 * Do a CPUID if available, otherwise do a jump. The jump
673 * can conveniently enough be the jump around CPUID.
675 asm volatile("cmpl %2,%1\n\t"
680 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
681 : "ebx", "ecx", "edx", "memory");
684 * CPUID is a barrier to speculative execution.
685 * Prefetched instructions are automatically
686 * invalidated when modified.
691 : "ebx", "ecx", "edx", "memory");
695 static inline void __monitor(const void *eax, unsigned long ecx,
698 /* "monitor %eax, %ecx, %edx;" */
699 asm volatile(".byte 0x0f, 0x01, 0xc8;"
700 :: "a" (eax), "c" (ecx), "d"(edx));
703 static inline void __mwait(unsigned long eax, unsigned long ecx)
705 /* "mwait %eax, %ecx;" */
706 asm volatile(".byte 0x0f, 0x01, 0xc9;"
707 :: "a" (eax), "c" (ecx));
710 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
713 /* "mwait %eax, %ecx;" */
714 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
715 :: "a" (eax), "c" (ecx));
718 extern void select_idle_routine(const struct cpuinfo_x86 *c);
719 extern void init_amd_e400_c1e_mask(void);
721 extern unsigned long boot_option_idle_override;
722 extern bool amd_e400_c1e_detected;
724 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
727 extern void enable_sep_cpu(void);
728 extern int sysenter_setup(void);
730 extern void early_trap_init(void);
731 void early_trap_pf_init(void);
733 /* Defined in head.S */
734 extern struct desc_ptr early_gdt_descr;
736 extern void cpu_set_gdt(int);
737 extern void switch_to_new_gdt(int);
738 extern void load_percpu_segment(int);
739 extern void cpu_init(void);
741 static inline unsigned long get_debugctlmsr(void)
743 unsigned long debugctlmsr = 0;
745 #ifndef CONFIG_X86_DEBUGCTLMSR
746 if (boot_cpu_data.x86 < 6)
749 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
754 static inline void update_debugctlmsr(unsigned long debugctlmsr)
756 #ifndef CONFIG_X86_DEBUGCTLMSR
757 if (boot_cpu_data.x86 < 6)
760 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
763 extern void set_task_blockstep(struct task_struct *task, bool on);
766 * from system description table in BIOS. Mostly for MCA use, but
767 * others may find it useful:
769 extern unsigned int machine_id;
770 extern unsigned int machine_submodel_id;
771 extern unsigned int BIOS_revision;
773 /* Boot loader type from the setup header: */
774 extern int bootloader_type;
775 extern int bootloader_version;
777 extern char ignore_fpu_irq;
779 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
780 #define ARCH_HAS_PREFETCHW
781 #define ARCH_HAS_SPINLOCK_PREFETCH
784 # define BASE_PREFETCH ASM_NOP4
785 # define ARCH_HAS_PREFETCH
787 # define BASE_PREFETCH "prefetcht0 (%1)"
791 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
793 * It's not worth to care about 3dnow prefetches for the K6
794 * because they are microcoded there and very slow.
796 static inline void prefetch(const void *x)
798 alternative_input(BASE_PREFETCH,
805 * 3dnow prefetch to get an exclusive cache line.
806 * Useful for spinlocks to avoid one state transition in the
807 * cache coherency protocol:
809 static inline void prefetchw(const void *x)
811 alternative_input(BASE_PREFETCH,
817 static inline void spin_lock_prefetch(const void *x)
824 * User space process size: 3GB (default).
826 #define TASK_SIZE PAGE_OFFSET
827 #define TASK_SIZE_MAX TASK_SIZE
828 #define STACK_TOP TASK_SIZE
829 #define STACK_TOP_MAX STACK_TOP
831 #define INIT_THREAD { \
832 .sp0 = sizeof(init_stack) + (long)&init_stack, \
834 .sysenter_cs = __KERNEL_CS, \
835 .io_bitmap_ptr = NULL, \
839 * Note that the .io_bitmap member must be extra-big. This is because
840 * the CPU will access an additional byte beyond the end of the IO
841 * permission bitmap. The extra byte must be all 1 bits, and must
842 * be within the limit.
846 .sp0 = sizeof(init_stack) + (long)&init_stack, \
847 .ss0 = __KERNEL_DS, \
848 .ss1 = __KERNEL_CS, \
849 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
851 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
854 extern unsigned long thread_saved_pc(struct task_struct *tsk);
856 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
857 #define KSTK_TOP(info) \
859 unsigned long *__ptr = (unsigned long *)(info); \
860 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
864 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
865 * This is necessary to guarantee that the entire "struct pt_regs"
866 * is accessible even if the CPU haven't stored the SS/ESP registers
867 * on the stack (interrupt gate does not save these registers
868 * when switching to the same priv ring).
869 * Therefore beware: accessing the ss/esp fields of the
870 * "struct pt_regs" is possible, but they may contain the
871 * completely wrong values.
873 #define task_pt_regs(task) \
875 struct pt_regs *__regs__; \
876 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
880 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
884 * User space process size. 47bits minus one guard page.
886 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
888 /* This decides where the kernel will search for a free chunk of vm
889 * space during mmap's.
891 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
892 0xc0000000 : 0xFFFFe000)
894 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
895 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
896 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
897 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
899 #define STACK_TOP TASK_SIZE
900 #define STACK_TOP_MAX TASK_SIZE_MAX
902 #define INIT_THREAD { \
903 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
907 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
911 * Return saved PC of a blocked thread.
912 * What is this good for? it will be always the scheduler or ret_from_fork.
914 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
916 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
917 extern unsigned long KSTK_ESP(struct task_struct *task);
920 * User space RSP while inside the SYSCALL fast path
922 DECLARE_PER_CPU(unsigned long, old_rsp);
924 #endif /* CONFIG_X86_64 */
926 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
927 unsigned long new_sp);
930 * This decides where the kernel will search for a free chunk of vm
931 * space during mmap's.
933 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
935 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
937 /* Get/set a process' ability to use the timestamp counter instruction */
938 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
939 #define SET_TSC_CTL(val) set_tsc_mode((val))
941 extern int get_tsc_mode(unsigned long adr);
942 extern int set_tsc_mode(unsigned int val);
944 extern u16 amd_get_nb_id(int cpu);
950 static inline void get_aperfmperf(struct aperfmperf *am)
952 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
954 rdmsrl(MSR_IA32_APERF, am->aperf);
955 rdmsrl(MSR_IA32_MPERF, am->mperf);
958 #define APERFMPERF_SHIFT 10
961 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
962 struct aperfmperf *new)
964 u64 aperf = new->aperf - old->aperf;
965 u64 mperf = new->mperf - old->mperf;
966 unsigned long ratio = aperf;
968 mperf >>= APERFMPERF_SHIFT;
970 ratio = div64_u64(aperf, mperf);
976 * AMD errata checking
978 #ifdef CONFIG_CPU_SUP_AMD
979 extern const int amd_erratum_383[];
980 extern const int amd_erratum_400[];
981 extern bool cpu_has_amd_erratum(const int *);
983 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
984 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
985 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
986 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
987 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
988 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
989 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
992 #define cpu_has_amd_erratum(x) (false)
993 #endif /* CONFIG_CPU_SUP_AMD */
995 extern unsigned long arch_align_stack(unsigned long sp);
996 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
998 void default_idle(void);
1000 bool xen_set_default_idle(void);
1002 #define xen_set_default_idle 0
1005 void stop_this_cpu(void *dummy);
1007 #endif /* _ASM_X86_PROCESSOR_H */