arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14
  15 #define RETPOLINE_THUNK_SIZE    32
  16
  17 /*
  18  * Fill the CPU return stack buffer.
  19  *
  20  * Each entry in the RSB, if used for a speculative 'ret', contains an
  21  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  22  *
  23  * This is required in various cases for retpoline and IBRS-based
  24  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  25  * eliminate potentially bogus entries from the RSB, and sometimes
  26  * purely to ensure that it doesn't get empty, which on some CPUs would
  27  * allow predictions from other (unwanted!) sources to be used.
  28  *
  29  * We define a CPP macro such that it can be used from both .S files and
  30  * inline assembly. It's possible to do a .macro and then include that
  31  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  32  */
  33
  34 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  35
  36 /*
  37  * Google experimented with loop-unrolling and this turned out to be
  38  * the optimal version - two calls, each with their own speculation
  39  * trap should their return address end up getting used, in a loop.
  40  */
  41 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  42         mov     $(nr/2), reg;                   \
  43 771:                                            \
  44         ANNOTATE_INTRA_FUNCTION_CALL;           \
  45         call    772f;                           \
  46 773:    /* speculation trap */                  \
  47         UNWIND_HINT_EMPTY;                      \
  48         pause;                                  \
  49         lfence;                                 \
  50         jmp     773b;                           \
  51 772:                                            \
  52         ANNOTATE_INTRA_FUNCTION_CALL;           \
  53         call    774f;                           \
  54 775:    /* speculation trap */                  \
  55         UNWIND_HINT_EMPTY;                      \
  56         pause;                                  \
  57         lfence;                                 \
  58         jmp     775b;                           \
  59 774:                                            \
  60         add     $(BITS_PER_LONG/8) * 2, sp;     \
  61         dec     reg;                            \
  62         jnz     771b;
  63
  64 #ifdef __ASSEMBLY__
  65
  66 /*
  67  * This should be used immediately before an indirect jump/call. It tells
  68  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  69  * builds.
  70  */
  71 .macro ANNOTATE_RETPOLINE_SAFE
  72         .Lannotate_\@:
  73         .pushsection .discard.retpoline_safe
  74         _ASM_PTR .Lannotate_\@
  75         .popsection
  76 .endm
  77
  78 /*
  79  * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
  80  * vs RETBleed validation.
  81  */
  82 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
  83
  84 /*
  85  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
  86  * indirect jmp/call which may be susceptible to the Spectre variant 2
  87  * attack.
  88  */
  89 .macro JMP_NOSPEC reg:req
  90 #ifdef CONFIG_RETPOLINE
  91         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
  92                       __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
  93                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
  94 #else
  95         jmp     *%\reg
  96 #endif
  97 .endm
  98
  99 .macro CALL_NOSPEC reg:req
 100 #ifdef CONFIG_RETPOLINE
 101         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
 102                       __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
 103                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
 104 #else
 105         call    *%\reg
 106 #endif
 107 .endm
 108
 109  /*
 110   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 111   * monstrosity above, manually.
 112   */
 113 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 114 #ifdef CONFIG_RETPOLINE
 115         ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
 116         __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
 117 .Lskip_rsb_\@:
 118 #endif
 119 .endm
 120
 121 /*
 122  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
 123  * return thunk isn't mapped into the userspace tables (then again, AMD
 124  * typically has NO_MELTDOWN).
 125  *
 126  * Doesn't clobber any registers but does require a stable stack.
 127  *
 128  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
 129  * where we have a stack but before any RET instruction.
 130  */
 131 .macro UNTRAIN_RET
 132 #ifdef CONFIG_RETPOLINE
 133         ALTERNATIVE "", "call zen_untrain_ret", X86_FEATURE_UNRET
 134 #endif
 135 .endm
 136
 137 #else /* __ASSEMBLY__ */
 138
 139 #define ANNOTATE_RETPOLINE_SAFE                                 \
 140         "999:\n\t"                                              \
 141         ".pushsection .discard.retpoline_safe\n\t"              \
 142         _ASM_PTR " 999b\n\t"                                    \
 143         ".popsection\n\t"
 144
 145 extern void __x86_return_thunk(void);
 146 extern void zen_untrain_ret(void);
 147
 148 #ifdef CONFIG_RETPOLINE
 149
 150 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
 151
 152 #define GEN(reg) \
 153         extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
 154 #include <asm/GEN-for-each-reg.h>
 155 #undef GEN
 156
 157 extern retpoline_thunk_t __x86_indirect_thunk_array[];
 158
 159 #ifdef CONFIG_X86_64
 160
 161 /*
 162  * Inline asm uses the %V modifier which is only in newer GCC
 163  * which is ensured when CONFIG_RETPOLINE is defined.
 164  */
 165 # define CALL_NOSPEC                                            \
 166         ALTERNATIVE_2(                                          \
 167         ANNOTATE_RETPOLINE_SAFE                                 \
 168         "call *%[thunk_target]\n",                              \
 169         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 170         X86_FEATURE_RETPOLINE,                                  \
 171         "lfence;\n"                                             \
 172         ANNOTATE_RETPOLINE_SAFE                                 \
 173         "call *%[thunk_target]\n",                              \
 174         X86_FEATURE_RETPOLINE_LFENCE)
 175
 176 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 177
 178 #else /* CONFIG_X86_32 */
 179 /*
 180  * For i386 we use the original ret-equivalent retpoline, because
 181  * otherwise we'll run out of registers. We don't care about CET
 182  * here, anyway.
 183  */
 184 # define CALL_NOSPEC                                            \
 185         ALTERNATIVE_2(                                          \
 186         ANNOTATE_RETPOLINE_SAFE                                 \
 187         "call *%[thunk_target]\n",                              \
 188         "       jmp    904f;\n"                                 \
 189         "       .align 16\n"                                    \
 190         "901:   call   903f;\n"                                 \
 191         "902:   pause;\n"                                       \
 192         "       lfence;\n"                                      \
 193         "       jmp    902b;\n"                                 \
 194         "       .align 16\n"                                    \
 195         "903:   lea    4(%%esp), %%esp;\n"                      \
 196         "       pushl  %[thunk_target];\n"                      \
 197         "       ret;\n"                                         \
 198         "       .align 16\n"                                    \
 199         "904:   call   901b;\n",                                \
 200         X86_FEATURE_RETPOLINE,                                  \
 201         "lfence;\n"                                             \
 202         ANNOTATE_RETPOLINE_SAFE                                 \
 203         "call *%[thunk_target]\n",                              \
 204         X86_FEATURE_RETPOLINE_LFENCE)
 205
 206 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 207 #endif
 208 #else /* No retpoline for C / inline asm */
 209 # define CALL_NOSPEC "call *%[thunk_target]\n"
 210 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 211 #endif
 212
 213 /* The Spectre V2 mitigation variants */
 214 enum spectre_v2_mitigation {
 215         SPECTRE_V2_NONE,
 216         SPECTRE_V2_RETPOLINE,
 217         SPECTRE_V2_LFENCE,
 218         SPECTRE_V2_EIBRS,
 219         SPECTRE_V2_EIBRS_RETPOLINE,
 220         SPECTRE_V2_EIBRS_LFENCE,
 221         SPECTRE_V2_IBRS,
 222 };
 223
 224 /* The indirect branch speculation control variants */
 225 enum spectre_v2_user_mitigation {
 226         SPECTRE_V2_USER_NONE,
 227         SPECTRE_V2_USER_STRICT,
 228         SPECTRE_V2_USER_STRICT_PREFERRED,
 229         SPECTRE_V2_USER_PRCTL,
 230         SPECTRE_V2_USER_SECCOMP,
 231 };
 232
 233 /* The Speculative Store Bypass disable variants */
 234 enum ssb_mitigation {
 235         SPEC_STORE_BYPASS_NONE,
 236         SPEC_STORE_BYPASS_DISABLE,
 237         SPEC_STORE_BYPASS_PRCTL,
 238         SPEC_STORE_BYPASS_SECCOMP,
 239 };
 240
 241 extern char __indirect_thunk_start[];
 242 extern char __indirect_thunk_end[];
 243
 244 static __always_inline
 245 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 246 {
 247         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 248                 : : "c" (msr),
 249                     "a" ((u32)val),
 250                     "d" ((u32)(val >> 32)),
 251                     [feature] "i" (feature)
 252                 : "memory");
 253 }
 254
 255 static inline void indirect_branch_prediction_barrier(void)
 256 {
 257         u64 val = PRED_CMD_IBPB;
 258
 259         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 260 }
 261
 262 /* The Intel SPEC CTRL MSR base value cache */
 263 extern u64 x86_spec_ctrl_base;
 264 extern void write_spec_ctrl_current(u64 val, bool force);
 265 extern u64 spec_ctrl_current(void);
 266
 267 /*
 268  * With retpoline, we must use IBRS to restrict branch prediction
 269  * before calling into firmware.
 270  *
 271  * (Implemented as CPP macros due to header hell.)
 272  */
 273 #define firmware_restrict_branch_speculation_start()                    \
 274 do {                                                                    \
 275         u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;                  \
 276                                                                         \
 277         preempt_disable();                                              \
 278         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 279                               X86_FEATURE_USE_IBRS_FW);                 \
 280 } while (0)
 281
 282 #define firmware_restrict_branch_speculation_end()                      \
 283 do {                                                                    \
 284         u64 val = x86_spec_ctrl_base;                                   \
 285                                                                         \
 286         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 287                               X86_FEATURE_USE_IBRS_FW);                 \
 288         preempt_enable();                                               \
 289 } while (0)
 290
 291 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 292 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 293 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 294
 295 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 296 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 297
 298 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 299
 300 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 301
 302 #include <asm/segment.h>
 303
 304 /**
 305  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 306  *
 307  * This uses the otherwise unused and obsolete VERW instruction in
 308  * combination with microcode which triggers a CPU buffer flush when the
 309  * instruction is executed.
 310  */
 311 static __always_inline void mds_clear_cpu_buffers(void)
 312 {
 313         static const u16 ds = __KERNEL_DS;
 314
 315         /*
 316          * Has to be the memory-operand variant because only that
 317          * guarantees the CPU buffer flush functionality according to
 318          * documentation. The register-operand variant does not.
 319          * Works with any segment selector, but a valid writable
 320          * data segment is the fastest variant.
 321          *
 322          * "cc" clobber is required because VERW modifies ZF.
 323          */
 324         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 325 }
 326
 327 /**
 328  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 329  *
 330  * Clear CPU buffers if the corresponding static key is enabled
 331  */
 332 static __always_inline void mds_user_clear_cpu_buffers(void)
 333 {
 334         if (static_branch_likely(&mds_user_clear))
 335                 mds_clear_cpu_buffers();
 336 }
 337
 338 /**
 339  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 340  *
 341  * Clear CPU buffers if the corresponding static key is enabled
 342  */
 343 static inline void mds_idle_clear_cpu_buffers(void)
 344 {
 345         if (static_branch_likely(&mds_idle_clear))
 346                 mds_clear_cpu_buffers();
 347 }
 348
 349 #endif /* __ASSEMBLY__ */
 350
 351 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */