arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14
  15 #define RETPOLINE_THUNK_SIZE    32
  16
  17 /*
  18  * Fill the CPU return stack buffer.
  19  *
  20  * Each entry in the RSB, if used for a speculative 'ret', contains an
  21  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  22  *
  23  * This is required in various cases for retpoline and IBRS-based
  24  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  25  * eliminate potentially bogus entries from the RSB, and sometimes
  26  * purely to ensure that it doesn't get empty, which on some CPUs would
  27  * allow predictions from other (unwanted!) sources to be used.
  28  *
  29  * We define a CPP macro such that it can be used from both .S files and
  30  * inline assembly. It's possible to do a .macro and then include that
  31  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  32  */
  33
  34 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  35
  36 /*
  37  * Google experimented with loop-unrolling and this turned out to be
  38  * the optimal version - two calls, each with their own speculation
  39  * trap should their return address end up getting used, in a loop.
  40  */
  41 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  42         mov     $(nr/2), reg;                   \
  43 771:                                            \
  44         ANNOTATE_INTRA_FUNCTION_CALL;           \
  45         call    772f;                           \
  46 773:    /* speculation trap */                  \
  47         UNWIND_HINT_EMPTY;                      \
  48         pause;                                  \
  49         lfence;                                 \
  50         jmp     773b;                           \
  51 772:                                            \
  52         ANNOTATE_INTRA_FUNCTION_CALL;           \
  53         call    774f;                           \
  54 775:    /* speculation trap */                  \
  55         UNWIND_HINT_EMPTY;                      \
  56         pause;                                  \
  57         lfence;                                 \
  58         jmp     775b;                           \
  59 774:                                            \
  60         add     $(BITS_PER_LONG/8) * 2, sp;     \
  61         dec     reg;                            \
  62         jnz     771b;
  63
  64 #ifdef __ASSEMBLY__
  65
  66 /*
  67  * This should be used immediately before an indirect jump/call. It tells
  68  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  69  * builds.
  70  */
  71 .macro ANNOTATE_RETPOLINE_SAFE
  72         .Lannotate_\@:
  73         .pushsection .discard.retpoline_safe
  74         _ASM_PTR .Lannotate_\@
  75         .popsection
  76 .endm
  77
  78 /*
  79  * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
  80  * vs RETBleed validation.
  81  */
  82 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
  83
  84 /*
  85  * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
  86  * eventually turn into it's own annotation.
  87  */
  88 .macro ANNOTATE_UNRET_END
  89 #ifdef CONFIG_DEBUG_ENTRY
  90         ANNOTATE_RETPOLINE_SAFE
  91         nop
  92 #endif
  93 .endm
  94
  95 /*
  96  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
  97  * indirect jmp/call which may be susceptible to the Spectre variant 2
  98  * attack.
  99  */
 100 .macro JMP_NOSPEC reg:req
 101 #ifdef CONFIG_RETPOLINE
 102         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
 103                       __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
 104                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
 105 #else
 106         jmp     *%\reg
 107 #endif
 108 .endm
 109
 110 .macro CALL_NOSPEC reg:req
 111 #ifdef CONFIG_RETPOLINE
 112         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
 113                       __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
 114                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
 115 #else
 116         call    *%\reg
 117 #endif
 118 .endm
 119
 120  /*
 121   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 122   * monstrosity above, manually.
 123   */
 124 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 125         ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
 126         __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
 127 .Lskip_rsb_\@:
 128 .endm
 129
 130 #ifdef CONFIG_CPU_UNRET_ENTRY
 131 #define CALL_ZEN_UNTRAIN_RET    "call zen_untrain_ret"
 132 #else
 133 #define CALL_ZEN_UNTRAIN_RET    ""
 134 #endif
 135
 136 /*
 137  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
 138  * return thunk isn't mapped into the userspace tables (then again, AMD
 139  * typically has NO_MELTDOWN).
 140  *
 141  * While zen_untrain_ret() doesn't clobber anything but requires stack,
 142  * entry_ibpb() will clobber AX, CX, DX.
 143  *
 144  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
 145  * where we have a stack but before any RET instruction.
 146  */
 147 .macro UNTRAIN_RET
 148 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY)
 149         ANNOTATE_UNRET_END
 150         ALTERNATIVE_2 "",                                               \
 151                       CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET,          \
 152                       "call entry_ibpb", X86_FEATURE_ENTRY_IBPB
 153 #endif
 154 .endm
 155
 156 #else /* __ASSEMBLY__ */
 157
 158 #define ANNOTATE_RETPOLINE_SAFE                                 \
 159         "999:\n\t"                                              \
 160         ".pushsection .discard.retpoline_safe\n\t"              \
 161         _ASM_PTR " 999b\n\t"                                    \
 162         ".popsection\n\t"
 163
 164 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
 165 extern retpoline_thunk_t __x86_indirect_thunk_array[];
 166
 167 extern void __x86_return_thunk(void);
 168 extern void zen_untrain_ret(void);
 169 extern void entry_ibpb(void);
 170
 171 #ifdef CONFIG_RETPOLINE
 172
 173 #define GEN(reg) \
 174         extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
 175 #include <asm/GEN-for-each-reg.h>
 176 #undef GEN
 177
 178 #ifdef CONFIG_X86_64
 179
 180 /*
 181  * Inline asm uses the %V modifier which is only in newer GCC
 182  * which is ensured when CONFIG_RETPOLINE is defined.
 183  */
 184 # define CALL_NOSPEC                                            \
 185         ALTERNATIVE_2(                                          \
 186         ANNOTATE_RETPOLINE_SAFE                                 \
 187         "call *%[thunk_target]\n",                              \
 188         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 189         X86_FEATURE_RETPOLINE,                                  \
 190         "lfence;\n"                                             \
 191         ANNOTATE_RETPOLINE_SAFE                                 \
 192         "call *%[thunk_target]\n",                              \
 193         X86_FEATURE_RETPOLINE_LFENCE)
 194
 195 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 196
 197 #else /* CONFIG_X86_32 */
 198 /*
 199  * For i386 we use the original ret-equivalent retpoline, because
 200  * otherwise we'll run out of registers. We don't care about CET
 201  * here, anyway.
 202  */
 203 # define CALL_NOSPEC                                            \
 204         ALTERNATIVE_2(                                          \
 205         ANNOTATE_RETPOLINE_SAFE                                 \
 206         "call *%[thunk_target]\n",                              \
 207         "       jmp    904f;\n"                                 \
 208         "       .align 16\n"                                    \
 209         "901:   call   903f;\n"                                 \
 210         "902:   pause;\n"                                       \
 211         "       lfence;\n"                                      \
 212         "       jmp    902b;\n"                                 \
 213         "       .align 16\n"                                    \
 214         "903:   lea    4(%%esp), %%esp;\n"                      \
 215         "       pushl  %[thunk_target];\n"                      \
 216         "       ret;\n"                                         \
 217         "       .align 16\n"                                    \
 218         "904:   call   901b;\n",                                \
 219         X86_FEATURE_RETPOLINE,                                  \
 220         "lfence;\n"                                             \
 221         ANNOTATE_RETPOLINE_SAFE                                 \
 222         "call *%[thunk_target]\n",                              \
 223         X86_FEATURE_RETPOLINE_LFENCE)
 224
 225 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 226 #endif
 227 #else /* No retpoline for C / inline asm */
 228 # define CALL_NOSPEC "call *%[thunk_target]\n"
 229 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 230 #endif
 231
 232 /* The Spectre V2 mitigation variants */
 233 enum spectre_v2_mitigation {
 234         SPECTRE_V2_NONE,
 235         SPECTRE_V2_RETPOLINE,
 236         SPECTRE_V2_LFENCE,
 237         SPECTRE_V2_EIBRS,
 238         SPECTRE_V2_EIBRS_RETPOLINE,
 239         SPECTRE_V2_EIBRS_LFENCE,
 240         SPECTRE_V2_IBRS,
 241 };
 242
 243 /* The indirect branch speculation control variants */
 244 enum spectre_v2_user_mitigation {
 245         SPECTRE_V2_USER_NONE,
 246         SPECTRE_V2_USER_STRICT,
 247         SPECTRE_V2_USER_STRICT_PREFERRED,
 248         SPECTRE_V2_USER_PRCTL,
 249         SPECTRE_V2_USER_SECCOMP,
 250 };
 251
 252 /* The Speculative Store Bypass disable variants */
 253 enum ssb_mitigation {
 254         SPEC_STORE_BYPASS_NONE,
 255         SPEC_STORE_BYPASS_DISABLE,
 256         SPEC_STORE_BYPASS_PRCTL,
 257         SPEC_STORE_BYPASS_SECCOMP,
 258 };
 259
 260 extern char __indirect_thunk_start[];
 261 extern char __indirect_thunk_end[];
 262
 263 static __always_inline
 264 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 265 {
 266         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 267                 : : "c" (msr),
 268                     "a" ((u32)val),
 269                     "d" ((u32)(val >> 32)),
 270                     [feature] "i" (feature)
 271                 : "memory");
 272 }
 273
 274 static inline void indirect_branch_prediction_barrier(void)
 275 {
 276         u64 val = PRED_CMD_IBPB;
 277
 278         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 279 }
 280
 281 /* The Intel SPEC CTRL MSR base value cache */
 282 extern u64 x86_spec_ctrl_base;
 283 extern u64 x86_spec_ctrl_current;
 284 extern void write_spec_ctrl_current(u64 val, bool force);
 285 extern u64 spec_ctrl_current(void);
 286
 287 /*
 288  * With retpoline, we must use IBRS to restrict branch prediction
 289  * before calling into firmware.
 290  *
 291  * (Implemented as CPP macros due to header hell.)
 292  */
 293 #define firmware_restrict_branch_speculation_start()                    \
 294 do {                                                                    \
 295         preempt_disable();                                              \
 296         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 297                               spec_ctrl_current() | SPEC_CTRL_IBRS,     \
 298                               X86_FEATURE_USE_IBRS_FW);                 \
 299 } while (0)
 300
 301 #define firmware_restrict_branch_speculation_end()                      \
 302 do {                                                                    \
 303         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 304                               spec_ctrl_current(),                      \
 305                               X86_FEATURE_USE_IBRS_FW);                 \
 306         preempt_enable();                                               \
 307 } while (0)
 308
 309 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 310 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 311 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 312
 313 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 314 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 315
 316 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 317
 318 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 319
 320 #include <asm/segment.h>
 321
 322 /**
 323  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 324  *
 325  * This uses the otherwise unused and obsolete VERW instruction in
 326  * combination with microcode which triggers a CPU buffer flush when the
 327  * instruction is executed.
 328  */
 329 static __always_inline void mds_clear_cpu_buffers(void)
 330 {
 331         static const u16 ds = __KERNEL_DS;
 332
 333         /*
 334          * Has to be the memory-operand variant because only that
 335          * guarantees the CPU buffer flush functionality according to
 336          * documentation. The register-operand variant does not.
 337          * Works with any segment selector, but a valid writable
 338          * data segment is the fastest variant.
 339          *
 340          * "cc" clobber is required because VERW modifies ZF.
 341          */
 342         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 343 }
 344
 345 /**
 346  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 347  *
 348  * Clear CPU buffers if the corresponding static key is enabled
 349  */
 350 static __always_inline void mds_user_clear_cpu_buffers(void)
 351 {
 352         if (static_branch_likely(&mds_user_clear))
 353                 mds_clear_cpu_buffers();
 354 }
 355
 356 /**
 357  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 358  *
 359  * Clear CPU buffers if the corresponding static key is enabled
 360  */
 361 static inline void mds_idle_clear_cpu_buffers(void)
 362 {
 363         if (static_branch_likely(&mds_idle_clear))
 364                 mds_clear_cpu_buffers();
 365 }
 366
 367 #endif /* __ASSEMBLY__ */
 368
 369 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */