1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
15 #define RETPOLINE_THUNK_SIZE 32
18 * Fill the CPU return stack buffer.
20 * Each entry in the RSB, if used for a speculative 'ret', contains an
21 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
23 * This is required in various cases for retpoline and IBRS-based
24 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
25 * eliminate potentially bogus entries from the RSB, and sometimes
26 * purely to ensure that it doesn't get empty, which on some CPUs would
27 * allow predictions from other (unwanted!) sources to be used.
29 * We define a CPP macro such that it can be used from both .S files and
30 * inline assembly. It's possible to do a .macro and then include that
31 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
34 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
37 * Google experimented with loop-unrolling and this turned out to be
38 * the optimal version - two calls, each with their own speculation
39 * trap should their return address end up getting used, in a loop.
41 #define __FILL_RETURN_BUFFER(reg, nr, sp) \
44 ANNOTATE_INTRA_FUNCTION_CALL; \
46 773: /* speculation trap */ \
52 ANNOTATE_INTRA_FUNCTION_CALL; \
54 775: /* speculation trap */ \
60 add $(BITS_PER_LONG/8) * 2, sp; \
67 * This should be used immediately before an indirect jump/call. It tells
68 * objtool the subsequent indirect jump/call is vouched safe for retpoline
71 .macro ANNOTATE_RETPOLINE_SAFE
73 .pushsection .discard.retpoline_safe
74 _ASM_PTR .Lannotate_\@
79 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
80 * vs RETBleed validation.
82 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
85 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
86 * eventually turn into it's own annotation.
88 .macro ANNOTATE_UNRET_END
89 #ifdef CONFIG_DEBUG_ENTRY
90 ANNOTATE_RETPOLINE_SAFE
96 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
97 * indirect jmp/call which may be susceptible to the Spectre variant 2
100 .macro JMP_NOSPEC reg:req
101 #ifdef CONFIG_RETPOLINE
102 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
103 __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
104 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
110 .macro CALL_NOSPEC reg:req
111 #ifdef CONFIG_RETPOLINE
112 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
113 __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
114 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
121 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
122 * monstrosity above, manually.
124 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
125 ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
126 __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
130 #ifdef CONFIG_CPU_UNRET_ENTRY
131 #define CALL_ZEN_UNTRAIN_RET "call zen_untrain_ret"
133 #define CALL_ZEN_UNTRAIN_RET ""
137 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
138 * return thunk isn't mapped into the userspace tables (then again, AMD
139 * typically has NO_MELTDOWN).
141 * While zen_untrain_ret() doesn't clobber anything but requires stack,
142 * entry_ibpb() will clobber AX, CX, DX.
144 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
145 * where we have a stack but before any RET instruction.
148 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY)
151 CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \
152 "call entry_ibpb", X86_FEATURE_ENTRY_IBPB
156 #else /* __ASSEMBLY__ */
158 #define ANNOTATE_RETPOLINE_SAFE \
160 ".pushsection .discard.retpoline_safe\n\t" \
161 _ASM_PTR " 999b\n\t" \
164 extern void __x86_return_thunk(void);
165 extern void zen_untrain_ret(void);
166 extern void entry_ibpb(void);
168 #ifdef CONFIG_RETPOLINE
170 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
173 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
174 #include <asm/GEN-for-each-reg.h>
177 extern retpoline_thunk_t __x86_indirect_thunk_array[];
182 * Inline asm uses the %V modifier which is only in newer GCC
183 * which is ensured when CONFIG_RETPOLINE is defined.
185 # define CALL_NOSPEC \
187 ANNOTATE_RETPOLINE_SAFE \
188 "call *%[thunk_target]\n", \
189 "call __x86_indirect_thunk_%V[thunk_target]\n", \
190 X86_FEATURE_RETPOLINE, \
192 ANNOTATE_RETPOLINE_SAFE \
193 "call *%[thunk_target]\n", \
194 X86_FEATURE_RETPOLINE_LFENCE)
196 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
198 #else /* CONFIG_X86_32 */
200 * For i386 we use the original ret-equivalent retpoline, because
201 * otherwise we'll run out of registers. We don't care about CET
204 # define CALL_NOSPEC \
206 ANNOTATE_RETPOLINE_SAFE \
207 "call *%[thunk_target]\n", \
210 "901: call 903f;\n" \
215 "903: lea 4(%%esp), %%esp;\n" \
216 " pushl %[thunk_target];\n" \
219 "904: call 901b;\n", \
220 X86_FEATURE_RETPOLINE, \
222 ANNOTATE_RETPOLINE_SAFE \
223 "call *%[thunk_target]\n", \
224 X86_FEATURE_RETPOLINE_LFENCE)
226 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
228 #else /* No retpoline for C / inline asm */
229 # define CALL_NOSPEC "call *%[thunk_target]\n"
230 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
233 /* The Spectre V2 mitigation variants */
234 enum spectre_v2_mitigation {
236 SPECTRE_V2_RETPOLINE,
239 SPECTRE_V2_EIBRS_RETPOLINE,
240 SPECTRE_V2_EIBRS_LFENCE,
244 /* The indirect branch speculation control variants */
245 enum spectre_v2_user_mitigation {
246 SPECTRE_V2_USER_NONE,
247 SPECTRE_V2_USER_STRICT,
248 SPECTRE_V2_USER_STRICT_PREFERRED,
249 SPECTRE_V2_USER_PRCTL,
250 SPECTRE_V2_USER_SECCOMP,
253 /* The Speculative Store Bypass disable variants */
254 enum ssb_mitigation {
255 SPEC_STORE_BYPASS_NONE,
256 SPEC_STORE_BYPASS_DISABLE,
257 SPEC_STORE_BYPASS_PRCTL,
258 SPEC_STORE_BYPASS_SECCOMP,
261 extern char __indirect_thunk_start[];
262 extern char __indirect_thunk_end[];
264 static __always_inline
265 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
267 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
270 "d" ((u32)(val >> 32)),
271 [feature] "i" (feature)
275 static inline void indirect_branch_prediction_barrier(void)
277 u64 val = PRED_CMD_IBPB;
279 alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
282 /* The Intel SPEC CTRL MSR base value cache */
283 extern u64 x86_spec_ctrl_base;
284 extern u64 x86_spec_ctrl_current;
285 extern void write_spec_ctrl_current(u64 val, bool force);
286 extern u64 spec_ctrl_current(void);
289 * With retpoline, we must use IBRS to restrict branch prediction
290 * before calling into firmware.
292 * (Implemented as CPP macros due to header hell.)
294 #define firmware_restrict_branch_speculation_start() \
297 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
298 spec_ctrl_current() | SPEC_CTRL_IBRS, \
299 X86_FEATURE_USE_IBRS_FW); \
302 #define firmware_restrict_branch_speculation_end() \
304 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
305 spec_ctrl_current(), \
306 X86_FEATURE_USE_IBRS_FW); \
310 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
311 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
312 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
314 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
315 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
317 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
319 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
321 #include <asm/segment.h>
324 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
326 * This uses the otherwise unused and obsolete VERW instruction in
327 * combination with microcode which triggers a CPU buffer flush when the
328 * instruction is executed.
330 static __always_inline void mds_clear_cpu_buffers(void)
332 static const u16 ds = __KERNEL_DS;
335 * Has to be the memory-operand variant because only that
336 * guarantees the CPU buffer flush functionality according to
337 * documentation. The register-operand variant does not.
338 * Works with any segment selector, but a valid writable
339 * data segment is the fastest variant.
341 * "cc" clobber is required because VERW modifies ZF.
343 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
347 * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
349 * Clear CPU buffers if the corresponding static key is enabled
351 static __always_inline void mds_user_clear_cpu_buffers(void)
353 if (static_branch_likely(&mds_user_clear))
354 mds_clear_cpu_buffers();
358 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
360 * Clear CPU buffers if the corresponding static key is enabled
362 static inline void mds_idle_clear_cpu_buffers(void)
364 if (static_branch_likely(&mds_idle_clear))
365 mds_clear_cpu_buffers();
368 #endif /* __ASSEMBLY__ */
370 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */