arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14
  15 /*
  16  * Fill the CPU return stack buffer.
  17  *
  18  * Each entry in the RSB, if used for a speculative 'ret', contains an
  19  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  20  *
  21  * This is required in various cases for retpoline and IBRS-based
  22  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  23  * eliminate potentially bogus entries from the RSB, and sometimes
  24  * purely to ensure that it doesn't get empty, which on some CPUs would
  25  * allow predictions from other (unwanted!) sources to be used.
  26  *
  27  * We define a CPP macro such that it can be used from both .S files and
  28  * inline assembly. It's possible to do a .macro and then include that
  29  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  30  */
  31
  32 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  33
  34 /*
  35  * Google experimented with loop-unrolling and this turned out to be
  36  * the optimal version - two calls, each with their own speculation
  37  * trap should their return address end up getting used, in a loop.
  38  */
  39 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  40         mov     $(nr/2), reg;                   \
  41 771:                                            \
  42         ANNOTATE_INTRA_FUNCTION_CALL;           \
  43         call    772f;                           \
  44 773:    /* speculation trap */                  \
  45         UNWIND_HINT_EMPTY;                      \
  46         pause;                                  \
  47         lfence;                                 \
  48         jmp     773b;                           \
  49 772:                                            \
  50         ANNOTATE_INTRA_FUNCTION_CALL;           \
  51         call    774f;                           \
  52 775:    /* speculation trap */                  \
  53         UNWIND_HINT_EMPTY;                      \
  54         pause;                                  \
  55         lfence;                                 \
  56         jmp     775b;                           \
  57 774:                                            \
  58         add     $(BITS_PER_LONG/8) * 2, sp;     \
  59         dec     reg;                            \
  60         jnz     771b;
  61
  62 #ifdef __ASSEMBLY__
  63
  64 /*
  65  * This should be used immediately before an indirect jump/call. It tells
  66  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  67  * builds.
  68  */
  69 .macro ANNOTATE_RETPOLINE_SAFE
  70         .Lannotate_\@:
  71         .pushsection .discard.retpoline_safe
  72         _ASM_PTR .Lannotate_\@
  73         .popsection
  74 .endm
  75
  76 /*
  77  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
  78  * indirect jmp/call which may be susceptible to the Spectre variant 2
  79  * attack.
  80  */
  81 .macro JMP_NOSPEC reg:req
  82 #ifdef CONFIG_RETPOLINE
  83         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
  84                       __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
  85                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
  86 #else
  87         jmp     *%\reg
  88 #endif
  89 .endm
  90
  91 .macro CALL_NOSPEC reg:req
  92 #ifdef CONFIG_RETPOLINE
  93         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
  94                       __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
  95                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
  96 #else
  97         call    *%\reg
  98 #endif
  99 .endm
 100
 101  /*
 102   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 103   * monstrosity above, manually.
 104   */
 105 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 106 #ifdef CONFIG_RETPOLINE
 107         ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
 108         __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
 109 .Lskip_rsb_\@:
 110 #endif
 111 .endm
 112
 113 #else /* __ASSEMBLY__ */
 114
 115 #define ANNOTATE_RETPOLINE_SAFE                                 \
 116         "999:\n\t"                                              \
 117         ".pushsection .discard.retpoline_safe\n\t"              \
 118         _ASM_PTR " 999b\n\t"                                    \
 119         ".popsection\n\t"
 120
 121 #ifdef CONFIG_RETPOLINE
 122
 123 #define GEN(reg) \
 124         extern asmlinkage void __x86_indirect_thunk_ ## reg (void);
 125 #include <asm/GEN-for-each-reg.h>
 126 #undef GEN
 127
 128 #ifdef CONFIG_X86_64
 129
 130 /*
 131  * Inline asm uses the %V modifier which is only in newer GCC
 132  * which is ensured when CONFIG_RETPOLINE is defined.
 133  */
 134 # define CALL_NOSPEC                                            \
 135         ALTERNATIVE_2(                                          \
 136         ANNOTATE_RETPOLINE_SAFE                                 \
 137         "call *%[thunk_target]\n",                              \
 138         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 139         X86_FEATURE_RETPOLINE,                                  \
 140         "lfence;\n"                                             \
 141         ANNOTATE_RETPOLINE_SAFE                                 \
 142         "call *%[thunk_target]\n",                              \
 143         X86_FEATURE_RETPOLINE_LFENCE)
 144
 145 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 146
 147 #else /* CONFIG_X86_32 */
 148 /*
 149  * For i386 we use the original ret-equivalent retpoline, because
 150  * otherwise we'll run out of registers. We don't care about CET
 151  * here, anyway.
 152  */
 153 # define CALL_NOSPEC                                            \
 154         ALTERNATIVE_2(                                          \
 155         ANNOTATE_RETPOLINE_SAFE                                 \
 156         "call *%[thunk_target]\n",                              \
 157         "       jmp    904f;\n"                                 \
 158         "       .align 16\n"                                    \
 159         "901:   call   903f;\n"                                 \
 160         "902:   pause;\n"                                       \
 161         "       lfence;\n"                                      \
 162         "       jmp    902b;\n"                                 \
 163         "       .align 16\n"                                    \
 164         "903:   lea    4(%%esp), %%esp;\n"                      \
 165         "       pushl  %[thunk_target];\n"                      \
 166         "       ret;\n"                                         \
 167         "       .align 16\n"                                    \
 168         "904:   call   901b;\n",                                \
 169         X86_FEATURE_RETPOLINE,                                  \
 170         "lfence;\n"                                             \
 171         ANNOTATE_RETPOLINE_SAFE                                 \
 172         "call *%[thunk_target]\n",                              \
 173         X86_FEATURE_RETPOLINE_LFENCE)
 174
 175 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 176 #endif
 177 #else /* No retpoline for C / inline asm */
 178 # define CALL_NOSPEC "call *%[thunk_target]\n"
 179 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 180 #endif
 181
 182 /* The Spectre V2 mitigation variants */
 183 enum spectre_v2_mitigation {
 184         SPECTRE_V2_NONE,
 185         SPECTRE_V2_RETPOLINE,
 186         SPECTRE_V2_LFENCE,
 187         SPECTRE_V2_EIBRS,
 188         SPECTRE_V2_EIBRS_RETPOLINE,
 189         SPECTRE_V2_EIBRS_LFENCE,
 190 };
 191
 192 /* The indirect branch speculation control variants */
 193 enum spectre_v2_user_mitigation {
 194         SPECTRE_V2_USER_NONE,
 195         SPECTRE_V2_USER_STRICT,
 196         SPECTRE_V2_USER_STRICT_PREFERRED,
 197         SPECTRE_V2_USER_PRCTL,
 198         SPECTRE_V2_USER_SECCOMP,
 199 };
 200
 201 /* The Speculative Store Bypass disable variants */
 202 enum ssb_mitigation {
 203         SPEC_STORE_BYPASS_NONE,
 204         SPEC_STORE_BYPASS_DISABLE,
 205         SPEC_STORE_BYPASS_PRCTL,
 206         SPEC_STORE_BYPASS_SECCOMP,
 207 };
 208
 209 extern char __indirect_thunk_start[];
 210 extern char __indirect_thunk_end[];
 211
 212 static __always_inline
 213 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 214 {
 215         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 216                 : : "c" (msr),
 217                     "a" ((u32)val),
 218                     "d" ((u32)(val >> 32)),
 219                     [feature] "i" (feature)
 220                 : "memory");
 221 }
 222
 223 static inline void indirect_branch_prediction_barrier(void)
 224 {
 225         u64 val = PRED_CMD_IBPB;
 226
 227         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 228 }
 229
 230 /* The Intel SPEC CTRL MSR base value cache */
 231 extern u64 x86_spec_ctrl_base;
 232
 233 /*
 234  * With retpoline, we must use IBRS to restrict branch prediction
 235  * before calling into firmware.
 236  *
 237  * (Implemented as CPP macros due to header hell.)
 238  */
 239 #define firmware_restrict_branch_speculation_start()                    \
 240 do {                                                                    \
 241         u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;                  \
 242                                                                         \
 243         preempt_disable();                                              \
 244         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 245                               X86_FEATURE_USE_IBRS_FW);                 \
 246 } while (0)
 247
 248 #define firmware_restrict_branch_speculation_end()                      \
 249 do {                                                                    \
 250         u64 val = x86_spec_ctrl_base;                                   \
 251                                                                         \
 252         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 253                               X86_FEATURE_USE_IBRS_FW);                 \
 254         preempt_enable();                                               \
 255 } while (0)
 256
 257 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 258 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 259 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 260
 261 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 262 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 263
 264 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 265
 266 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 267
 268 #include <asm/segment.h>
 269
 270 /**
 271  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 272  *
 273  * This uses the otherwise unused and obsolete VERW instruction in
 274  * combination with microcode which triggers a CPU buffer flush when the
 275  * instruction is executed.
 276  */
 277 static __always_inline void mds_clear_cpu_buffers(void)
 278 {
 279         static const u16 ds = __KERNEL_DS;
 280
 281         /*
 282          * Has to be the memory-operand variant because only that
 283          * guarantees the CPU buffer flush functionality according to
 284          * documentation. The register-operand variant does not.
 285          * Works with any segment selector, but a valid writable
 286          * data segment is the fastest variant.
 287          *
 288          * "cc" clobber is required because VERW modifies ZF.
 289          */
 290         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 291 }
 292
 293 /**
 294  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 295  *
 296  * Clear CPU buffers if the corresponding static key is enabled
 297  */
 298 static __always_inline void mds_user_clear_cpu_buffers(void)
 299 {
 300         if (static_branch_likely(&mds_user_clear))
 301                 mds_clear_cpu_buffers();
 302 }
 303
 304 /**
 305  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 306  *
 307  * Clear CPU buffers if the corresponding static key is enabled
 308  */
 309 static inline void mds_idle_clear_cpu_buffers(void)
 310 {
 311         if (static_branch_likely(&mds_idle_clear))
 312                 mds_clear_cpu_buffers();
 313 }
 314
 315 #endif /* __ASSEMBLY__ */
 316
 317 /*
 318  * Below is used in the eBPF JIT compiler and emits the byte sequence
 319  * for the following assembly:
 320  *
 321  * With retpolines configured:
 322  *
 323  *    callq do_rop
 324  *  spec_trap:
 325  *    pause
 326  *    lfence
 327  *    jmp spec_trap
 328  *  do_rop:
 329  *    mov %rcx,(%rsp) for x86_64
 330  *    mov %edx,(%esp) for x86_32
 331  *    retq
 332  *
 333  * Without retpolines configured:
 334  *
 335  *    jmp *%rcx for x86_64
 336  *    jmp *%edx for x86_32
 337  */
 338 #ifdef CONFIG_RETPOLINE
 339 # ifdef CONFIG_X86_64
 340 #  define RETPOLINE_RCX_BPF_JIT_SIZE    17
 341 #  define RETPOLINE_RCX_BPF_JIT()                               \
 342 do {                                                            \
 343         EMIT1_off32(0xE8, 7);    /* callq do_rop */             \
 344         /* spec_trap: */                                        \
 345         EMIT2(0xF3, 0x90);       /* pause */                    \
 346         EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
 347         EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
 348         /* do_rop: */                                           \
 349         EMIT4(0x48, 0x89, 0x0C, 0x24); /* mov %rcx,(%rsp) */    \
 350         EMIT1(0xC3);             /* retq */                     \
 351 } while (0)
 352 # else /* !CONFIG_X86_64 */
 353 #  define RETPOLINE_EDX_BPF_JIT()                               \
 354 do {                                                            \
 355         EMIT1_off32(0xE8, 7);    /* call do_rop */              \
 356         /* spec_trap: */                                        \
 357         EMIT2(0xF3, 0x90);       /* pause */                    \
 358         EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
 359         EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
 360         /* do_rop: */                                           \
 361         EMIT3(0x89, 0x14, 0x24); /* mov %edx,(%esp) */          \
 362         EMIT1(0xC3);             /* ret */                      \
 363 } while (0)
 364 # endif
 365 #else /* !CONFIG_RETPOLINE */
 366 # ifdef CONFIG_X86_64
 367 #  define RETPOLINE_RCX_BPF_JIT_SIZE    2
 368 #  define RETPOLINE_RCX_BPF_JIT()                               \
 369         EMIT2(0xFF, 0xE1);       /* jmp *%rcx */
 370 # else /* !CONFIG_X86_64 */
 371 #  define RETPOLINE_EDX_BPF_JIT()                               \
 372         EMIT2(0xFF, 0xE2)        /* jmp *%edx */
 373 # endif
 374 #endif
 375
 376 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */