arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <asm/alternative.h>
   7 #include <asm/alternative-asm.h>
   8 #include <asm/cpufeatures.h>
   9 #include <asm/msr-index.h>
  10
  11 /*
  12  * Fill the CPU return stack buffer.
  13  *
  14  * Each entry in the RSB, if used for a speculative 'ret', contains an
  15  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  16  *
  17  * This is required in various cases for retpoline and IBRS-based
  18  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  19  * eliminate potentially bogus entries from the RSB, and sometimes
  20  * purely to ensure that it doesn't get empty, which on some CPUs would
  21  * allow predictions from other (unwanted!) sources to be used.
  22  *
  23  * We define a CPP macro such that it can be used from both .S files and
  24  * inline assembly. It's possible to do a .macro and then include that
  25  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  26  */
  27
  28 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  29 #define RSB_FILL_LOOPS          16      /* To avoid underflow */
  30
  31 /*
  32  * Google experimented with loop-unrolling and this turned out to be
  33  * the optimal version — two calls, each with their own speculation
  34  * trap should their return address end up getting used, in a loop.
  35  */
  36 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  37         mov     $(nr/2), reg;                   \
  38 771:                                            \
  39         call    772f;                           \
  40 773:    /* speculation trap */                  \
  41         pause;                                  \
  42         lfence;                                 \
  43         jmp     773b;                           \
  44 772:                                            \
  45         call    774f;                           \
  46 775:    /* speculation trap */                  \
  47         pause;                                  \
  48         lfence;                                 \
  49         jmp     775b;                           \
  50 774:                                            \
  51         dec     reg;                            \
  52         jnz     771b;                           \
  53         add     $(BITS_PER_LONG/8) * nr, sp;
  54
  55 #ifdef __ASSEMBLY__
  56
  57 /*
  58  * This should be used immediately before a retpoline alternative.  It tells
  59  * objtool where the retpolines are so that it can make sense of the control
  60  * flow by just reading the original instruction(s) and ignoring the
  61  * alternatives.
  62  */
  63 .macro ANNOTATE_NOSPEC_ALTERNATIVE
  64         .Lannotate_\@:
  65         .pushsection .discard.nospec
  66         .long .Lannotate_\@ - .
  67         .popsection
  68 .endm
  69
  70 /*
  71  * This should be used immediately before an indirect jump/call. It tells
  72  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  73  * builds.
  74  */
  75 .macro ANNOTATE_RETPOLINE_SAFE
  76         .Lannotate_\@:
  77         .pushsection .discard.retpoline_safe
  78         _ASM_PTR .Lannotate_\@
  79         .popsection
  80 .endm
  81
  82 /*
  83  * These are the bare retpoline primitives for indirect jmp and call.
  84  * Do not use these directly; they only exist to make the ALTERNATIVE
  85  * invocation below less ugly.
  86  */
  87 .macro RETPOLINE_JMP reg:req
  88         call    .Ldo_rop_\@
  89 .Lspec_trap_\@:
  90         pause
  91         lfence
  92         jmp     .Lspec_trap_\@
  93 .Ldo_rop_\@:
  94         mov     \reg, (%_ASM_SP)
  95         ret
  96 .endm
  97
  98 /*
  99  * This is a wrapper around RETPOLINE_JMP so the called function in reg
 100  * returns to the instruction after the macro.
 101  */
 102 .macro RETPOLINE_CALL reg:req
 103         jmp     .Ldo_call_\@
 104 .Ldo_retpoline_jmp_\@:
 105         RETPOLINE_JMP \reg
 106 .Ldo_call_\@:
 107         call    .Ldo_retpoline_jmp_\@
 108 .endm
 109
 110 /*
 111  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
 112  * indirect jmp/call which may be susceptible to the Spectre variant 2
 113  * attack.
 114  */
 115 .macro JMP_NOSPEC reg:req
 116 #ifdef CONFIG_RETPOLINE
 117         ANNOTATE_NOSPEC_ALTERNATIVE
 118         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg),  \
 119                 __stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
 120                 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
 121 #else
 122         jmp     *\reg
 123 #endif
 124 .endm
 125
 126 .macro CALL_NOSPEC reg:req
 127 #ifdef CONFIG_RETPOLINE
 128         ANNOTATE_NOSPEC_ALTERNATIVE
 129         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg), \
 130                 __stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
 131                 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_AMD
 132 #else
 133         call    *\reg
 134 #endif
 135 .endm
 136
 137  /*
 138   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 139   * monstrosity above, manually.
 140   */
 141 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 142 #ifdef CONFIG_RETPOLINE
 143         ANNOTATE_NOSPEC_ALTERNATIVE
 144         ALTERNATIVE "jmp .Lskip_rsb_\@",                                \
 145                 __stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP))    \
 146                 \ftr
 147 .Lskip_rsb_\@:
 148 #endif
 149 .endm
 150
 151 #else /* __ASSEMBLY__ */
 152
 153 #define ANNOTATE_NOSPEC_ALTERNATIVE                             \
 154         "999:\n\t"                                              \
 155         ".pushsection .discard.nospec\n\t"                      \
 156         ".long 999b - .\n\t"                                    \
 157         ".popsection\n\t"
 158
 159 #define ANNOTATE_RETPOLINE_SAFE                                 \
 160         "999:\n\t"                                              \
 161         ".pushsection .discard.retpoline_safe\n\t"              \
 162         _ASM_PTR " 999b\n\t"                                    \
 163         ".popsection\n\t"
 164
 165 #ifdef CONFIG_RETPOLINE
 166 #ifdef CONFIG_X86_64
 167
 168 /*
 169  * Inline asm uses the %V modifier which is only in newer GCC
 170  * which is ensured when CONFIG_RETPOLINE is defined.
 171  */
 172 # define CALL_NOSPEC                                            \
 173         ANNOTATE_NOSPEC_ALTERNATIVE                             \
 174         ALTERNATIVE_2(                                          \
 175         ANNOTATE_RETPOLINE_SAFE                                 \
 176         "call *%[thunk_target]\n",                              \
 177         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 178         X86_FEATURE_RETPOLINE,                                  \
 179         "lfence;\n"                                             \
 180         ANNOTATE_RETPOLINE_SAFE                                 \
 181         "call *%[thunk_target]\n",                              \
 182         X86_FEATURE_RETPOLINE_AMD)
 183 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 184
 185 #else /* CONFIG_X86_32 */
 186 /*
 187  * For i386 we use the original ret-equivalent retpoline, because
 188  * otherwise we'll run out of registers. We don't care about CET
 189  * here, anyway.
 190  */
 191 # define CALL_NOSPEC                                            \
 192         ANNOTATE_NOSPEC_ALTERNATIVE                             \
 193         ALTERNATIVE_2(                                          \
 194         ANNOTATE_RETPOLINE_SAFE                                 \
 195         "call *%[thunk_target]\n",                              \
 196         "       jmp    904f;\n"                                 \
 197         "       .align 16\n"                                    \
 198         "901:   call   903f;\n"                                 \
 199         "902:   pause;\n"                                       \
 200         "       lfence;\n"                                      \
 201         "       jmp    902b;\n"                                 \
 202         "       .align 16\n"                                    \
 203         "903:   addl   $4, %%esp;\n"                            \
 204         "       pushl  %[thunk_target];\n"                      \
 205         "       ret;\n"                                         \
 206         "       .align 16\n"                                    \
 207         "904:   call   901b;\n",                                \
 208         X86_FEATURE_RETPOLINE,                                  \
 209         "lfence;\n"                                             \
 210         ANNOTATE_RETPOLINE_SAFE                                 \
 211         "call *%[thunk_target]\n",                              \
 212         X86_FEATURE_RETPOLINE_AMD)
 213
 214 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 215 #endif
 216 #else /* No retpoline for C / inline asm */
 217 # define CALL_NOSPEC "call *%[thunk_target]\n"
 218 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 219 #endif
 220
 221 /* The Spectre V2 mitigation variants */
 222 enum spectre_v2_mitigation {
 223         SPECTRE_V2_NONE,
 224         SPECTRE_V2_RETPOLINE_MINIMAL,
 225         SPECTRE_V2_RETPOLINE_MINIMAL_AMD,
 226         SPECTRE_V2_RETPOLINE_GENERIC,
 227         SPECTRE_V2_RETPOLINE_AMD,
 228         SPECTRE_V2_IBRS_ENHANCED,
 229 };
 230
 231 /* The Speculative Store Bypass disable variants */
 232 enum ssb_mitigation {
 233         SPEC_STORE_BYPASS_NONE,
 234         SPEC_STORE_BYPASS_DISABLE,
 235         SPEC_STORE_BYPASS_PRCTL,
 236         SPEC_STORE_BYPASS_SECCOMP,
 237 };
 238
 239 extern char __indirect_thunk_start[];
 240 extern char __indirect_thunk_end[];
 241
 242 /*
 243  * On VMEXIT we must ensure that no RSB predictions learned in the guest
 244  * can be followed in the host, by overwriting the RSB completely. Both
 245  * retpoline and IBRS mitigations for Spectre v2 need this; only on future
 246  * CPUs with IBRS_ALL *might* it be avoided.
 247  */
 248 static inline void vmexit_fill_RSB(void)
 249 {
 250 #ifdef CONFIG_RETPOLINE
 251         unsigned long loops;
 252
 253         asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
 254                       ALTERNATIVE("jmp 910f",
 255                                   __stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
 256                                   X86_FEATURE_RETPOLINE)
 257                       "910:"
 258                       : "=r" (loops), ASM_CALL_CONSTRAINT
 259                       : : "memory" );
 260 #endif
 261 }
 262
 263 static __always_inline
 264 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 265 {
 266         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 267                 : : "c" (msr),
 268                     "a" ((u32)val),
 269                     "d" ((u32)(val >> 32)),
 270                     [feature] "i" (feature)
 271                 : "memory");
 272 }
 273
 274 static inline void indirect_branch_prediction_barrier(void)
 275 {
 276         u64 val = PRED_CMD_IBPB;
 277
 278         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 279 }
 280
 281 /* The Intel SPEC CTRL MSR base value cache */
 282 extern u64 x86_spec_ctrl_base;
 283
 284 /*
 285  * With retpoline, we must use IBRS to restrict branch prediction
 286  * before calling into firmware.
 287  *
 288  * (Implemented as CPP macros due to header hell.)
 289  */
 290 #define firmware_restrict_branch_speculation_start()                    \
 291 do {                                                                    \
 292         u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;                  \
 293                                                                         \
 294         preempt_disable();                                              \
 295         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 296                               X86_FEATURE_USE_IBRS_FW);                 \
 297 } while (0)
 298
 299 #define firmware_restrict_branch_speculation_end()                      \
 300 do {                                                                    \
 301         u64 val = x86_spec_ctrl_base;                                   \
 302                                                                         \
 303         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 304                               X86_FEATURE_USE_IBRS_FW);                 \
 305         preempt_enable();                                               \
 306 } while (0)
 307
 308 #endif /* __ASSEMBLY__ */
 309
 310 /*
 311  * Below is used in the eBPF JIT compiler and emits the byte sequence
 312  * for the following assembly:
 313  *
 314  * With retpolines configured:
 315  *
 316  *    callq do_rop
 317  *  spec_trap:
 318  *    pause
 319  *    lfence
 320  *    jmp spec_trap
 321  *  do_rop:
 322  *    mov %rax,(%rsp) for x86_64
 323  *    mov %edx,(%esp) for x86_32
 324  *    retq
 325  *
 326  * Without retpolines configured:
 327  *
 328  *    jmp *%rax for x86_64
 329  *    jmp *%edx for x86_32
 330  */
 331 #ifdef CONFIG_RETPOLINE
 332 # ifdef CONFIG_X86_64
 333 #  define RETPOLINE_RAX_BPF_JIT_SIZE    17
 334 #  define RETPOLINE_RAX_BPF_JIT()                               \
 335 do {                                                            \
 336         EMIT1_off32(0xE8, 7);    /* callq do_rop */             \
 337         /* spec_trap: */                                        \
 338         EMIT2(0xF3, 0x90);       /* pause */                    \
 339         EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
 340         EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
 341         /* do_rop: */                                           \
 342         EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */    \
 343         EMIT1(0xC3);             /* retq */                     \
 344 } while (0)
 345 # else /* !CONFIG_X86_64 */
 346 #  define RETPOLINE_EDX_BPF_JIT()                               \
 347 do {                                                            \
 348         EMIT1_off32(0xE8, 7);    /* call do_rop */              \
 349         /* spec_trap: */                                        \
 350         EMIT2(0xF3, 0x90);       /* pause */                    \
 351         EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
 352         EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
 353         /* do_rop: */                                           \
 354         EMIT3(0x89, 0x14, 0x24); /* mov %edx,(%esp) */          \
 355         EMIT1(0xC3);             /* ret */                      \
 356 } while (0)
 357 # endif
 358 #else /* !CONFIG_RETPOLINE */
 359 # ifdef CONFIG_X86_64
 360 #  define RETPOLINE_RAX_BPF_JIT_SIZE    2
 361 #  define RETPOLINE_RAX_BPF_JIT()                               \
 362         EMIT2(0xFF, 0xE0);       /* jmp *%rax */
 363 # else /* !CONFIG_X86_64 */
 364 #  define RETPOLINE_EDX_BPF_JIT()                               \
 365         EMIT2(0xFF, 0xE2)        /* jmp *%edx */
 366 # endif
 367 #endif
 368
 369 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */