1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2014 Google, Inc
5 * From Coreboot file of the same name
11 /* MTRR region types */
12 #define MTRR_TYPE_UNCACHEABLE 0
13 #define MTRR_TYPE_WRCOMB 1
14 #define MTRR_TYPE_WRTHROUGH 4
15 #define MTRR_TYPE_WRPROT 5
16 #define MTRR_TYPE_WRBACK 6
18 #define MTRR_TYPE_COUNT 7
20 #define MTRR_CAP_MSR 0x0fe
21 #define MTRR_DEF_TYPE_MSR 0x2ff
23 #define MTRR_CAP_SMRR (1 << 11)
24 #define MTRR_CAP_WC (1 << 10)
25 #define MTRR_CAP_FIX (1 << 8)
26 #define MTRR_CAP_VCNT_MASK 0xff
28 #define MTRR_DEF_TYPE_MASK 0xff
29 #define MTRR_DEF_TYPE_EN (1 << 11)
30 #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
32 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
35 #define MTRR_PHYS_MASK_VALID (1 << 11)
37 #define MTRR_BASE_TYPE_MASK 0x7
39 /* Maximum number of MTRRs supported - see also mtrr_get_var_count() */
40 #define MTRR_MAX_COUNT 10
42 #define NUM_FIXED_MTRRS 11
43 #define RANGES_PER_FIXED_MTRR 8
44 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
46 #define MTRR_FIX_64K_00000_MSR 0x250
47 #define MTRR_FIX_16K_80000_MSR 0x258
48 #define MTRR_FIX_16K_A0000_MSR 0x259
49 #define MTRR_FIX_4K_C0000_MSR 0x268
50 #define MTRR_FIX_4K_C8000_MSR 0x269
51 #define MTRR_FIX_4K_D0000_MSR 0x26a
52 #define MTRR_FIX_4K_D8000_MSR 0x26b
53 #define MTRR_FIX_4K_E0000_MSR 0x26c
54 #define MTRR_FIX_4K_E8000_MSR 0x26d
55 #define MTRR_FIX_4K_F0000_MSR 0x26e
56 #define MTRR_FIX_4K_F8000_MSR 0x26f
58 #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t)
60 #if !defined(__ASSEMBLY__)
63 * Information about the previous MTRR state, set up by mtrr_open()
65 * @deftype: Previous value of MTRR_DEF_TYPE_MSR
66 * @enable_cache: true if cache was enabled
74 * struct mtrr - Information about a single MTRR
76 * @base: Base address and MTRR_BASE_TYPE_MASK
77 * @mask: Mask and MTRR_PHYS_MASK_VALID
85 * struct mtrr_info - Information about all MTRRs
87 * @mtrr: Information about each mtrr
90 struct mtrr mtrr[MTRR_MAX_COUNT];
94 * mtrr_open() - Prepare to adjust MTRRs
96 * Use mtrr_open() passing in a structure - this function will init it. Then
97 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
100 * @state: Empty structure to pass in to hold settings
101 * @do_caches: true to disable caches before opening
103 void mtrr_open(struct mtrr_state *state, bool do_caches);
106 * mtrr_close() - Clean up after adjusting MTRRs, and enable them
108 * This uses the structure containing information returned from mtrr_open().
110 * @state: Structure from mtrr_open()
111 * @state: true to restore cache state to that before mtrr_open()
113 void mtrr_close(struct mtrr_state *state, bool do_caches);
116 * mtrr_add_request() - Add a new MTRR request
118 * This adds a request for a memory region to be set up in a particular way.
120 * @type: Requested type (MTRR_TYPE_)
121 * @start: Start address
122 * @size: Size, must be power of 2
124 * @return: 0 on success, non-zero on failure
126 int mtrr_add_request(int type, uint64_t start, uint64_t size);
129 * mtrr_commit() - set up the MTRR registers based on current requests
131 * This sets up MTRRs for the available DRAM and the requests received so far.
132 * It must be called with caches disabled.
134 * @do_caches: true if caches are currently on
136 * @return: 0 on success, non-zero on failure
138 int mtrr_commit(bool do_caches);
141 * mtrr_set_next_var() - set up a variable MTRR
143 * This finds the first free variable MTRR and sets to the given area
145 * @type: Requested type (MTRR_TYPE_)
146 * @start: Start address
147 * @size: Size, must be power of 2
148 * Return: 0 on success, -EINVAL if size is not power of 2,
149 * -ENOSPC if there are no more MTRRs
151 int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
154 * mtrr_read_all() - Save all the MTRRs
156 * This reads all MTRRs from the boot CPU into a struct so they can be loaded
159 * @info: Place to put the MTRR info
161 void mtrr_read_all(struct mtrr_info *info);
164 * mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s)
166 * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
167 * @reg: MTRR register to write (0-7)
168 * @valid: Valid flag to write
169 * Return: 0 on success, -ve on error
171 int mtrr_set_valid(int cpu_select, int reg, bool valid);
174 * mtrr_set() - Set the base address and mask for a selected MTRR and CPU(s)
176 * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
177 * @reg: MTRR register to write (0-7)
178 * @base: Base address and MTRR_BASE_TYPE_MASK
179 * @mask: Mask and MTRR_PHYS_MASK_VALID
180 * Return: 0 on success, -ve on error
182 int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
185 * mtrr_get_var_count() - Get the number of variable MTRRs
187 * Some CPUs have more than 8 MTRRs. This function returns the actual number
189 * Return: number of variable MTRRs
191 int mtrr_get_var_count(void);
194 * mtrr_list() - List the MTRRs
196 * Shows a list of all the MTRRs including their values
198 * @reg_count: Number of registers to show. You can use mtrr_get_var_count() for
200 * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
201 * Returns: 0 if OK, -ve if the CPU was not found
203 int mtrr_list(int reg_count, int cpu_select);
206 * mtrr_get_type_by_name() - Get the type of an MTRR given its type name
208 * @typename: Name to check
209 * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
211 int mtrr_get_type_by_name(const char *typename);
215 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
216 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
219 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
220 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
223 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)