1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MSR_INDEX_H
3 #define _ASM_X86_MSR_INDEX_H
5 #include <linux/bits.h>
8 * CPU model specific register (MSR) numbers.
10 * Do not add new entries to this file unless the definitions are shared
11 * between multiple compilation units.
14 /* x86-64 specific MSRs */
15 #define MSR_EFER 0xc0000080 /* extended feature register */
16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
27 #define _EFER_LME 8 /* Long mode enable */
28 #define _EFER_LMA 10 /* Long mode active (read-only) */
29 #define _EFER_NX 11 /* No execute enable */
30 #define _EFER_SVME 12 /* Enable virtualization */
31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
34 #define EFER_SCE (1<<_EFER_SCE)
35 #define EFER_LME (1<<_EFER_LME)
36 #define EFER_LMA (1<<_EFER_LMA)
37 #define EFER_NX (1<<_EFER_NX)
38 #define EFER_SVME (1<<_EFER_SVME)
39 #define EFER_LMSLE (1<<_EFER_LMSLE)
40 #define EFER_FFXSR (1<<_EFER_FFXSR)
42 /* Intel MSRs. Some also available on other CPUs */
44 #define MSR_TEST_CTRL 0x00000033
45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
54 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
55 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
57 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
58 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
60 #define MSR_PPIN_CTL 0x0000004e
61 #define MSR_PPIN 0x0000004f
63 #define MSR_IA32_PERFCTR0 0x000000c1
64 #define MSR_IA32_PERFCTR1 0x000000c2
65 #define MSR_FSB_FREQ 0x000000cd
66 #define MSR_PLATFORM_INFO 0x000000ce
67 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
68 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
70 #define MSR_IA32_UMWAIT_CONTROL 0xe1
71 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
72 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
74 * The time field is bit[31:2], but representing a 32bit value with
77 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
79 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
80 #define MSR_IA32_CORE_CAPS 0x000000cf
81 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
82 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
83 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
84 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
86 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
87 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
88 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
89 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
90 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
91 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
93 #define MSR_MTRRcap 0x000000fe
95 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
96 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
97 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
98 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
99 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
100 #define ARCH_CAP_SSB_NO BIT(4) /*
101 * Not susceptible to Speculative Store Bypass
102 * attack, so no Speculative Store Bypass
105 #define ARCH_CAP_MDS_NO BIT(5) /*
107 * Microarchitectural Data
108 * Sampling (MDS) vulnerabilities.
110 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
111 * The processor is not susceptible to a
112 * machine check error due to modifying the
113 * code page size along with either the
114 * physical address or cache type
115 * without TLB invalidation.
117 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
118 #define ARCH_CAP_TAA_NO BIT(8) /*
120 * TSX Async Abort (TAA) vulnerabilities.
122 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /*
123 * Not susceptible to SBDR and SSDP
124 * variants of Processor MMIO stale data
127 #define ARCH_CAP_FBSDP_NO BIT(14) /*
128 * Not susceptible to FBSDP variant of
129 * Processor MMIO stale data
132 #define ARCH_CAP_PSDP_NO BIT(15) /*
133 * Not susceptible to PSDP variant of
134 * Processor MMIO stale data
137 #define ARCH_CAP_FB_CLEAR BIT(17) /*
138 * VERW clears CPU fill buffer
139 * even on MDS_NO CPUs.
141 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
142 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
143 * bit available to control VERW
146 #define ARCH_CAP_RRSBA BIT(19) /*
147 * Indicates RET may use predictors
148 * other than the RSB. With eIBRS
149 * enabled predictions in kernel mode
150 * are restricted to targets in
153 #define ARCH_CAP_PBRSB_NO BIT(24) /*
154 * Not susceptible to Post-Barrier
155 * Return Stack Buffer Predictions.
158 #define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
159 * IA32_XAPIC_DISABLE_STATUS MSR
163 #define MSR_IA32_FLUSH_CMD 0x0000010b
164 #define L1D_FLUSH BIT(0) /*
165 * Writeback and invalidate the
169 #define MSR_IA32_BBL_CR_CTL 0x00000119
170 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
172 #define MSR_IA32_TSX_CTRL 0x00000122
173 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
174 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
176 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
177 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
178 #define RTM_ALLOW BIT(1) /* TSX development mode */
179 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
181 #define MSR_IA32_SYSENTER_CS 0x00000174
182 #define MSR_IA32_SYSENTER_ESP 0x00000175
183 #define MSR_IA32_SYSENTER_EIP 0x00000176
185 #define MSR_IA32_MCG_CAP 0x00000179
186 #define MSR_IA32_MCG_STATUS 0x0000017a
187 #define MSR_IA32_MCG_CTL 0x0000017b
188 #define MSR_ERROR_CONTROL 0x0000017f
189 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
191 #define MSR_OFFCORE_RSP_0 0x000001a6
192 #define MSR_OFFCORE_RSP_1 0x000001a7
193 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
194 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
195 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
197 #define MSR_LBR_SELECT 0x000001c8
198 #define MSR_LBR_TOS 0x000001c9
200 #define MSR_IA32_POWER_CTL 0x000001fc
201 #define MSR_IA32_POWER_CTL_BIT_EE 19
203 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
204 #define MSR_INTEGRITY_CAPS 0x000002d9
205 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
206 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
208 #define MSR_LBR_NHM_FROM 0x00000680
209 #define MSR_LBR_NHM_TO 0x000006c0
210 #define MSR_LBR_CORE_FROM 0x00000040
211 #define MSR_LBR_CORE_TO 0x00000060
213 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
214 #define LBR_INFO_MISPRED BIT_ULL(63)
215 #define LBR_INFO_IN_TX BIT_ULL(62)
216 #define LBR_INFO_ABORT BIT_ULL(61)
217 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
218 #define LBR_INFO_CYCLES 0xffff
219 #define LBR_INFO_BR_TYPE_OFFSET 56
220 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
222 #define MSR_ARCH_LBR_CTL 0x000014ce
223 #define ARCH_LBR_CTL_LBREN BIT(0)
224 #define ARCH_LBR_CTL_CPL_OFFSET 1
225 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
226 #define ARCH_LBR_CTL_STACK_OFFSET 3
227 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
228 #define ARCH_LBR_CTL_FILTER_OFFSET 16
229 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
230 #define MSR_ARCH_LBR_DEPTH 0x000014cf
231 #define MSR_ARCH_LBR_FROM_0 0x00001500
232 #define MSR_ARCH_LBR_TO_0 0x00001600
233 #define MSR_ARCH_LBR_INFO_0 0x00001200
235 #define MSR_IA32_PEBS_ENABLE 0x000003f1
236 #define MSR_PEBS_DATA_CFG 0x000003f2
237 #define MSR_IA32_DS_AREA 0x00000600
238 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
239 #define PERF_CAP_METRICS_IDX 15
240 #define PERF_CAP_PT_IDX 16
242 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
243 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
244 #define PERF_CAP_ARCH_REG BIT_ULL(7)
245 #define PERF_CAP_PEBS_FORMAT 0xf00
246 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
247 #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
248 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
250 #define MSR_IA32_RTIT_CTL 0x00000570
251 #define RTIT_CTL_TRACEEN BIT(0)
252 #define RTIT_CTL_CYCLEACC BIT(1)
253 #define RTIT_CTL_OS BIT(2)
254 #define RTIT_CTL_USR BIT(3)
255 #define RTIT_CTL_PWR_EVT_EN BIT(4)
256 #define RTIT_CTL_FUP_ON_PTW BIT(5)
257 #define RTIT_CTL_FABRIC_EN BIT(6)
258 #define RTIT_CTL_CR3EN BIT(7)
259 #define RTIT_CTL_TOPA BIT(8)
260 #define RTIT_CTL_MTC_EN BIT(9)
261 #define RTIT_CTL_TSC_EN BIT(10)
262 #define RTIT_CTL_DISRETC BIT(11)
263 #define RTIT_CTL_PTW_EN BIT(12)
264 #define RTIT_CTL_BRANCH_EN BIT(13)
265 #define RTIT_CTL_EVENT_EN BIT(31)
266 #define RTIT_CTL_NOTNT BIT_ULL(55)
267 #define RTIT_CTL_MTC_RANGE_OFFSET 14
268 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
269 #define RTIT_CTL_CYC_THRESH_OFFSET 19
270 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
271 #define RTIT_CTL_PSB_FREQ_OFFSET 24
272 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
273 #define RTIT_CTL_ADDR0_OFFSET 32
274 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
275 #define RTIT_CTL_ADDR1_OFFSET 36
276 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
277 #define RTIT_CTL_ADDR2_OFFSET 40
278 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
279 #define RTIT_CTL_ADDR3_OFFSET 44
280 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
281 #define MSR_IA32_RTIT_STATUS 0x00000571
282 #define RTIT_STATUS_FILTEREN BIT(0)
283 #define RTIT_STATUS_CONTEXTEN BIT(1)
284 #define RTIT_STATUS_TRIGGEREN BIT(2)
285 #define RTIT_STATUS_BUFFOVF BIT(3)
286 #define RTIT_STATUS_ERROR BIT(4)
287 #define RTIT_STATUS_STOPPED BIT(5)
288 #define RTIT_STATUS_BYTECNT_OFFSET 32
289 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
290 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
291 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
292 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
293 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
294 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
295 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
296 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
297 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
298 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
299 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
300 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
302 #define MSR_MTRRfix64K_00000 0x00000250
303 #define MSR_MTRRfix16K_80000 0x00000258
304 #define MSR_MTRRfix16K_A0000 0x00000259
305 #define MSR_MTRRfix4K_C0000 0x00000268
306 #define MSR_MTRRfix4K_C8000 0x00000269
307 #define MSR_MTRRfix4K_D0000 0x0000026a
308 #define MSR_MTRRfix4K_D8000 0x0000026b
309 #define MSR_MTRRfix4K_E0000 0x0000026c
310 #define MSR_MTRRfix4K_E8000 0x0000026d
311 #define MSR_MTRRfix4K_F0000 0x0000026e
312 #define MSR_MTRRfix4K_F8000 0x0000026f
313 #define MSR_MTRRdefType 0x000002ff
315 #define MSR_IA32_CR_PAT 0x00000277
317 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
318 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
319 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
320 #define MSR_IA32_LASTINTFROMIP 0x000001dd
321 #define MSR_IA32_LASTINTTOIP 0x000001de
323 #define MSR_IA32_PASID 0x00000d93
324 #define MSR_IA32_PASID_VALID BIT_ULL(31)
326 /* DEBUGCTLMSR bits (others vary by model): */
327 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
328 #define DEBUGCTLMSR_BTF_SHIFT 1
329 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
330 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
331 #define DEBUGCTLMSR_TR (1UL << 6)
332 #define DEBUGCTLMSR_BTS (1UL << 7)
333 #define DEBUGCTLMSR_BTINT (1UL << 8)
334 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
335 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
336 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
337 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
338 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
339 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
341 #define MSR_PEBS_FRONTEND 0x000003f7
343 #define MSR_IA32_MC0_CTL 0x00000400
344 #define MSR_IA32_MC0_STATUS 0x00000401
345 #define MSR_IA32_MC0_ADDR 0x00000402
346 #define MSR_IA32_MC0_MISC 0x00000403
348 /* C-state Residency Counters */
349 #define MSR_PKG_C3_RESIDENCY 0x000003f8
350 #define MSR_PKG_C6_RESIDENCY 0x000003f9
351 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
352 #define MSR_PKG_C7_RESIDENCY 0x000003fa
353 #define MSR_CORE_C3_RESIDENCY 0x000003fc
354 #define MSR_CORE_C6_RESIDENCY 0x000003fd
355 #define MSR_CORE_C7_RESIDENCY 0x000003fe
356 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
357 #define MSR_PKG_C2_RESIDENCY 0x0000060d
358 #define MSR_PKG_C8_RESIDENCY 0x00000630
359 #define MSR_PKG_C9_RESIDENCY 0x00000631
360 #define MSR_PKG_C10_RESIDENCY 0x00000632
362 /* Interrupt Response Limit */
363 #define MSR_PKGC3_IRTL 0x0000060a
364 #define MSR_PKGC6_IRTL 0x0000060b
365 #define MSR_PKGC7_IRTL 0x0000060c
366 #define MSR_PKGC8_IRTL 0x00000633
367 #define MSR_PKGC9_IRTL 0x00000634
368 #define MSR_PKGC10_IRTL 0x00000635
370 /* Run Time Average Power Limiting (RAPL) Interface */
372 #define MSR_VR_CURRENT_CONFIG 0x00000601
373 #define MSR_RAPL_POWER_UNIT 0x00000606
375 #define MSR_PKG_POWER_LIMIT 0x00000610
376 #define MSR_PKG_ENERGY_STATUS 0x00000611
377 #define MSR_PKG_PERF_STATUS 0x00000613
378 #define MSR_PKG_POWER_INFO 0x00000614
380 #define MSR_DRAM_POWER_LIMIT 0x00000618
381 #define MSR_DRAM_ENERGY_STATUS 0x00000619
382 #define MSR_DRAM_PERF_STATUS 0x0000061b
383 #define MSR_DRAM_POWER_INFO 0x0000061c
385 #define MSR_PP0_POWER_LIMIT 0x00000638
386 #define MSR_PP0_ENERGY_STATUS 0x00000639
387 #define MSR_PP0_POLICY 0x0000063a
388 #define MSR_PP0_PERF_STATUS 0x0000063b
390 #define MSR_PP1_POWER_LIMIT 0x00000640
391 #define MSR_PP1_ENERGY_STATUS 0x00000641
392 #define MSR_PP1_POLICY 0x00000642
394 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
395 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
396 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
398 /* Config TDP MSRs */
399 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
400 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
401 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
402 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
403 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
405 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
406 #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
408 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
409 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
410 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
411 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
413 #define MSR_CORE_C1_RES 0x00000660
414 #define MSR_MODULE_C6_RES_MS 0x00000664
416 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
417 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
419 #define MSR_ATOM_CORE_RATIOS 0x0000066a
420 #define MSR_ATOM_CORE_VIDS 0x0000066b
421 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
422 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
424 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
425 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
426 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
428 /* Control-flow Enforcement Technology MSRs */
429 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
430 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
431 #define CET_SHSTK_EN BIT_ULL(0)
432 #define CET_WRSS_EN BIT_ULL(1)
433 #define CET_ENDBR_EN BIT_ULL(2)
434 #define CET_LEG_IW_EN BIT_ULL(3)
435 #define CET_NO_TRACK_EN BIT_ULL(4)
436 #define CET_SUPPRESS_DISABLE BIT_ULL(5)
437 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
438 #define CET_SUPPRESS BIT_ULL(10)
439 #define CET_WAIT_ENDBR BIT_ULL(11)
441 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
442 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
443 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
444 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
445 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
447 /* Hardware P state interface */
448 #define MSR_PPERF 0x0000064e
449 #define MSR_PERF_LIMIT_REASONS 0x0000064f
450 #define MSR_PM_ENABLE 0x00000770
451 #define MSR_HWP_CAPABILITIES 0x00000771
452 #define MSR_HWP_REQUEST_PKG 0x00000772
453 #define MSR_HWP_INTERRUPT 0x00000773
454 #define MSR_HWP_REQUEST 0x00000774
455 #define MSR_HWP_STATUS 0x00000777
458 #define HWP_BASE_BIT (1<<7)
459 #define HWP_NOTIFICATIONS_BIT (1<<8)
460 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
461 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
462 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
464 /* IA32_HWP_CAPABILITIES */
465 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
466 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
467 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
468 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
470 /* IA32_HWP_REQUEST */
471 #define HWP_MIN_PERF(x) (x & 0xff)
472 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
473 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
474 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
475 #define HWP_EPP_PERFORMANCE 0x00
476 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
477 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
478 #define HWP_EPP_POWERSAVE 0xFF
479 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
480 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
482 /* IA32_HWP_STATUS */
483 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
484 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
486 /* IA32_HWP_INTERRUPT */
487 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
488 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
490 #define MSR_AMD64_MC0_MASK 0xc0010044
492 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
493 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
494 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
495 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
497 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
499 /* These are consecutive and not in the normal 4er MCE bank block */
500 #define MSR_IA32_MC0_CTL2 0x00000280
501 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
503 #define MSR_P6_PERFCTR0 0x000000c1
504 #define MSR_P6_PERFCTR1 0x000000c2
505 #define MSR_P6_EVNTSEL0 0x00000186
506 #define MSR_P6_EVNTSEL1 0x00000187
508 #define MSR_KNC_PERFCTR0 0x00000020
509 #define MSR_KNC_PERFCTR1 0x00000021
510 #define MSR_KNC_EVNTSEL0 0x00000028
511 #define MSR_KNC_EVNTSEL1 0x00000029
513 /* Alternative perfctr range with full access. */
514 #define MSR_IA32_PMC0 0x000004c1
516 /* Auto-reload via MSR instead of DS area */
517 #define MSR_RELOAD_PMC0 0x000014c1
518 #define MSR_RELOAD_FIXED_CTR0 0x00001309
521 * AMD64 MSRs. Not complete. See the architecture manual for a more
524 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
525 #define MSR_AMD64_TSC_RATIO 0xc0000104
526 #define MSR_AMD64_NB_CFG 0xc001001f
527 #define MSR_AMD64_PATCH_LOADER 0xc0010020
528 #define MSR_AMD_PERF_CTL 0xc0010062
529 #define MSR_AMD_PERF_STATUS 0xc0010063
530 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
531 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
532 #define MSR_AMD64_OSVW_STATUS 0xc0010141
533 #define MSR_AMD_PPIN_CTL 0xc00102f0
534 #define MSR_AMD_PPIN 0xc00102f1
535 #define MSR_AMD64_CPUID_FN_1 0xc0011004
536 #define MSR_AMD64_LS_CFG 0xc0011020
537 #define MSR_AMD64_DC_CFG 0xc0011022
539 #define MSR_AMD64_DE_CFG 0xc0011029
540 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
541 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
543 #define MSR_AMD64_BU_CFG2 0xc001102a
544 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
545 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
546 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
547 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
548 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
549 #define MSR_AMD64_IBSOPCTL 0xc0011033
550 #define MSR_AMD64_IBSOPRIP 0xc0011034
551 #define MSR_AMD64_IBSOPDATA 0xc0011035
552 #define MSR_AMD64_IBSOPDATA2 0xc0011036
553 #define MSR_AMD64_IBSOPDATA3 0xc0011037
554 #define MSR_AMD64_IBSDCLINAD 0xc0011038
555 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
556 #define MSR_AMD64_IBSOP_REG_COUNT 7
557 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
558 #define MSR_AMD64_IBSCTL 0xc001103a
559 #define MSR_AMD64_IBSBRTARGET 0xc001103b
560 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
561 #define MSR_AMD64_IBSOPDATA4 0xc001103d
562 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
563 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
564 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
565 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
566 #define MSR_AMD64_SEV 0xc0010131
567 #define MSR_AMD64_SEV_ENABLED_BIT 0
568 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1
569 #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
570 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
571 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
572 #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
574 /* SNP feature bits enabled by the hypervisor */
575 #define MSR_AMD64_SNP_VTOM BIT_ULL(3)
576 #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4)
577 #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5)
578 #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6)
579 #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7)
580 #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8)
581 #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9)
582 #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10)
583 #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11)
584 #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12)
585 #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14)
586 #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16)
587 #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17)
589 /* SNP feature bits reserved for future use. */
590 #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
591 #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
592 #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18)
594 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
596 /* AMD Collaborative Processor Performance Control MSRs */
597 #define MSR_AMD_CPPC_CAP1 0xc00102b0
598 #define MSR_AMD_CPPC_ENABLE 0xc00102b1
599 #define MSR_AMD_CPPC_CAP2 0xc00102b2
600 #define MSR_AMD_CPPC_REQ 0xc00102b3
601 #define MSR_AMD_CPPC_STATUS 0xc00102b4
603 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
604 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
605 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
606 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
608 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
609 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
610 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
611 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
613 /* AMD Performance Counter Global Status and Control MSRs */
614 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
615 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
616 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
618 /* AMD Last Branch Record MSRs */
619 #define MSR_AMD64_LBR_SELECT 0xc000010e
622 #define MSR_F17H_IRPERF 0xc00000e9
624 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
625 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
628 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
629 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
630 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
631 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
632 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
633 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
636 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
637 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
638 #define MSR_F15H_PERF_CTL 0xc0010200
639 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
640 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
641 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
642 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
643 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
644 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
646 #define MSR_F15H_PERF_CTR 0xc0010201
647 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
648 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
649 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
650 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
651 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
652 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
654 #define MSR_F15H_NB_PERF_CTL 0xc0010240
655 #define MSR_F15H_NB_PERF_CTR 0xc0010241
656 #define MSR_F15H_PTSC 0xc0010280
657 #define MSR_F15H_IC_CFG 0xc0011021
658 #define MSR_F15H_EX_CFG 0xc001102c
661 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
662 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
663 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
664 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
665 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
666 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
667 #define MSR_FAM10H_NODE_ID 0xc001100c
670 #define MSR_K8_TOP_MEM1 0xc001001a
671 #define MSR_K8_TOP_MEM2 0xc001001d
672 #define MSR_AMD64_SYSCFG 0xc0010010
673 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
674 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
675 #define MSR_K8_INT_PENDING_MSG 0xc0010055
676 /* C1E active bits in int pending message */
677 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
678 #define MSR_K8_TSEG_ADDR 0xc0010112
679 #define MSR_K8_TSEG_MASK 0xc0010113
680 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
681 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
682 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
685 #define MSR_K7_EVNTSEL0 0xc0010000
686 #define MSR_K7_PERFCTR0 0xc0010004
687 #define MSR_K7_EVNTSEL1 0xc0010001
688 #define MSR_K7_PERFCTR1 0xc0010005
689 #define MSR_K7_EVNTSEL2 0xc0010002
690 #define MSR_K7_PERFCTR2 0xc0010006
691 #define MSR_K7_EVNTSEL3 0xc0010003
692 #define MSR_K7_PERFCTR3 0xc0010007
693 #define MSR_K7_CLK_CTL 0xc001001b
694 #define MSR_K7_HWCR 0xc0010015
695 #define MSR_K7_HWCR_SMMLOCK_BIT 0
696 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
697 #define MSR_K7_HWCR_IRPERF_EN_BIT 30
698 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
699 #define MSR_K7_FID_VID_CTL 0xc0010041
700 #define MSR_K7_FID_VID_STATUS 0xc0010042
703 #define MSR_K6_WHCR 0xc0000082
704 #define MSR_K6_UWCCR 0xc0000085
705 #define MSR_K6_EPMR 0xc0000086
706 #define MSR_K6_PSOR 0xc0000087
707 #define MSR_K6_PFIR 0xc0000088
709 /* Centaur-Hauls/IDT defined MSRs. */
710 #define MSR_IDT_FCR1 0x00000107
711 #define MSR_IDT_FCR2 0x00000108
712 #define MSR_IDT_FCR3 0x00000109
713 #define MSR_IDT_FCR4 0x0000010a
715 #define MSR_IDT_MCR0 0x00000110
716 #define MSR_IDT_MCR1 0x00000111
717 #define MSR_IDT_MCR2 0x00000112
718 #define MSR_IDT_MCR3 0x00000113
719 #define MSR_IDT_MCR4 0x00000114
720 #define MSR_IDT_MCR5 0x00000115
721 #define MSR_IDT_MCR6 0x00000116
722 #define MSR_IDT_MCR7 0x00000117
723 #define MSR_IDT_MCR_CTRL 0x00000120
725 /* VIA Cyrix defined MSRs*/
726 #define MSR_VIA_FCR 0x00001107
727 #define MSR_VIA_LONGHAUL 0x0000110a
728 #define MSR_VIA_RNG 0x0000110b
729 #define MSR_VIA_BCR2 0x00001147
731 /* Transmeta defined MSRs */
732 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
733 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
734 #define MSR_TMTA_LRTI_READOUT 0x80868018
735 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
737 /* Intel defined MSRs. */
738 #define MSR_IA32_P5_MC_ADDR 0x00000000
739 #define MSR_IA32_P5_MC_TYPE 0x00000001
740 #define MSR_IA32_TSC 0x00000010
741 #define MSR_IA32_PLATFORM_ID 0x00000017
742 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
743 #define MSR_EBC_FREQUENCY_ID 0x0000002c
744 #define MSR_SMI_COUNT 0x00000034
746 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
747 #define MSR_IA32_FEAT_CTL 0x0000003a
748 #define FEAT_CTL_LOCKED BIT(0)
749 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
750 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
751 #define FEAT_CTL_SGX_LC_ENABLED BIT(17)
752 #define FEAT_CTL_SGX_ENABLED BIT(18)
753 #define FEAT_CTL_LMCE_ENABLED BIT(20)
755 #define MSR_IA32_TSC_ADJUST 0x0000003b
756 #define MSR_IA32_BNDCFGS 0x00000d90
758 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
760 #define MSR_IA32_XFD 0x000001c4
761 #define MSR_IA32_XFD_ERR 0x000001c5
762 #define MSR_IA32_XSS 0x00000da0
764 #define MSR_IA32_APICBASE 0x0000001b
765 #define MSR_IA32_APICBASE_BSP (1<<8)
766 #define MSR_IA32_APICBASE_ENABLE (1<<11)
767 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
769 #define MSR_IA32_UCODE_WRITE 0x00000079
770 #define MSR_IA32_UCODE_REV 0x0000008b
772 /* Intel SGX Launch Enclave Public Key Hash MSRs */
773 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
774 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
775 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
776 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
778 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
779 #define MSR_IA32_SMBASE 0x0000009e
781 #define MSR_IA32_PERF_STATUS 0x00000198
782 #define MSR_IA32_PERF_CTL 0x00000199
783 #define INTEL_PERF_CTL_MASK 0xffff
785 /* AMD Branch Sampling configuration */
786 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f
787 #define MSR_AMD_SAMP_BR_FROM 0xc0010300
789 #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
791 #define MSR_IA32_MPERF 0x000000e7
792 #define MSR_IA32_APERF 0x000000e8
794 #define MSR_IA32_THERM_CONTROL 0x0000019a
795 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
797 #define THERM_INT_HIGH_ENABLE (1 << 0)
798 #define THERM_INT_LOW_ENABLE (1 << 1)
799 #define THERM_INT_PLN_ENABLE (1 << 24)
801 #define MSR_IA32_THERM_STATUS 0x0000019c
803 #define THERM_STATUS_PROCHOT (1 << 0)
804 #define THERM_STATUS_POWER_LIMIT (1 << 10)
806 #define MSR_THERM2_CTL 0x0000019d
808 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
810 #define MSR_IA32_MISC_ENABLE 0x000001a0
812 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
814 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
815 #define MSR_MISC_PWR_MGMT 0x000001aa
817 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
818 #define ENERGY_PERF_BIAS_PERFORMANCE 0
819 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
820 #define ENERGY_PERF_BIAS_NORMAL 6
821 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
822 #define ENERGY_PERF_BIAS_POWERSAVE 15
824 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
826 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
827 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
828 #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
830 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
832 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
833 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
834 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
835 #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
837 /* Thermal Thresholds Support */
838 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
839 #define THERM_SHIFT_THRESHOLD0 8
840 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
841 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
842 #define THERM_SHIFT_THRESHOLD1 16
843 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
844 #define THERM_STATUS_THRESHOLD0 (1 << 6)
845 #define THERM_LOG_THRESHOLD0 (1 << 7)
846 #define THERM_STATUS_THRESHOLD1 (1 << 8)
847 #define THERM_LOG_THRESHOLD1 (1 << 9)
849 /* MISC_ENABLE bits: architectural */
850 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
851 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
852 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
853 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
854 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
855 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
856 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
857 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
858 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
859 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
860 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
861 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
862 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
863 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
864 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
865 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
866 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
867 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
868 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
869 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
871 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
872 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
873 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
874 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
875 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
876 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
877 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
878 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
879 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
880 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
881 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
882 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
883 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
884 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
885 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
886 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
887 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
888 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
889 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
890 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
891 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
892 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
893 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
894 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
895 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
896 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
897 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
898 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
899 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
900 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
901 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
903 /* MISC_FEATURES_ENABLES non-architectural features */
904 #define MSR_MISC_FEATURES_ENABLES 0x00000140
906 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
907 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
908 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
910 #define MSR_IA32_TSC_DEADLINE 0x000006E0
913 #define MSR_TSX_FORCE_ABORT 0x0000010F
915 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
916 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
917 #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
918 #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
919 #define MSR_TFA_SDV_ENABLE_RTM_BIT 2
920 #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
922 /* P4/Xeon+ specific */
923 #define MSR_IA32_MCG_EAX 0x00000180
924 #define MSR_IA32_MCG_EBX 0x00000181
925 #define MSR_IA32_MCG_ECX 0x00000182
926 #define MSR_IA32_MCG_EDX 0x00000183
927 #define MSR_IA32_MCG_ESI 0x00000184
928 #define MSR_IA32_MCG_EDI 0x00000185
929 #define MSR_IA32_MCG_EBP 0x00000186
930 #define MSR_IA32_MCG_ESP 0x00000187
931 #define MSR_IA32_MCG_EFLAGS 0x00000188
932 #define MSR_IA32_MCG_EIP 0x00000189
933 #define MSR_IA32_MCG_RESERVED 0x0000018a
935 /* Pentium IV performance counter MSRs */
936 #define MSR_P4_BPU_PERFCTR0 0x00000300
937 #define MSR_P4_BPU_PERFCTR1 0x00000301
938 #define MSR_P4_BPU_PERFCTR2 0x00000302
939 #define MSR_P4_BPU_PERFCTR3 0x00000303
940 #define MSR_P4_MS_PERFCTR0 0x00000304
941 #define MSR_P4_MS_PERFCTR1 0x00000305
942 #define MSR_P4_MS_PERFCTR2 0x00000306
943 #define MSR_P4_MS_PERFCTR3 0x00000307
944 #define MSR_P4_FLAME_PERFCTR0 0x00000308
945 #define MSR_P4_FLAME_PERFCTR1 0x00000309
946 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
947 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
948 #define MSR_P4_IQ_PERFCTR0 0x0000030c
949 #define MSR_P4_IQ_PERFCTR1 0x0000030d
950 #define MSR_P4_IQ_PERFCTR2 0x0000030e
951 #define MSR_P4_IQ_PERFCTR3 0x0000030f
952 #define MSR_P4_IQ_PERFCTR4 0x00000310
953 #define MSR_P4_IQ_PERFCTR5 0x00000311
954 #define MSR_P4_BPU_CCCR0 0x00000360
955 #define MSR_P4_BPU_CCCR1 0x00000361
956 #define MSR_P4_BPU_CCCR2 0x00000362
957 #define MSR_P4_BPU_CCCR3 0x00000363
958 #define MSR_P4_MS_CCCR0 0x00000364
959 #define MSR_P4_MS_CCCR1 0x00000365
960 #define MSR_P4_MS_CCCR2 0x00000366
961 #define MSR_P4_MS_CCCR3 0x00000367
962 #define MSR_P4_FLAME_CCCR0 0x00000368
963 #define MSR_P4_FLAME_CCCR1 0x00000369
964 #define MSR_P4_FLAME_CCCR2 0x0000036a
965 #define MSR_P4_FLAME_CCCR3 0x0000036b
966 #define MSR_P4_IQ_CCCR0 0x0000036c
967 #define MSR_P4_IQ_CCCR1 0x0000036d
968 #define MSR_P4_IQ_CCCR2 0x0000036e
969 #define MSR_P4_IQ_CCCR3 0x0000036f
970 #define MSR_P4_IQ_CCCR4 0x00000370
971 #define MSR_P4_IQ_CCCR5 0x00000371
972 #define MSR_P4_ALF_ESCR0 0x000003ca
973 #define MSR_P4_ALF_ESCR1 0x000003cb
974 #define MSR_P4_BPU_ESCR0 0x000003b2
975 #define MSR_P4_BPU_ESCR1 0x000003b3
976 #define MSR_P4_BSU_ESCR0 0x000003a0
977 #define MSR_P4_BSU_ESCR1 0x000003a1
978 #define MSR_P4_CRU_ESCR0 0x000003b8
979 #define MSR_P4_CRU_ESCR1 0x000003b9
980 #define MSR_P4_CRU_ESCR2 0x000003cc
981 #define MSR_P4_CRU_ESCR3 0x000003cd
982 #define MSR_P4_CRU_ESCR4 0x000003e0
983 #define MSR_P4_CRU_ESCR5 0x000003e1
984 #define MSR_P4_DAC_ESCR0 0x000003a8
985 #define MSR_P4_DAC_ESCR1 0x000003a9
986 #define MSR_P4_FIRM_ESCR0 0x000003a4
987 #define MSR_P4_FIRM_ESCR1 0x000003a5
988 #define MSR_P4_FLAME_ESCR0 0x000003a6
989 #define MSR_P4_FLAME_ESCR1 0x000003a7
990 #define MSR_P4_FSB_ESCR0 0x000003a2
991 #define MSR_P4_FSB_ESCR1 0x000003a3
992 #define MSR_P4_IQ_ESCR0 0x000003ba
993 #define MSR_P4_IQ_ESCR1 0x000003bb
994 #define MSR_P4_IS_ESCR0 0x000003b4
995 #define MSR_P4_IS_ESCR1 0x000003b5
996 #define MSR_P4_ITLB_ESCR0 0x000003b6
997 #define MSR_P4_ITLB_ESCR1 0x000003b7
998 #define MSR_P4_IX_ESCR0 0x000003c8
999 #define MSR_P4_IX_ESCR1 0x000003c9
1000 #define MSR_P4_MOB_ESCR0 0x000003aa
1001 #define MSR_P4_MOB_ESCR1 0x000003ab
1002 #define MSR_P4_MS_ESCR0 0x000003c0
1003 #define MSR_P4_MS_ESCR1 0x000003c1
1004 #define MSR_P4_PMH_ESCR0 0x000003ac
1005 #define MSR_P4_PMH_ESCR1 0x000003ad
1006 #define MSR_P4_RAT_ESCR0 0x000003bc
1007 #define MSR_P4_RAT_ESCR1 0x000003bd
1008 #define MSR_P4_SAAT_ESCR0 0x000003ae
1009 #define MSR_P4_SAAT_ESCR1 0x000003af
1010 #define MSR_P4_SSU_ESCR0 0x000003be
1011 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
1013 #define MSR_P4_TBPU_ESCR0 0x000003c2
1014 #define MSR_P4_TBPU_ESCR1 0x000003c3
1015 #define MSR_P4_TC_ESCR0 0x000003c4
1016 #define MSR_P4_TC_ESCR1 0x000003c5
1017 #define MSR_P4_U2L_ESCR0 0x000003b0
1018 #define MSR_P4_U2L_ESCR1 0x000003b1
1020 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
1022 /* Intel Core-based CPU performance counters */
1023 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
1024 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
1025 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
1026 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
1027 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
1028 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
1029 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
1030 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
1032 #define MSR_PERF_METRICS 0x00000329
1034 /* PERF_GLOBAL_OVF_CTL bits */
1035 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
1036 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
1037 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
1038 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
1039 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
1040 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
1042 /* Geode defined MSRs */
1043 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
1046 #define MSR_IA32_VMX_BASIC 0x00000480
1047 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
1048 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
1049 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
1050 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
1051 #define MSR_IA32_VMX_MISC 0x00000485
1052 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
1053 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
1054 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
1055 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
1056 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
1057 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
1058 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
1059 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
1060 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
1061 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
1062 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
1063 #define MSR_IA32_VMX_VMFUNC 0x00000491
1064 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
1066 /* VMX_BASIC bits and bitmasks */
1067 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
1068 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
1069 #define VMX_BASIC_64 0x0001000000000000LLU
1070 #define VMX_BASIC_MEM_TYPE_SHIFT 50
1071 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
1072 #define VMX_BASIC_MEM_TYPE_WB 6LLU
1073 #define VMX_BASIC_INOUT 0x0040000000000000LLU
1075 /* MSR_IA32_VMX_MISC bits */
1076 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
1077 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
1078 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
1081 #define MSR_VM_CR 0xc0010114
1082 #define MSR_VM_IGNNE 0xc0010115
1083 #define MSR_VM_HSAVE_PA 0xc0010117
1085 /* Hardware Feedback Interface */
1086 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
1087 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
1089 /* x2APIC locked status */
1090 #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
1091 #define LEGACY_XAPIC_DISABLED BIT(0) /*
1092 * x2APIC mode is locked and
1093 * disabling x2APIC will cause
1097 #endif /* _ASM_X86_MSR_INDEX_H */