1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 Google, Inc
5 * Taken from coreboot file of the same name
11 #include <asm/atomic.h>
12 #include <asm/cache.h>
14 typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
17 * A mp_flight_record details a sequence of calls for the APs to perform
18 * along with the BSP to coordinate sequencing. Each flight record either
19 * provides a barrier for each AP before calling the callback or the APs
20 * are allowed to perform the callback without waiting. Regardless, each
21 * record has the cpus_entered field incremented for each record. When
22 * the BSP observes that the cpus_entered matches the number of APs
23 * the bsp_call is called with bsp_arg and upon returning releases the
24 * barrier allowing the APs to make further progress.
26 * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
27 * callback will just not be called.
29 struct mp_flight_record {
31 atomic_t cpus_entered;
32 mp_callback_t ap_call;
34 mp_callback_t bsp_call;
36 } __attribute__((aligned(ARCH_DMA_MINALIGN)));
38 #define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
40 .barrier = ATOMIC_INIT(barrier_), \
41 .cpus_entered = ATOMIC_INIT(0), \
42 .ap_call = ap_func_, \
44 .bsp_call = bsp_func_, \
45 .bsp_arg = bsp_arg_, \
48 #define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
49 MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
51 #define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
52 MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
55 * mp_init() will set up the SIPI vector and bring up the APs according to
56 * mp_params. Each flight record will be executed according to the plan. Note
57 * that the MP infrastructure uses SMM default area without saving it. It's
58 * up to the chipset or mainboard to either e820 reserve this area or save this
59 * region prior to calling mp_init() and restoring it after mp_init returns.
61 * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
62 * caching is enabled before running the flight plan.
64 * The MP init has the following properties:
65 * 1. APs are brought up in parallel.
66 * 2. The ordering of cpu number and APIC ids is not deterministic.
67 * Therefore, one cannot rely on this property or the order of devices in
68 * the device tree unless the chipset or mainboard know the APIC ids
71 * mp_init() returns < 0 on error, 0 on success.
75 /* Set up additional CPUs */
76 int x86_mp_init(void);
78 #endif /* _X86_MP_H_ */