1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 Google, Inc
5 * Taken from coreboot file of the same name
11 #include <asm/atomic.h>
12 #include <asm/cache.h>
15 /* Indicates that the function should run on all CPUs */
18 /* Run on boot CPUs */
21 /* Run on non-boot CPUs */
25 typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
28 * A mp_flight_record details a sequence of calls for the APs to perform
29 * along with the BSP to coordinate sequencing. Each flight record either
30 * provides a barrier for each AP before calling the callback or the APs
31 * are allowed to perform the callback without waiting. Regardless, each
32 * record has the cpus_entered field incremented for each record. When
33 * the BSP observes that the cpus_entered matches the number of APs
34 * the bsp_call is called with bsp_arg and upon returning releases the
35 * barrier allowing the APs to make further progress.
37 * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
38 * callback will just not be called.
40 struct mp_flight_record {
42 atomic_t cpus_entered;
43 mp_callback_t ap_call;
45 mp_callback_t bsp_call;
47 } __attribute__((aligned(ARCH_DMA_MINALIGN)));
49 #define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
51 .barrier = ATOMIC_INIT(barrier_), \
52 .cpus_entered = ATOMIC_INIT(0), \
53 .ap_call = ap_func_, \
55 .bsp_call = bsp_func_, \
56 .bsp_arg = bsp_arg_, \
59 #define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
60 MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
62 #define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
63 MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
66 * mp_init() will set up the SIPI vector and bring up the APs according to
67 * mp_params. Each flight record will be executed according to the plan. Note
68 * that the MP infrastructure uses SMM default area without saving it. It's
69 * up to the chipset or mainboard to either e820 reserve this area or save this
70 * region prior to calling mp_init() and restoring it after mp_init returns.
72 * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
73 * caching is enabled before running the flight plan.
75 * The MP init has the following properties:
76 * 1. APs are brought up in parallel.
77 * 2. The ordering of cpu number and APIC ids is not deterministic.
78 * Therefore, one cannot rely on this property or the order of devices in
79 * the device tree unless the chipset or mainboard know the APIC ids
82 * mp_init() returns < 0 on error, 0 on success.
86 /* Set up additional CPUs */
87 int x86_mp_init(void);
89 #endif /* _X86_MP_H_ */