1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 * x86-64 work by Andi Kleen 2002
11 #ifndef _ASM_X86_FPU_INTERNAL_H
12 #define _ASM_X86_FPU_INTERNAL_H
14 #include <linux/compat.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
20 #include <asm/fpu/api.h>
21 #include <asm/fpu/xstate.h>
22 #include <asm/fpu/xcr.h>
23 #include <asm/cpufeature.h>
24 #include <asm/trace/fpu.h>
27 * High level FPU state handling functions:
29 extern int fpu__restore_sig(void __user *buf, int ia32_frame);
30 extern void fpu__drop(struct fpu *fpu);
31 extern void fpu__clear_user_states(struct fpu *fpu);
32 extern void fpu__clear_all(struct fpu *fpu);
33 extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
35 extern void fpu_sync_fpstate(struct fpu *fpu);
37 extern int fpu_clone(struct task_struct *dst);
40 * Boot time FPU initialization functions:
42 extern void fpu__init_cpu(void);
43 extern void fpu__init_system_xstate(void);
44 extern void fpu__init_cpu_xstate(void);
45 extern void fpu__init_system(struct cpuinfo_x86 *c);
46 extern void fpu__init_check_bugs(void);
47 extern void fpu__resume_cpu(void);
52 #ifdef CONFIG_X86_DEBUG_FPU
53 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
55 # define WARN_ON_FPU(x) ({ (void)(x); 0; })
59 * FPU related CPU feature flag helper routines:
61 static __always_inline __pure bool use_xsaveopt(void)
63 return static_cpu_has(X86_FEATURE_XSAVEOPT);
66 static __always_inline __pure bool use_xsave(void)
68 return static_cpu_has(X86_FEATURE_XSAVE);
71 static __always_inline __pure bool use_fxsr(void)
73 return static_cpu_has(X86_FEATURE_FXSR);
77 * fpstate handling functions:
80 extern union fpregs_state init_fpstate;
82 extern void fpstate_init(union fpregs_state *state);
83 #ifdef CONFIG_MATH_EMULATION
84 extern void fpstate_init_soft(struct swregs_state *soft);
86 static inline void fpstate_init_soft(struct swregs_state *soft) {}
88 extern void save_fpregs_to_fpstate(struct fpu *fpu);
90 #define user_insn(insn, output, input...) \
96 asm volatile(ASM_STAC "\n" \
99 ".section .fixup,\"ax\"\n" \
100 "3: movl $-1,%[err]\n" \
103 _ASM_EXTABLE(1b, 3b) \
104 : [err] "=r" (err), output \
109 #define kernel_insn_err(insn, output, input...) \
112 asm volatile("1:" #insn "\n\t" \
114 ".section .fixup,\"ax\"\n" \
115 "3: movl $-1,%[err]\n" \
118 _ASM_EXTABLE(1b, 3b) \
119 : [err] "=r" (err), output \
124 #define kernel_insn(insn, output, input...) \
125 asm volatile("1:" #insn "\n\t" \
127 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore) \
130 static inline int fnsave_to_user_sigframe(struct fregs_state __user *fx)
132 return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
135 static inline int fxsave_to_user_sigframe(struct fxregs_state __user *fx)
137 if (IS_ENABLED(CONFIG_X86_32))
138 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
140 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
144 static inline void fxrstor(struct fxregs_state *fx)
146 if (IS_ENABLED(CONFIG_X86_32))
147 kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
149 kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
152 static inline int fxrstor_safe(struct fxregs_state *fx)
154 if (IS_ENABLED(CONFIG_X86_32))
155 return kernel_insn_err(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
157 return kernel_insn_err(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
160 static inline int fxrstor_from_user_sigframe(struct fxregs_state __user *fx)
162 if (IS_ENABLED(CONFIG_X86_32))
163 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
165 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
168 static inline void frstor(struct fregs_state *fx)
170 kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
173 static inline int frstor_safe(struct fregs_state *fx)
175 return kernel_insn_err(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
178 static inline int frstor_from_user_sigframe(struct fregs_state __user *fx)
180 return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
183 static inline void fxsave(struct fxregs_state *fx)
185 if (IS_ENABLED(CONFIG_X86_32))
186 asm volatile( "fxsave %[fx]" : [fx] "=m" (*fx));
188 asm volatile("fxsaveq %[fx]" : [fx] "=m" (*fx));
191 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
192 #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
193 #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
194 #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
195 #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
196 #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
198 #define XSTATE_OP(op, st, lmask, hmask, err) \
199 asm volatile("1:" op "\n\t" \
200 "xor %[err], %[err]\n" \
202 ".pushsection .fixup,\"ax\"\n\t" \
203 "3: movl $-2,%[err]\n\t" \
206 _ASM_EXTABLE(1b, 3b) \
208 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
212 * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
213 * format and supervisor states in addition to modified optimization in
216 * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
217 * supports modified optimization which is not supported by XSAVE.
219 * We use XSAVE as a fallback.
221 * The 661 label is defined in the ALTERNATIVE* macros as the address of the
222 * original instruction which gets replaced. We need to use it here as the
223 * address of the instruction where we might get an exception at.
225 #define XSTATE_XSAVE(st, lmask, hmask, err) \
226 asm volatile(ALTERNATIVE_2(XSAVE, \
227 XSAVEOPT, X86_FEATURE_XSAVEOPT, \
228 XSAVES, X86_FEATURE_XSAVES) \
230 "xor %[err], %[err]\n" \
232 ".pushsection .fixup,\"ax\"\n" \
233 "4: movl $-2, %[err]\n" \
236 _ASM_EXTABLE(661b, 4b) \
238 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
242 * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
245 #define XSTATE_XRESTORE(st, lmask, hmask) \
246 asm volatile(ALTERNATIVE(XRSTOR, \
247 XRSTORS, X86_FEATURE_XSAVES) \
250 _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
252 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
256 * This function is called only during boot time when x86 caps are not set
257 * up and alternative can not be used yet.
259 static inline void os_xrstor_booting(struct xregs_state *xstate)
263 u32 hmask = mask >> 32;
266 WARN_ON(system_state != SYSTEM_BOOTING);
268 if (boot_cpu_has(X86_FEATURE_XSAVES))
269 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
271 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
274 * We should never fault when copying from a kernel buffer, and the FPU
275 * state we set at boot time should be valid.
281 * Save processor xstate to xsave area.
283 * Uses either XSAVE or XSAVEOPT or XSAVES depending on the CPU features
284 * and command line options. The choice is permanent until the next reboot.
286 static inline void os_xsave(struct xregs_state *xstate)
288 u64 mask = xfeatures_mask_all;
290 u32 hmask = mask >> 32;
293 WARN_ON_FPU(!alternatives_patched);
295 XSTATE_XSAVE(xstate, lmask, hmask, err);
297 /* We should never fault when copying to a kernel buffer: */
302 * Restore processor xstate from xsave area.
304 * Uses XRSTORS when XSAVES is used, XRSTOR otherwise.
306 static inline void os_xrstor(struct xregs_state *xstate, u64 mask)
309 u32 hmask = mask >> 32;
311 XSTATE_XRESTORE(xstate, lmask, hmask);
315 * Save xstate to user space xsave area.
317 * We don't use modified optimization because xrstor/xrstors might track
318 * a different application.
320 * We don't use compacted format xsave area for
321 * backward compatibility for old applications which don't understand
322 * compacted format of xsave area.
324 static inline int xsave_to_user_sigframe(struct xregs_state __user *buf)
326 u64 mask = xfeatures_mask_user();
328 u32 hmask = mask >> 32;
332 * Clear the xsave header first, so that reserved fields are
333 * initialized to zero.
335 err = __clear_user(&buf->header, sizeof(buf->header));
340 XSTATE_OP(XSAVE, buf, lmask, hmask, err);
347 * Restore xstate from user space xsave area.
349 static inline int xrstor_from_user_sigframe(struct xregs_state __user *buf, u64 mask)
351 struct xregs_state *xstate = ((__force struct xregs_state *)buf);
353 u32 hmask = mask >> 32;
357 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
364 * Restore xstate from kernel space xsave area, return an error code instead of
367 static inline int os_xrstor_safe(struct xregs_state *xstate, u64 mask)
370 u32 hmask = mask >> 32;
373 if (cpu_feature_enabled(X86_FEATURE_XSAVES))
374 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
376 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
381 static inline void __restore_fpregs_from_fpstate(union fpregs_state *fpstate, u64 mask)
384 os_xrstor(&fpstate->xsave, mask);
387 fxrstor(&fpstate->fxsave);
389 frstor(&fpstate->fsave);
393 static inline void restore_fpregs_from_fpstate(union fpregs_state *fpstate)
396 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
397 * pending. Clear the x87 state here by setting it to fixed values.
398 * "m" is a random variable that should be in L1.
400 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
404 "fildl %P[addr]" /* set F?P to defined value */
405 : : [addr] "m" (fpstate));
408 __restore_fpregs_from_fpstate(fpstate, -1);
411 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
414 * FPU context switch related helper methods:
417 DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
420 * The in-register FPU state for an FPU context on a CPU is assumed to be
421 * valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx
424 * If the FPU register state is valid, the kernel can skip restoring the
425 * FPU state from memory.
427 * Any code that clobbers the FPU registers or updates the in-memory
428 * FPU state for a task MUST let the rest of the kernel know that the
429 * FPU registers are no longer valid for this task.
431 * Either one of these invalidation functions is enough. Invalidate
432 * a resource you control: CPU if using the CPU for something else
433 * (with preemption disabled), FPU for the current task, or a task that
434 * is prevented from running by the current task.
436 static inline void __cpu_invalidate_fpregs_state(void)
438 __this_cpu_write(fpu_fpregs_owner_ctx, NULL);
441 static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu)
446 static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu)
448 return fpu == this_cpu_read(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
452 * These generally need preemption protection to work,
453 * do try to avoid using these on their own:
455 static inline void fpregs_deactivate(struct fpu *fpu)
457 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
458 trace_x86_fpu_regs_deactivated(fpu);
461 static inline void fpregs_activate(struct fpu *fpu)
463 this_cpu_write(fpu_fpregs_owner_ctx, fpu);
464 trace_x86_fpu_regs_activated(fpu);
468 * Internal helper, do not use directly. Use switch_fpu_return() instead.
470 static inline void __fpregs_load_activate(void)
472 struct fpu *fpu = ¤t->thread.fpu;
473 int cpu = smp_processor_id();
475 if (WARN_ON_ONCE(current->flags & PF_KTHREAD))
478 if (!fpregs_state_valid(fpu, cpu)) {
479 restore_fpregs_from_fpstate(&fpu->state);
480 fpregs_activate(fpu);
483 clear_thread_flag(TIF_NEED_FPU_LOAD);
487 * FPU state switching for scheduling.
489 * This is a two-stage process:
491 * - switch_fpu_prepare() saves the old state.
492 * This is done within the context of the old process.
494 * - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state
495 * will get loaded on return to userspace, or when the kernel needs it.
497 * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
498 * are saved in the current thread's FPU register state.
500 * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
501 * hold current()'s FPU registers. It is required to load the
502 * registers before returning to userland or using the content
505 * The FPU context is only stored/restored for a user task and
506 * PF_KTHREAD is used to distinguish between kernel and user threads.
508 static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu)
510 if (static_cpu_has(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) {
511 save_fpregs_to_fpstate(old_fpu);
513 * The save operation preserved register state, so the
514 * fpu_fpregs_owner_ctx is still @old_fpu. Store the
515 * current CPU number in @old_fpu, so the next return
516 * to user space can avoid the FPU register restore
517 * when is returns on the same CPU and still owns the
520 old_fpu->last_cpu = cpu;
522 trace_x86_fpu_regs_deactivated(old_fpu);
527 * Misc helper functions:
531 * Load PKRU from the FPU context if available. Delay loading of the
532 * complete FPU state until the return to userland.
534 static inline void switch_fpu_finish(struct fpu *new_fpu)
536 u32 pkru_val = init_pkru_value;
537 struct pkru_state *pk;
539 if (!static_cpu_has(X86_FEATURE_FPU))
542 set_thread_flag(TIF_NEED_FPU_LOAD);
544 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
548 * PKRU state is switched eagerly because it needs to be valid before we
549 * return to userland e.g. for a copy_to_user() operation.
551 if (!(current->flags & PF_KTHREAD)) {
553 * If the PKRU bit in xsave.header.xfeatures is not set,
554 * then the PKRU component was in init state, which means
555 * XRSTOR will set PKRU to 0. If the bit is not set then
556 * get_xsave_addr() will return NULL because the PKRU value
557 * in memory is not valid. This means pkru_val has to be
558 * set to 0 and not to init_pkru_value.
560 pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);
561 pkru_val = pk ? pk->pkru : 0;
563 __write_pkru(pkru_val);
566 #endif /* _ASM_X86_FPU_INTERNAL_H */