1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_CPUFEATURES_H
3 #define _ASM_X86_CPUFEATURES_H
5 #ifndef _ASM_X86_REQUIRED_FEATURES_H
6 #include <asm/required-features.h>
9 #ifndef _ASM_X86_DISABLED_FEATURES_H
10 #include <asm/disabled-features.h>
14 * Defines x86 CPU feature bits
16 #define NCAPINTS 21 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
20 * Note: If the comment begins with a quoted string, that string is used
21 * in /proc/cpuinfo instead of the macro name. If the string is "",
22 * this feature bit is not displayed in /proc/cpuinfo at all.
24 * When adding new features here that depend on other features,
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
38 #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
39 #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
40 #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
41 #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
42 #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
43 #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
44 #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
46 #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
47 #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
48 #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
49 #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
50 #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
51 #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
52 #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
53 #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
54 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
56 #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
58 #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
61 /* Don't duplicate feature flags which are redundant with Intel! */
62 #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
63 #define X86_FEATURE_MP ( 1*32+19) /* MP Capable */
64 #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
65 #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
66 #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
67 #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
68 #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
69 #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
70 #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow extensions */
71 #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
75 #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
76 #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
78 /* Other features, Linux-defined mapping, word 3 */
79 /* This range is used for feature bits which conflict or are synthesized */
80 #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
81 #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
82 #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
83 #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
85 /* CPU types for specific tunings: */
86 #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
87 /* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */
88 #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
89 #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
90 #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
91 #define X86_FEATURE_UP ( 3*32+ 9) /* SMP kernel running on UP */
92 #define X86_FEATURE_ART ( 3*32+10) /* Always running timer (ART) */
93 #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
94 #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
95 #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
96 #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
97 #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
98 #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
99 #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
100 /* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
101 #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
102 #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
103 #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
104 #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* CPU topology enum extensions */
105 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
106 #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
107 #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */
108 #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */
109 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */
110 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
111 #define X86_FEATURE_RAPL ( 3*32+29) /* AMD/Hygon RAPL interface */
112 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
113 #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
117 #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
118 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
119 #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */
120 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
121 #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
122 #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer Mode eXtensions */
123 #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
124 #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
125 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
126 #define X86_FEATURE_CID ( 4*32+10) /* Context ID */
127 #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
128 #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
129 #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B instruction */
130 #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
131 #define X86_FEATURE_PDCM ( 4*32+15) /* Perf/Debug Capabilities MSR */
132 #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
133 #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
134 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
135 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
136 #define X86_FEATURE_X2APIC ( 4*32+21) /* X2APIC */
137 #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
138 #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
139 #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* TSC deadline timer */
140 #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
141 #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */
142 #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE instruction enabled in the OS */
143 #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
144 #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit FP conversions */
145 #define X86_FEATURE_RDRAND ( 4*32+30) /* RDRAND instruction */
146 #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
149 #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
150 #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
151 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
152 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
153 #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
154 #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
155 #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
156 #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
157 #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
158 #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
160 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
161 #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
162 #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
163 #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure Virtual Machine */
164 #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
165 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
166 #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
167 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
168 #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
169 #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
170 #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
171 #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
172 #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
173 #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
174 #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
175 #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
176 #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
177 #define X86_FEATURE_TCE ( 6*32+17) /* Translation Cache Extension */
178 #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
179 #define X86_FEATURE_TBM ( 6*32+21) /* Trailing Bit Manipulations */
180 #define X86_FEATURE_TOPOEXT ( 6*32+22) /* Topology extensions CPUID leafs */
181 #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* Core performance counter extensions */
182 #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
183 #define X86_FEATURE_BPEXT ( 6*32+26) /* Data breakpoint extension */
184 #define X86_FEATURE_PTSC ( 6*32+27) /* Performance time-stamp counter */
185 #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
186 #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */
189 * Auxiliary flags: Linux defined - For features scattered in various
190 * CPUID levels like 0x6, 0xA etc, word 7.
192 * Reuse free bits when adding new feature flags!
194 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */
195 #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
196 #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
197 #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
198 #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
199 #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
200 #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
201 #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
202 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
203 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
204 #define X86_FEATURE_XCOMPACTED ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
205 #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
206 #define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
207 #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */
208 #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
209 #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
210 #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
211 #define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
212 #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
213 #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
214 #define X86_FEATURE_PERFMON_V2 ( 7*32+20) /* AMD Performance Monitoring Version 2 */
215 #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
216 #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
217 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
218 #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */
219 #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
220 #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
221 #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
222 #define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */
223 #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
224 #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
225 #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
227 /* Virtualization flags: Linux defined, word 8 */
228 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
229 #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* Intel FlexPriority */
230 #define X86_FEATURE_EPT ( 8*32+ 2) /* Intel Extended Page Table */
231 #define X86_FEATURE_VPID ( 8*32+ 3) /* Intel Virtual Processor ID */
233 #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
234 #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
235 #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
236 #define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
237 #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
238 #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */
239 #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempted function */
240 #define X86_FEATURE_TDX_GUEST ( 8*32+22) /* Intel Trust Domain Extensions Guest */
242 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
243 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
244 #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */
245 #define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */
246 #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
247 #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
248 #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
249 #define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
250 #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
251 #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
252 #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
253 #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
254 #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
255 #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
256 #define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */
257 #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
258 #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
259 #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
260 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
261 #define X86_FEATURE_RDSEED ( 9*32+18) /* RDSEED instruction */
262 #define X86_FEATURE_ADX ( 9*32+19) /* ADCX and ADOX instructions */
263 #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
264 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
265 #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
266 #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
267 #define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */
268 #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
269 #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
270 #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
271 #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
272 #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
273 #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
275 /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
276 #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT instruction */
277 #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC instruction */
278 #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */
279 #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */
280 #define X86_FEATURE_XFD (10*32+ 4) /* "" eXtended Feature Disabling */
283 * Extended auxiliary flags: Linux defined - for features scattered in various
284 * CPUID levels like 0xf, etc.
286 * Reuse free bits when adding new feature flags!
288 #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
289 #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
290 #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
291 #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
292 #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
293 #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
294 #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
295 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
296 #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */
297 #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */
298 #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */
299 #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */
300 #define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
301 #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
302 #define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
303 #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
304 #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
305 #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
306 #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
307 #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
308 #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
309 #define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
310 #define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
312 #define X86_FEATURE_SRSO (11*32+24) /* "" AMD BTB untrain RETs */
313 #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
314 #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
316 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
317 #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
318 #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
319 #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
320 #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
321 #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
322 #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
323 #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
324 #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
325 #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
326 #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
327 #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
329 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
330 #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
331 #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
332 #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
333 #define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */
334 #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
335 #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
336 #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
337 #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
338 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
339 #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */
340 #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
341 #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
342 #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
343 #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
344 #define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
345 #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
346 #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
348 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
349 #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
350 #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
351 #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
352 #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
353 #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
354 #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
355 #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
356 #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
357 #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
358 #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
359 #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
361 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
362 #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
363 #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
364 #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
365 #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
366 #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
367 #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
368 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
369 #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
370 #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
371 #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
372 #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
373 #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
374 #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
375 #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */
376 #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */
377 #define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */
378 #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
380 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
381 #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
382 #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */
383 #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
384 #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
385 #define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
386 #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
387 #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
388 #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
389 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */
390 #define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */
391 #define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
392 #define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */
393 #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
394 #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
395 #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
396 #define X86_FEATURE_BUS_LOCK_DETECT (16*32+24) /* Bus Lock detect */
397 #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */
398 #define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */
399 #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */
400 #define X86_FEATURE_ENQCMD (16*32+29) /* ENQCMD and ENQCMDS instructions */
401 #define X86_FEATURE_SGX_LC (16*32+30) /* Software Guard Extensions Launch Control */
403 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
404 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
405 #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */
406 #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
408 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
409 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
410 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
411 #define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */
412 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
413 #define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */
414 #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
415 #define X86_FEATURE_RTM_ALWAYS_ABORT (18*32+11) /* "" RTM transaction always aborts */
416 #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
417 #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
418 #define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs of more than one type */
419 #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
420 #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
421 #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
422 #define X86_FEATURE_IBT (18*32+20) /* Indirect Branch Tracking */
423 #define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
424 #define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
425 #define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
426 #define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
427 #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
428 #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
429 #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
430 #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
431 #define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
432 #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
434 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
435 #define X86_FEATURE_SME (19*32+ 0) /* AMD Secure Memory Encryption */
436 #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */
437 #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */
438 #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
439 #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
440 #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
442 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
443 #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */
444 #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
445 #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */
446 #define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */
447 #define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */
449 #define X86_FEATURE_SBPB (20*32+27) /* "" Selective Branch Prediction Barrier */
450 #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
451 #define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */
456 #define X86_BUG(x) (NCAPINTS*32 + (x))
458 #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
459 #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
460 #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
461 #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
462 #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
463 #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
464 #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
465 #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
466 #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
469 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
470 * to avoid confusion.
472 #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
474 #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
475 #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
476 #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
477 #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
478 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
479 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
480 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
481 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
482 #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
483 #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
484 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
485 #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
486 #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
487 #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
488 #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
489 #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
490 #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
491 #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
492 #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
493 #define X86_BUG_SMT_RSB X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */
494 #define X86_BUG_GDS X86_BUG(30) /* CPU is affected by Gather Data Sampling */
497 #define X86_BUG_SRSO X86_BUG(1*32 + 0) /* AMD SRSO bug */
498 #define X86_BUG_DIV0 X86_BUG(1*32 + 1) /* AMD DIV0 speculation bug */
499 #endif /* _ASM_X86_CPUFEATURES_H */
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