1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * This file is part of the libpayload project.
5 * Copyright (C) 2008 Advanced Micro Devices, Inc.
8 #ifndef _COREBOOT_TABLES_H
9 #define _COREBOOT_TABLES_H
11 struct timestamp_entry {
16 struct timestamp_table {
21 struct timestamp_entry entries[0]; /* Variable number of entries */
25 /* coreboot-specific timestamp IDs */
26 TS_START_ROMSTAGE = 1,
27 TS_BEFORE_INITRAM = 2,
34 TS_START_RAMSTAGE = 10,
35 TS_START_BOOTBLOCK = 11,
36 TS_END_BOOTBLOCK = 12,
37 TS_START_COPYROM = 13,
43 TS_DEVICE_ENUMERATE = 30,
44 TS_DEVICE_CONFIGURE = 40,
45 TS_DEVICE_ENABLE = 50,
46 TS_DEVICE_INITIALIZE = 60,
50 TS_FINALIZE_CHIPS = 85,
52 TS_ACPI_WAKE_JUMP = 98,
53 TS_SELFBOOT_JUMP = 99,
55 /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
56 TS_START_COPYVER = 501,
58 TS_START_TPMINIT = 503,
60 TS_START_VERIFY_SLOT = 505,
61 TS_END_VERIFY_SLOT = 506,
62 TS_START_HASH_BODY = 507,
63 TS_DONE_LOADING = 508,
64 TS_DONE_HASHING = 509,
65 TS_END_HASH_BODY = 510,
66 TS_START_COPYVPD = 550,
67 TS_END_COPYVPD_RO = 551,
68 TS_END_COPYVPD_RW = 552,
70 /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
71 TS_ME_INFORM_DRAM_WAIT = 940,
72 TS_ME_INFORM_DRAM_DONE = 941,
74 /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
75 TS_FSP_MEMORY_INIT_START = 950,
76 TS_FSP_MEMORY_INIT_END = 951,
77 TS_FSP_TEMP_RAM_EXIT_START = 952,
78 TS_FSP_TEMP_RAM_EXIT_END = 953,
79 TS_FSP_SILICON_INIT_START = 954,
80 TS_FSP_SILICON_INIT_END = 955,
81 TS_FSP_BEFORE_ENUMERATE = 956,
82 TS_FSP_AFTER_ENUMERATE = 957,
83 TS_FSP_BEFORE_FINALIZE = 958,
84 TS_FSP_AFTER_FINALIZE = 959,
85 TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
86 TS_FSP_AFTER_END_OF_FIRMWARE = 961,
88 /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
90 /* U-Boot entry IDs start at 1000 */
91 TS_U_BOOT_INITTED = 1000, /* This is where U-Boot starts */
93 TS_RO_PARAMS_INIT = 1001,
95 TS_RO_VB_SELECT_FIRMWARE = 1003,
96 TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004,
98 TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010,
100 TS_VB_SELECT_AND_LOAD_KERNEL = 1020,
101 TS_VB_EC_VBOOT_DONE = 1030,
102 TS_VB_STORAGE_INIT_DONE = 1040,
103 TS_VB_READ_KERNEL_DONE = 1050,
104 TS_VB_VBOOT_DONE = 1100,
106 TS_START_KERNEL = 1101,
107 TS_KERNEL_DECOMPRESSION = 1102,
108 TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel */
132 #define CB_TAG_UNUSED 0x0000
133 #define CB_TAG_MEMORY 0x0001
135 struct cb_memory_range {
136 struct cbuint64 start;
137 struct cbuint64 size;
142 #define CB_MEM_RESERVED 2
143 #define CB_MEM_ACPI 3
145 #define CB_MEM_UNUSABLE 5
146 #define CB_MEM_VENDOR_RSVD 6
147 #define CB_MEM_TABLE 16
152 struct cb_memory_range map[0];
155 #define CB_TAG_HWRPB 0x0002
163 #define CB_TAG_MAINBOARD 0x0003
165 struct cb_mainboard {
173 #define CB_TAG_VERSION 0x0004
174 #define CB_TAG_EXTRA_VERSION 0x0005
175 #define CB_TAG_BUILD 0x0006
176 #define CB_TAG_COMPILE_TIME 0x0007
177 #define CB_TAG_COMPILE_BY 0x0008
178 #define CB_TAG_COMPILE_HOST 0x0009
179 #define CB_TAG_COMPILE_DOMAIN 0x000a
180 #define CB_TAG_COMPILER 0x000b
181 #define CB_TAG_LINKER 0x000c
182 #define CB_TAG_ASSEMBLER 0x000d
190 #define CB_TAG_SERIAL 0x000f
195 #define CB_SERIAL_TYPE_IO_MAPPED 1
196 #define CB_SERIAL_TYPE_MEMORY_MAPPED 2
203 * Crystal or input frequency to the chip containing the UART.
204 * Provide the board specific details to allow the payload to
205 * initialize the chip containing the UART and make independent
206 * decisions as to which dividers to select and their values
207 * to eventually arrive at the desired console baud-rate.
212 * UART PCI address: bus, device, function
213 * 1 << 31 - Valid bit, PCI UART in use
221 #define CB_TAG_CONSOLE 0x0010
229 #define CB_TAG_CONSOLE_SERIAL8250 0
230 #define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */
231 #define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */
232 #define CB_TAG_CONSOLE_LOGBUF 3
233 #define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */
234 #define CB_TAG_CONSOLE_EHCI 5
236 #define CB_TAG_FORWARD 0x0011
244 #define CB_TAG_FRAMEBUFFER 0x0012
246 struct cb_framebuffer {
249 u64 physical_address;
260 u8 reserved_mask_pos;
261 u8 reserved_mask_size;
264 #define CB_TAG_GPIO 0x0013
265 #define CB_GPIO_ACTIVE_LOW 0
266 #define CB_GPIO_ACTIVE_HIGH 1
267 #define CB_GPIO_MAX_NAME_LENGTH 16
272 u8 name[CB_GPIO_MAX_NAME_LENGTH];
279 struct cb_gpio gpios[0];
282 #define CB_TAG_FDT 0x0014
286 u32 size; /* size of the entire entry */
287 /* the actual FDT gets placed here */
290 #define CB_TAG_VDAT 0x0015
294 u32 size; /* size of the entire entry */
299 #define CB_TAG_TIMESTAMPS 0x0016
300 #define CB_TAG_CBMEM_CONSOLE 0x0017
302 struct cbmem_console {
308 #define CB_TAG_MRC_CACHE 0x0018
310 struct cb_cbmem_tab {
316 #define CB_TAG_VBNV 0x0019
325 #define CB_TAG_VBOOT_HANDOFF 0x0020
327 #define CB_TAG_X86_ROM_MTRR 0x0021
328 struct cb_x86_rom_mtrr {
332 * The variable range MTRR index covering the ROM. If one wants to
333 * enable caching the ROM, the variable MTRR needs to be set to
334 * write-protect. To disable the caching after enabling set the
335 * type to uncacheable
340 #define CB_TAG_DMA 0x0022
341 #define CB_TAG_RAM_OOPS 0x0023
342 #define CB_TAG_ACPI_GNVS 0x0024
344 #define CB_TAG_BOARD_ID 0x0025
348 /* Board ID as retrieved from the board revision GPIOs. */
352 #define CB_TAG_MAC_ADDRS 0x0026
355 u8 pad[2]; /* Pad it to 8 bytes to keep it simple. */
362 struct mac_address mac_addrs[0];
365 #define CB_TAG_WIFI_CALIBRATION 0x0027
367 #define CB_TAG_RAM_CODE 0x0028
374 #define CB_TAG_SPI_FLASH 0x0029
375 struct cb_spi_flash {
383 #define CB_TAG_MTC 0x002b
384 #define CB_TAG_VPD 0x002c
392 #define CB_TAG_BOOT_MEDIA_PARAMS 0x0030
393 struct cb_boot_media_params {
396 /* offsets are relative to start of boot media */
403 #define CB_TAG_CBMEM_ENTRY 0x0031
404 #define CBMEM_ID_SMBIOS 0x534d4254
406 struct cb_cbmem_entry {
414 #define CB_TAG_TSC_INFO 0x0032
422 #define CB_TAG_SERIALNO 0x002a
423 #define CB_MAX_SERIALNO_LENGTH 32
425 #define CB_TAG_ACPI_RSDP 0x0043
427 #define CB_TAG_CMOS_OPTION_TABLE 0x00c8
429 struct cb_cmos_option_table {
433 /* entries follow after this header */
436 #define CB_TAG_OPTION 0x00c9
438 #define CB_CMOS_MAX_NAME_LENGTH 32
440 struct cb_cmos_entries {
447 u8 name[CB_CMOS_MAX_NAME_LENGTH];
450 #define CB_TAG_OPTION_ENUM 0x00ca
451 #define CB_CMOS_MAX_TEXT_LENGTH 32
452 struct cb_cmos_enums {
457 u8 text[CB_CMOS_MAX_TEXT_LENGTH];
460 #define CB_TAG_OPTION_DEFAULTS 0x00cb
461 #define CB_CMOS_IMAGE_BUFFER_SIZE 128
463 struct cb_cmos_defaults {
467 u8 name[CB_CMOS_MAX_NAME_LENGTH];
468 u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE];
471 #define CB_TAG_OPTION_CHECKSUM 0x00cc
472 #define CB_CHECKSUM_NONE 0
473 #define CB_CHECKSUM_PCBIOS 1
475 struct cb_cmos_checksum {
486 #define MEM_RANGE_COUNT(_rec) \
487 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
489 #define MEM_RANGE_PTR(_rec, _idx) \
490 (((u8 *) (_rec)) + sizeof(*(_rec)) \
491 + (sizeof((_rec)->map[0]) * (_idx)))
493 #define MB_VENDOR_STRING(_mb) \
494 (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
496 #define MB_PART_STRING(_mb) \
497 (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
499 #define UNPACK_CB64(_in) \
500 ((((u64) _in.hi) << 32) | _in.lo)
502 #define CBMEM_TOC_RESERVED 512
503 #define MAX_CBMEM_ENTRIES 16
504 #define CBMEM_MAGIC 0x434f5245
513 #define CBMEM_ID_FREESPACE 0x46524545
514 #define CBMEM_ID_GDT 0x4c474454
515 #define CBMEM_ID_ACPI 0x41435049
516 #define CBMEM_ID_CBTABLE 0x43425442
517 #define CBMEM_ID_PIRQ 0x49525154
518 #define CBMEM_ID_MPTABLE 0x534d5054
519 #define CBMEM_ID_RESUME 0x5245534d
520 #define CBMEM_ID_RESUME_SCRATCH 0x52455343
521 #define CBMEM_ID_SMBIOS 0x534d4254
522 #define CBMEM_ID_TIMESTAMP 0x54494d45
523 #define CBMEM_ID_MRCDATA 0x4d524344
524 #define CBMEM_ID_CONSOLE 0x434f4e53
525 #define CBMEM_ID_NONE 0x00000000
528 * high_table_reserve() - reserve configuration table in high memory
530 * This reserves configuration table in high memory.
534 int high_table_reserve(void);
537 * high_table_malloc() - allocate configuration table in high memory
539 * This allocates configuration table in high memory.
541 * @bytes: size of configuration table to be allocated
542 * @return: pointer to configuration table in high memory
544 void *high_table_malloc(size_t bytes);
547 * write_coreboot_table() - write coreboot table
549 * This writes coreboot table at a given address.
551 * @addr: start address to write coreboot table
552 * @cfg_tables: pointer to configuration table memory area
554 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
557 * locate_coreboot_table() - Try to find coreboot tables at standard locations
559 * Return: address of table that was found, or -ve error number
561 long locate_coreboot_table(void);