1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * This file is part of the libpayload project.
5 * Copyright (C) 2008 Advanced Micro Devices, Inc.
8 #ifndef _COREBOOT_TABLES_H
9 #define _COREBOOT_TABLES_H
32 #define CB_TAG_UNUSED 0x0000
33 #define CB_TAG_MEMORY 0x0001
35 struct cb_memory_range {
36 struct cbuint64 start;
42 #define CB_MEM_RESERVED 2
45 #define CB_MEM_UNUSABLE 5
46 #define CB_MEM_VENDOR_RSVD 6
47 #define CB_MEM_TABLE 16
52 struct cb_memory_range map[0];
55 #define CB_TAG_HWRPB 0x0002
63 #define CB_TAG_MAINBOARD 0x0003
73 #define CB_TAG_VERSION 0x0004
74 #define CB_TAG_EXTRA_VERSION 0x0005
75 #define CB_TAG_BUILD 0x0006
76 #define CB_TAG_COMPILE_TIME 0x0007
77 #define CB_TAG_COMPILE_BY 0x0008
78 #define CB_TAG_COMPILE_HOST 0x0009
79 #define CB_TAG_COMPILE_DOMAIN 0x000a
80 #define CB_TAG_COMPILER 0x000b
81 #define CB_TAG_LINKER 0x000c
82 #define CB_TAG_ASSEMBLER 0x000d
90 #define CB_TAG_SERIAL 0x000f
95 #define CB_SERIAL_TYPE_IO_MAPPED 1
96 #define CB_SERIAL_TYPE_MEMORY_MAPPED 2
103 * Crystal or input frequency to the chip containing the UART.
104 * Provide the board specific details to allow the payload to
105 * initialize the chip containing the UART and make independent
106 * decisions as to which dividers to select and their values
107 * to eventually arrive at the desired console baud-rate.
112 * UART PCI address: bus, device, function
113 * 1 << 31 - Valid bit, PCI UART in use
121 #define CB_TAG_CONSOLE 0x0010
129 #define CB_TAG_CONSOLE_SERIAL8250 0
130 #define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */
131 #define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */
132 #define CB_TAG_CONSOLE_LOGBUF 3
133 #define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */
134 #define CB_TAG_CONSOLE_EHCI 5
136 #define CB_TAG_FORWARD 0x0011
144 #define CB_TAG_FRAMEBUFFER 0x0012
146 struct cb_framebuffer {
149 u64 physical_address;
160 u8 reserved_mask_pos;
161 u8 reserved_mask_size;
164 #define CB_TAG_GPIO 0x0013
165 #define GPIO_MAX_NAME_LENGTH 16
171 u8 name[GPIO_MAX_NAME_LENGTH];
178 struct cb_gpio gpios[0];
181 #define CB_TAG_FDT 0x0014
185 uint32_t size; /* size of the entire entry */
186 /* the actual FDT gets placed here */
189 #define CB_TAG_VDAT 0x0015
193 uint32_t size; /* size of the entire entry */
198 #define CB_TAG_TIMESTAMPS 0x0016
199 #define CB_TAG_CBMEM_CONSOLE 0x0017
200 #define CB_TAG_MRC_CACHE 0x0018
202 struct cb_cbmem_tab {
208 #define CB_TAG_VBNV 0x0019
217 #define CB_TAG_CMOS_OPTION_TABLE 0x00c8
219 struct cb_cmos_option_table {
225 #define CB_TAG_OPTION 0x00c9
227 #define CMOS_MAX_NAME_LENGTH 32
229 struct cb_cmos_entries {
236 u8 name[CMOS_MAX_NAME_LENGTH];
239 #define CB_TAG_OPTION_ENUM 0x00ca
240 #define CMOS_MAX_TEXT_LENGTH 32
242 struct cb_cmos_enums {
247 u8 text[CMOS_MAX_TEXT_LENGTH];
250 #define CB_TAG_OPTION_DEFAULTS 0x00cb
251 #define CMOS_IMAGE_BUFFER_SIZE 128
253 struct cb_cmos_defaults {
257 u8 name[CMOS_MAX_NAME_LENGTH];
258 u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
261 #define CB_TAG_OPTION_CHECKSUM 0x00cc
262 #define CHECKSUM_NONE 0
263 #define CHECKSUM_PCBIOS 1
265 struct cb_cmos_checksum {
276 #define MEM_RANGE_COUNT(_rec) \
277 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
279 #define MEM_RANGE_PTR(_rec, _idx) \
280 (((u8 *) (_rec)) + sizeof(*(_rec)) \
281 + (sizeof((_rec)->map[0]) * (_idx)))
283 #define MB_VENDOR_STRING(_mb) \
284 (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
286 #define MB_PART_STRING(_mb) \
287 (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
289 #define UNPACK_CB64(_in) \
290 ((((u64) _in.hi) << 32) | _in.lo)
292 #define CBMEM_TOC_RESERVED 512
293 #define MAX_CBMEM_ENTRIES 16
294 #define CBMEM_MAGIC 0x434f5245
303 #define CBMEM_ID_FREESPACE 0x46524545
304 #define CBMEM_ID_GDT 0x4c474454
305 #define CBMEM_ID_ACPI 0x41435049
306 #define CBMEM_ID_CBTABLE 0x43425442
307 #define CBMEM_ID_PIRQ 0x49525154
308 #define CBMEM_ID_MPTABLE 0x534d5054
309 #define CBMEM_ID_RESUME 0x5245534d
310 #define CBMEM_ID_RESUME_SCRATCH 0x52455343
311 #define CBMEM_ID_SMBIOS 0x534d4254
312 #define CBMEM_ID_TIMESTAMP 0x54494d45
313 #define CBMEM_ID_MRCDATA 0x4d524344
314 #define CBMEM_ID_CONSOLE 0x434f4e53
315 #define CBMEM_ID_NONE 0x00000000
318 * high_table_reserve() - reserve configuration table in high memory
320 * This reserves configuration table in high memory.
324 int high_table_reserve(void);
327 * high_table_malloc() - allocate configuration table in high memory
329 * This allocates configuration table in high memory.
331 * @bytes: size of configuration table to be allocated
332 * @return: pointer to configuration table in high memory
334 void *high_table_malloc(size_t bytes);
337 * write_coreboot_table() - write coreboot table
339 * This writes coreboot table at a given address.
341 * @addr: start address to write coreboot table
342 * @cfg_tables: pointer to configuration table memory area
344 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
347 * locate_coreboot_table() - Try to find coreboot tables at standard locations
349 * @return address of table that was found, or -ve error number
351 long locate_coreboot_table(void);