1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * This file is part of the libpayload project.
5 * Copyright (C) 2008 Advanced Micro Devices, Inc.
8 #ifndef _COREBOOT_SYSINFO_H
9 #define _COREBOOT_SYSINFO_H
11 #include <asm/coreboot_tables.h>
13 /* Maximum number of memory range definitions */
14 #define SYSINFO_MAX_MEM_RANGES 32
15 /* Allow a maximum of 8 GPIOs */
16 #define SYSINFO_MAX_GPIOS 8
17 /* Up to 10 MAC addresses */
18 #define SYSINFO_MAX_MACS 10
19 /* Track the first 32 unimplemented tags */
20 #define SYSINFO_MAX_UNIMPL 32
23 * struct sysinfo_t - Information passed to U-Boot from coreboot
25 * Coreboot passes on a lot of information using a list of individual data
26 * structures identified by a numeric tag. These are parsed in U-Boot to produce
27 * this struct. Some of the pointers here point back to the tagged data
28 * structure, since it is assumed to remain around while U-Boot is running.
30 * The 'cbsysinfo' command can display this information.
32 * @cpu_khz: CPU frequence in KHz (e.g. 1100000)
33 * @serial: Pointer to the serial information, NULL if none
34 * @ser_ioport: Not actually provided by a tag and not used on modern hardware,
35 * which typicaally uses a memory-mapped port
36 * @ser_base: Not used at all, but present to match up with the coreboot data
38 * @n_memranges: Number of memory ranges
39 * @memrange: List of memory ranges:
40 * @base: Base address of range
41 * @size: Size of range in bytes
42 * @type: Type of range (CB_MEM_RAM, etc.)
43 * @option_table: Provides a pointer to the CMOS RAM options table, which
44 * indicates which options are available. The header is followed by a list
45 * of struct cb_cmos_entries records, so that an option can be found from
46 * its name. This is not used in U-Boot. NULL if not present
47 * @cmos_range_start: Start bit of the CMOS checksum range (in fact this must
49 * @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is
51 * @cmos_checksum_location: Location of checksum, multiplied by 8. This is the
52 * byte offset into the CMOS RAM of the first checksum byte. The second one
53 * follows immediately. The checksum is a simple 16-bit sum of all the
54 * bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive,
55 * in big-endian format (so sum >> 8 is stored in the first byte).
56 * @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot
58 * @vbnv_size: Number of bytes used by Chromium OS verified boot (typically
60 * @extra_version: Extra version information, typically ""
61 * @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020"
62 * @compile_time: Compilation time, e.g. "02:51:58"
63 * @compile_by: Who compiled coreboot (never set?)
64 * @compile_host: Name of the machine that compiled coreboot (never set?)
65 * @compile_domain: Domain name of the machine that compiled coreboot (never
67 * @compiler: Name of the compiler used to build coreboot (never set?)
68 * @linker: Name of the linker used to build coreboot (never set?)
69 * @assembler: Name of the assembler used to build coreboot (never set?)
70 * @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d
71 * @framebuffer: Address of framebuffer tag, or NULL if none. See
72 * struct cb_framebuffer for the definition
73 * @num_gpios: Number of verified-boot GPIOs
74 * @gpios: List of GPIOs:
75 * @port: GPIO number, or 0xffffffff if not a GPIO
76 * @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH
77 * @value: Value of GPIO (0 or 1)
81 * id: port polarity val name
82 * 0: - active-high 1 write protect
83 * 1: - active-high 0 recovery
84 * 2: - active-high 1 lid
85 * 3: - active-high 0 power
86 * 4: - active-high 0 oprom
87 * 5: 29 active-high 0 EC in RW
89 * @num_macs: Number of MAC addresses
90 * @macs: List of MAC addresses
91 * @serialno: Serial number, or NULL (never set?)
92 * @mbtable: Address of the multiboot table, or NULL. This is a
93 * struct multiboot_header, not used in U-Boot
94 * @header: Address of header, if there is a CB_TAG_FORWARD, else NULL
95 * @mainboard: Pointer to mainboard info or NULL. Typically the vendor is
96 * "Google" and the part number is ""
97 * @vboot_handoff: Pointer to Chromium OS verified boot hand-off information.
98 * This is struct vboot_handoff, providing access to internal information
99 * generated by coreboot when this is being used
100 * @vboot_handoff_size: Size of hand-off information (typically 0xc0c)
101 * @vdat_addr: Pointer to Chromium OS verified boot data, which uses
102 * struct chromeos_acpi. It sits in the Intel Global NVS struct, after the
104 * @vdat_size: Size of this data, typically 0xf00
105 * @smbios_start: Address of SMBIOS tables
106 * @smbios_size: Size of SMBIOS tables (e.g. 0x800)
107 * @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot
108 * @tstamp_table: Pointer to timestamp_table, struct timestamp_table
109 * @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides
110 * access to the console output generated by coreboot, typically about 64KB
111 * and mostly PCI enumeration info
112 * @mrc_cache: Pointer to memory-reference-code cache, typically NULL
113 * acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs
114 * @board_id: Board ID indicating the board variant, typically 0xffffffff
115 * @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff
116 * @wifi_calibration: WiFi calibration info, NULL if none
117 * @ramoops_buffer: Address of kernel Ramoops buffer
118 * @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB
119 * @spi_flash: Information about SPI flash:
120 * @size: Size in bytes, e.g. 16MB
121 * @sector_size; Sector size of flash device, e.g. 4KB
122 * @erase_cmd: Command used to erase flash, or 0 if not used
123 * @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a
124 * __FMAP__ header. It provides information about the different top-level
125 * sections in the SPI flash, e.g. 0x204000
126 * @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for
127 * read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in
128 * the flash map. It holds various coreboot binaries as well as
129 * video-configuration files and graphics data for the Chromium OS
130 * verified boot user interface.
131 * @cbfs_size: Size of CBFS, e.g. 0x17b000
132 * @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB
133 * @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See
134 * https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c
135 * @mtc_size: Size of MTC region
136 * @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
138 * @rsdp: Pointer to ACPI RSDP table
139 * @unimpl_count: Number of entries in unimpl_map[]
140 * @unimpl: List of unimplemented IDs (bottom 8 bits only)
141 * @table_size: Number of bytes taken up by the sysinfo table
142 * @rec_count: Number of records in the sysinfo table
145 unsigned int cpu_khz;
146 struct cb_serial *serial;
147 unsigned short ser_ioport;
148 unsigned long ser_base; // for mmapped serial
153 unsigned long long base;
154 unsigned long long size;
156 } memrange[SYSINFO_MAX_MEM_RANGES];
158 struct cb_cmos_option_table *option_table;
159 u32 cmos_range_start;
161 u32 cmos_checksum_location;
171 char *compile_domain;
178 struct cb_framebuffer *framebuffer;
181 struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
183 struct mac_address macs[SYSINFO_MAX_MACS];
186 unsigned long *mbtable; /** Pointer to the multiboot table */
188 struct cb_header *header;
189 struct cb_mainboard *mainboard;
192 u32 vboot_handoff_size;
198 int x86_rom_var_mtrr_index;
206 void *wifi_calibration;
208 u32 ramoops_buffer_size;
223 u8 unimpl[SYSINFO_MAX_UNIMPL];
228 extern struct sysinfo_t lib_sysinfo;
231 * get_coreboot_info() - parse the coreboot sysinfo table
233 * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
236 * @info: Place to put the parsed information
237 * Return: 0 if OK, -ENOENT if no table found
239 int get_coreboot_info(struct sysinfo_t *info);
242 * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
244 * Return: pointer to sysinfo, or NULL if not available
246 const struct sysinfo_t *cb_get_sysinfo(void);