2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Message Bus Ports */
11 #define MSG_PORT_MEM_ARBITER 0x00
12 #define MSG_PORT_HOST_BRIDGE 0x03
13 #define MSG_PORT_RMU 0x04
14 #define MSG_PORT_MEM_MGR 0x05
15 #define MSG_PORT_SOC_UNIT 0x31
17 /* Port 0x00: Memory Arbiter Message Port Registers */
19 /* Enhanced Configuration Space */
22 /* Port 0x03: Host Bridge Message Port Registers */
24 /* Host Memory I/O Boundary */
27 /* Extended Configuration Space */
30 /* Port 0x04: Remote Management Unit Message Port Registers */
32 /* ACPI PBLK Base Address Register */
35 /* SPI DMA Base Address Register */
36 #define SPI_DMA_BA 0x7a
38 /* Port 0x05: Memory Manager Message Port Registers */
40 /* eSRAM Block Page Control */
41 #define ESRAM_BLK_CTRL 0x82
42 #define ESRAM_BLOCK_MODE 0x10000000
45 #define DRAM_BASE 0x00000000
46 #define DRAM_MAX_SIZE 0x80000000
49 #define ESRAM_SIZE 0x80000
51 /* Memory BAR Enable */
52 #define MEM_BAR_EN 0x00000001
55 #define IO_BAR_EN 0x80000000
57 /* 64KiB of RMU binary in flash */
58 #define RMU_BINARY_SIZE 0x10000
60 /* Legacy Bridge PCI Configuration Registers */
62 #define LB_PM1BLK 0x48
63 #define LB_GPE0BLK 0x4c
65 #define LB_PABCDRC 0x60
66 #define LB_PEFGHRC 0x64
72 #endif /* _QUARK_H_ */