2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
6 * Copyright (C) 2008-2009 coresystems GmbH
7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
9 * SPDX-License-Identifier: GPL-2.0
12 #ifndef _ASM_ARCH_PCH_H
13 #define _ASM_ARCH_PCH_H
18 #define PCH_TYPE_CPT 0x1c /* CougarPoint */
19 #define PCH_TYPE_PPT 0x1e /* IvyBridge */
21 /* PCH stepping values for LPC device */
28 #define DEFAULT_GPIOBASE 0x0480
29 #define DEFAULT_PMBASE 0x0500
31 #define SMBUS_IO_BASE 0x0400
33 #define MAINBOARD_POWER_OFF 0
34 #define MAINBOARD_POWER_ON 1
35 #define MAINBOARD_POWER_KEEP 2
37 /* PCI Configuration Space (D30:F0): PCI2PCI */
47 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
48 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
49 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
50 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
51 #define PCH_PCIE_DEV_SLOT 28
53 #define PCH_DEV PCI_BDF(0, 0, 0)
54 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
56 /* PCI Configuration Space (D31:F0): LPC */
57 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
58 #define SERIRQ_CNTL 0x64
60 #define GEN_PMCON_1 0xa0
61 #define GEN_PMCON_2 0xa2
62 #define GEN_PMCON_3 0xa4
64 #define ETR3_CWORWRE (1 << 18)
65 #define ETR3_CF9GR (1 << 20)
67 /* GEN_PMCON_3 bits */
68 #define RTC_BATTERY_DEAD (1 << 2)
69 #define RTC_POWER_FAILED (1 << 1)
70 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
73 #define ACPI_CNTL 0x44
74 #define BIOS_CNTL 0xDC
75 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
76 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
77 #define GPIO_ROUT 0xb8
79 #define PIRQA_ROUT 0x60
80 #define PIRQB_ROUT 0x61
81 #define PIRQC_ROUT 0x62
82 #define PIRQD_ROUT 0x63
83 #define PIRQE_ROUT 0x68
84 #define PIRQF_ROUT 0x69
85 #define PIRQG_ROUT 0x6A
86 #define PIRQH_ROUT 0x6B
88 #define GEN_PMCON_1 0xa0
89 #define GEN_PMCON_2 0xa2
90 #define GEN_PMCON_3 0xa4
92 #define ETR3_CWORWRE (1 << 18)
93 #define ETR3_CF9GR (1 << 20)
96 #define ACPI_CNTL 0x44
97 #define BIOS_CNTL 0xDC
98 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
99 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
100 #define GPIO_ROUT 0xb8
102 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
103 #define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
104 #define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
105 #define LPC_EN 0x82 /* LPC IF Enables Register */
106 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
107 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
108 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
109 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
110 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
111 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
112 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
113 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
114 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
115 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
116 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
117 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
118 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
119 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
120 #define LPC_GENX_DEC(x) (0x84 + 4 * (x))
121 #define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
122 #define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
123 #define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
124 #define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
125 #define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
126 #define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
127 #define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
128 #define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
130 /* PCI Configuration Space (D31:F1): IDE */
131 #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
132 #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
133 #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
136 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
137 #define IDE_DECODE_ENABLE (1 << 15)
138 #define IDE_SITRE (1 << 14)
139 #define IDE_ISP_5_CLOCKS (0 << 12)
140 #define IDE_ISP_4_CLOCKS (1 << 12)
141 #define IDE_ISP_3_CLOCKS (2 << 12)
142 #define IDE_RCT_4_CLOCKS (0 << 8)
143 #define IDE_RCT_3_CLOCKS (1 << 8)
144 #define IDE_RCT_2_CLOCKS (2 << 8)
145 #define IDE_RCT_1_CLOCKS (3 << 8)
146 #define IDE_DTE1 (1 << 7)
147 #define IDE_PPE1 (1 << 6)
148 #define IDE_IE1 (1 << 5)
149 #define IDE_TIME1 (1 << 4)
150 #define IDE_DTE0 (1 << 3)
151 #define IDE_PPE0 (1 << 2)
152 #define IDE_IE0 (1 << 1)
153 #define IDE_TIME0 (1 << 0)
154 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
156 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
157 #define IDE_SSDE1 (1 << 3)
158 #define IDE_SSDE0 (1 << 2)
159 #define IDE_PSDE1 (1 << 1)
160 #define IDE_PSDE0 (1 << 0)
162 #define IDE_SDMA_TIM 0x4a
164 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
165 #define SIG_MODE_SEC_NORMAL (0 << 18)
166 #define SIG_MODE_SEC_TRISTATE (1 << 18)
167 #define SIG_MODE_SEC_DRIVELOW (2 << 18)
168 #define SIG_MODE_PRI_NORMAL (0 << 16)
169 #define SIG_MODE_PRI_TRISTATE (1 << 16)
170 #define SIG_MODE_PRI_DRIVELOW (2 << 16)
171 #define FAST_SCB1 (1 << 15)
172 #define FAST_SCB0 (1 << 14)
173 #define FAST_PCB1 (1 << 13)
174 #define FAST_PCB0 (1 << 12)
175 #define SCB1 (1 << 3)
176 #define SCB0 (1 << 2)
177 #define PCB1 (1 << 1)
178 #define PCB0 (1 << 0)
180 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
181 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
182 #define SATA_SP 0xd0 /* Scratchpad */
184 /* SATA IOBP Registers */
185 #define SATA_IOBP_SP0G3IR 0xea000151
186 #define SATA_IOBP_SP1G3IR 0xea000051
188 /* PCI Configuration Space (D31:F3): SMBus */
189 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
190 #define SMB_BASE 0x20
192 #define SMB_RCV_SLVA 0x09
195 #define I2C_EN (1 << 2)
196 #define SMB_SMI_EN (1 << 1)
197 #define HST_EN (1 << 0)
199 /* SMBus I/O bits. */
200 #define SMBHSTSTAT 0x0
201 #define SMBHSTCTL 0x2
202 #define SMBHSTCMD 0x3
203 #define SMBXMITADD 0x4
204 #define SMBHSTDAT0 0x5
205 #define SMBHSTDAT1 0x6
206 #define SMBBLKDAT 0x7
207 #define SMBTRNSADD 0x9
208 #define SMBSLVDATA 0xa
209 #define SMLINK_PIN_CTL 0xe
210 #define SMBUS_PIN_CTL 0xf
212 #define SMBUS_TIMEOUT (10 * 1000 * 100)
214 #define VCH 0x0000 /* 32bit */
215 #define VCAP1 0x0004 /* 32bit */
216 #define VCAP2 0x0008 /* 32bit */
217 #define PVC 0x000c /* 16bit */
218 #define PVS 0x000e /* 16bit */
220 #define V0CAP 0x0010 /* 32bit */
221 #define V0CTL 0x0014 /* 32bit */
222 #define V0STS 0x001a /* 16bit */
224 #define V1CAP 0x001c /* 32bit */
225 #define V1CTL 0x0020 /* 32bit */
226 #define V1STS 0x0026 /* 16bit */
228 #define RCTCL 0x0100 /* 32bit */
229 #define ESD 0x0104 /* 32bit */
230 #define ULD 0x0110 /* 32bit */
231 #define ULBA 0x0118 /* 64bit */
233 #define RP1D 0x0120 /* 32bit */
234 #define RP1BA 0x0128 /* 64bit */
235 #define RP2D 0x0130 /* 32bit */
236 #define RP2BA 0x0138 /* 64bit */
237 #define RP3D 0x0140 /* 32bit */
238 #define RP3BA 0x0148 /* 64bit */
239 #define RP4D 0x0150 /* 32bit */
240 #define RP4BA 0x0158 /* 64bit */
241 #define HDD 0x0160 /* 32bit */
242 #define HDBA 0x0168 /* 64bit */
243 #define RP5D 0x0170 /* 32bit */
244 #define RP5BA 0x0178 /* 64bit */
245 #define RP6D 0x0180 /* 32bit */
246 #define RP6BA 0x0188 /* 64bit */
248 #define RPC 0x0400 /* 32bit */
249 #define RPFN 0x0404 /* 32bit */
251 #define TRSR 0x1e00 /* 8bit */
252 #define TRCR 0x1e10 /* 64bit */
253 #define TWDR 0x1e18 /* 64bit */
255 #define IOTR0 0x1e80 /* 64bit */
256 #define IOTR1 0x1e88 /* 64bit */
257 #define IOTR2 0x1e90 /* 64bit */
258 #define IOTR3 0x1e98 /* 64bit */
260 #define TCTL 0x3000 /* 8bit */
268 #define DIR_IDR 12 /* Interrupt D Pin Offset */
269 #define DIR_ICR 8 /* Interrupt C Pin Offset */
270 #define DIR_IBR 4 /* Interrupt B Pin Offset */
271 #define DIR_IAR 0 /* Interrupt A Pin Offset */
282 /* IO Buffer Programming */
283 #define IOBPIRI 0x2330
286 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
287 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
288 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
290 #define D31IP 0x3100 /* 32bit */
291 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
292 #define D31IP_SIP2 20 /* SATA Pin 2 */
293 #define D31IP_SMIP 12 /* SMBUS Pin */
294 #define D31IP_SIP 8 /* SATA Pin */
295 #define D30IP 0x3104 /* 32bit */
296 #define D30IP_PIP 0 /* PCI Bridge Pin */
297 #define D29IP 0x3108 /* 32bit */
298 #define D29IP_E1P 0 /* EHCI #1 Pin */
299 #define D28IP 0x310c /* 32bit */
300 #define D28IP_P8IP 28 /* PCI Express Port 8 */
301 #define D28IP_P7IP 24 /* PCI Express Port 7 */
302 #define D28IP_P6IP 20 /* PCI Express Port 6 */
303 #define D28IP_P5IP 16 /* PCI Express Port 5 */
304 #define D28IP_P4IP 12 /* PCI Express Port 4 */
305 #define D28IP_P3IP 8 /* PCI Express Port 3 */
306 #define D28IP_P2IP 4 /* PCI Express Port 2 */
307 #define D28IP_P1IP 0 /* PCI Express Port 1 */
308 #define D27IP 0x3110 /* 32bit */
309 #define D27IP_ZIP 0 /* HD Audio Pin */
310 #define D26IP 0x3114 /* 32bit */
311 #define D26IP_E2P 0 /* EHCI #2 Pin */
312 #define D25IP 0x3118 /* 32bit */
313 #define D25IP_LIP 0 /* GbE LAN Pin */
314 #define D22IP 0x3124 /* 32bit */
315 #define D22IP_KTIP 12 /* KT Pin */
316 #define D22IP_IDERIP 8 /* IDE-R Pin */
317 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
318 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
319 #define D20IP 0x3128 /* 32bit */
320 #define D20IP_XHCIIP 0
321 #define D31IR 0x3140 /* 16bit */
322 #define D30IR 0x3142 /* 16bit */
323 #define D29IR 0x3144 /* 16bit */
324 #define D28IR 0x3146 /* 16bit */
325 #define D27IR 0x3148 /* 16bit */
326 #define D26IR 0x314c /* 16bit */
327 #define D25IR 0x3150 /* 16bit */
328 #define D22IR 0x315c /* 16bit */
329 #define D20IR 0x3160 /* 16bit */
330 #define OIC 0x31fe /* 16bit */
332 #define SPI_FREQ_SWSEQ 0x3893
333 #define SPI_DESC_COMP0 0x38b0
334 #define SPI_FREQ_WR_ERA 0x38b4
336 #define DIR_ROUTE(a, b, c, d) \
337 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
338 ((b) << DIR_IBR) | ((a) << DIR_IAR))
340 #define RC 0x3400 /* 32bit */
341 #define HPTC 0x3404 /* 32bit */
342 #define GCS 0x3410 /* 32bit */
343 #define BUC 0x3414 /* 32bit */
344 #define PCH_DISABLE_GBE (1 << 5)
345 #define FD 0x3418 /* 32bit */
346 #define DISPBDF 0x3424 /* 16bit */
347 #define FD2 0x3428 /* 32bit */
348 #define CG 0x341c /* 32bit */
350 /* Function Disable 1 RCBA 0x3418 */
351 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
352 #define PCH_DISABLE_P2P (1 << 1)
353 #define PCH_DISABLE_SATA1 (1 << 2)
354 #define PCH_DISABLE_SMBUS (1 << 3)
355 #define PCH_DISABLE_HD_AUDIO (1 << 4)
356 #define PCH_DISABLE_EHCI2 (1 << 13)
357 #define PCH_DISABLE_LPC (1 << 14)
358 #define PCH_DISABLE_EHCI1 (1 << 15)
359 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
360 #define PCH_DISABLE_THERMAL (1 << 24)
361 #define PCH_DISABLE_SATA2 (1 << 25)
362 #define PCH_DISABLE_XHCI (1 << 27)
364 /* Function Disable 2 RCBA 0x3428 */
365 #define PCH_DISABLE_KT (1 << 4)
366 #define PCH_DISABLE_IDER (1 << 3)
367 #define PCH_DISABLE_MEI2 (1 << 2)
368 #define PCH_DISABLE_MEI1 (1 << 1)
369 #define PCH_ENABLE_DBDF (1 << 0)
372 #define GPIO_USE_SEL 0x00
373 #define GP_IO_SEL 0x04
375 #define GPO_BLINK 0x18
377 #define GPIO_USE_SEL2 0x30
378 #define GP_IO_SEL2 0x34
380 #define GPIO_USE_SEL3 0x40
381 #define GP_IO_SEL3 0x44
383 #define GP_RST_SEL1 0x60
384 #define GP_RST_SEL2 0x64
385 #define GP_RST_SEL3 0x68
389 #define WAK_STS (1 << 15)
390 #define PCIEXPWAK_STS (1 << 14)
391 #define PRBTNOR_STS (1 << 11)
392 #define RTC_STS (1 << 10)
393 #define PWRBTN_STS (1 << 8)
394 #define GBL_STS (1 << 5)
395 #define BM_STS (1 << 4)
396 #define TMROF_STS (1 << 0)
398 #define PCIEXPWAK_DIS (1 << 14)
399 #define RTC_EN (1 << 10)
400 #define PWRBTN_EN (1 << 8)
401 #define GBL_EN (1 << 5)
402 #define TMROF_EN (1 << 0)
404 #define SLP_EN (1 << 13)
405 #define SLP_TYP (7 << 10)
411 #define GBL_RLS (1 << 2)
412 #define BM_RLD (1 << 1)
413 #define SCI_EN (1 << 0)
415 #define PROC_CNT 0x10
419 #define PM2_CNT 0x50 /* mobile only */
420 #define GPE0_STS 0x20
421 #define PME_B0_STS (1 << 13)
422 #define PME_STS (1 << 11)
423 #define BATLOW_STS (1 << 10)
424 #define PCI_EXP_STS (1 << 9)
425 #define RI_STS (1 << 8)
426 #define SMB_WAK_STS (1 << 7)
427 #define TCOSCI_STS (1 << 6)
428 #define SWGPE_STS (1 << 2)
429 #define HOT_PLUG_STS (1 << 1)
431 #define PME_B0_EN (1 << 13)
432 #define PME_EN (1 << 11)
433 #define TCOSCI_EN (1 << 6)
435 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
436 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
437 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
438 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
439 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
440 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
441 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
442 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
443 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
444 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
445 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
446 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */
447 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
449 #define ALT_GP_SMI_EN 0x38
450 #define ALT_GP_SMI_STS 0x3a
451 #define GPE_CNTL 0x42
452 #define DEVACT_STS 0x44
455 #define TCO1_STS 0x64
456 #define DMISCI_STS (1 << 9)
457 #define TCO2_STS 0x66
460 * pch_silicon_revision() - Read silicon device ID from the PCH
463 * @return silicon device ID
465 int pch_silicon_type(struct udevice *dev);
468 * pch_pch_iobp_update() - Update a pch register
471 * @address: Address to update
472 * @andvalue: Value to AND with existing value
473 * @orvalue: Value to OR with existing value
475 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,