1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016 Google, Inc
6 #ifndef __asm_arch_rcba_h
7 #define __asm_arch_rcba_h
9 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
10 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
12 #define DEEP_S3_POL 0x3328 /* 32bit */
13 #define DEEP_S3_EN_AC (1 << 0)
14 #define DEEP_S3_EN_DC (1 << 1)
15 #define DEEP_S5_POL 0x3330 /* 32bit */
16 #define DEEP_S5_EN_AC (1 << 14)
17 #define DEEP_S5_EN_DC (1 << 15)
18 #define DEEP_SX_CONFIG 0x3334 /* 32bit */
19 #define DEEP_SX_WAKE_PIN_EN (1 << 2)
20 #define DEEP_SX_ACPRESENT_PD (1 << 1)
21 #define DEEP_SX_GP27_PIN_EN (1 << 0)
22 #define PMSYNC_CONFIG 0x33c4 /* 32bit */
23 #define PMSYNC_CONFIG2 0x33cc /* 32bit */
25 #define RC 0x3400 /* 32bit */
26 #define HPTC 0x3404 /* 32bit */
27 #define GCS 0x3410 /* 32bit */
28 #define BUC 0x3414 /* 32bit */
29 #define PCH_DISABLE_GBE (1 << 5)
30 #define FD 0x3418 /* 32bit */
31 #define FDSW 0x3420 /* 8bit */
32 #define DISPBDF 0x3424 /* 16bit */
33 #define FD2 0x3428 /* 32bit */
34 #define CG 0x341c /* 32bit */
36 /* Function Disable 1 RCBA 0x3418 */
37 #define PCH_DISABLE_ALWAYS (1 << 0)
38 #define PCH_DISABLE_ADSPD (1 << 1)
39 #define PCH_DISABLE_SATA1 (1 << 2)
40 #define PCH_DISABLE_SMBUS (1 << 3)
41 #define PCH_DISABLE_HD_AUDIO (1 << 4)
42 #define PCH_DISABLE_EHCI2 (1 << 13)
43 #define PCH_DISABLE_LPC (1 << 14)
44 #define PCH_DISABLE_EHCI1 (1 << 15)
45 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
46 #define PCH_DISABLE_THERMAL (1 << 24)
47 #define PCH_DISABLE_SATA2 (1 << 25)
48 #define PCH_DISABLE_XHCI (1 << 27)
50 /* Function Disable 2 RCBA 0x3428 */
51 #define PCH_DISABLE_KT (1 << 4)
52 #define PCH_DISABLE_IDER (1 << 3)
53 #define PCH_DISABLE_MEI2 (1 << 2)
54 #define PCH_DISABLE_MEI1 (1 << 1)
55 #define PCH_ENABLE_DBDF (1 << 0)