1 #ifndef _ASM_X86_AMD_NB_H
2 #define _ASM_X86_AMD_NB_H
6 struct amd_nb_bus_dev_range {
12 extern const struct pci_device_id amd_nb_misc_ids[];
13 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
15 extern bool early_is_amd_nb(u32 value);
16 extern int amd_cache_northbridges(void);
17 extern void amd_flush_garts(void);
18 extern int amd_numa_init(void);
19 extern int amd_get_subcaches(int);
20 extern int amd_set_subcaches(int, int);
27 struct amd_northbridge {
30 struct amd_l3_cache l3_cache;
33 struct amd_northbridge_info {
36 struct amd_northbridge *nb;
38 extern struct amd_northbridge_info amd_northbridges;
40 #define AMD_NB_GART BIT(0)
41 #define AMD_NB_L3_INDEX_DISABLE BIT(1)
42 #define AMD_NB_L3_PARTITIONING BIT(2)
46 static inline u16 amd_nb_num(void)
48 return amd_northbridges.num;
51 static inline bool amd_nb_has_feature(unsigned feature)
53 return ((amd_northbridges.flags & feature) == feature);
56 static inline struct amd_northbridge *node_to_amd_nb(int node)
58 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
63 #define amd_nb_num(x) 0
64 #define amd_nb_has_feature(x) false
65 #define node_to_amd_nb(x) NULL
70 #endif /* _ASM_X86_AMD_NB_H */